MSP430 test cases, stable poking of RAM.

[goodfet] / firmware / apps / jtag / jtag430asm.S

diff --git a/firmware/apps/jtag/jtag430asm.S b/firmware/apps/jtag/jtag430asm.S
index e9fa6f5..39dcb8f 100644 (file)
--- a/firmware/apps/jtag/jtag430asm.S
+++ b/firmware/apps/jtag/jtag430asm.S
@@ -1,16 +1,48 @@
 .globl jtag430_tclk_flashpulses
 .type jtag430_tclk_flashpulses,@function //for linking
 
-
-//! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
+//This detects model, chooses appropriate timing.
 jtag430_tclk_flashpulses:
+       mov &0x0ff0, r14
+       cmp  #0x6cf1, r14       ;Is the chip an MSP430F1xx?
+       jz jtag430_tclk_flashpulses_3mhz
+       jmp jtag430_tclk_flashpulses_16mhz
+       
+// At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz.
+// At 16MHz, 33 to 62 cycles/loop are allowed.
+jtag430_tclk_flashpulses_3mhz:
        mov #0x0031, r14
-pulseloop:     
+pulseloop3:    
        bis.b #2, @r14          ;SETTCLK, 3 cycles
        sub #1, r15             ; 1 cycle
        ;;  1+3+3+1+2=10, within limits
        bic.b #2, @r14          ;CLRTCLK, 3 cycles
        tst r15                 ; 1 cycle
-       jnz pulseloop           ; 2 cycles
+       jnz pulseloop3          ; 2 cycles
+       ret
+
+jtag430_tclk_flashpulses_16mhz:
+       mov #0x0031, r14
+pulseloop16:   
+       bis.b #2, @r14          ;SETTCLK, 3 cycles
+       sub #1, r15             ; 1 cycle
+       ;;  1+3+3+1+2=10, beneath limits,
+
+       ;; +3+2=5, repeat 5 times to get 10+25=35, within limits
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       push r11                ; 3 cycles
+       pop r11                 ; 2 cycles
+       
+       
+       bic.b #2, @r14          ;CLRTCLK, 3 cycles
+       tst r15                 ; 1 cycle
+       jnz pulseloop16         ; 2 cycles
        ret