Reclocked to 3.6834 MHz, exactly twice a standard PC uart.

[goodfet] / firmware / apps / jtag / jtag430asm.S

diff --git a/firmware/apps/jtag/jtag430asm.S b/firmware/apps/jtag/jtag430asm.S
index 2477016..5c7caa2 100644 (file)
--- a/firmware/apps/jtag/jtag430asm.S
+++ b/firmware/apps/jtag/jtag430asm.S
@@ -1,14 +1,16 @@
 .globl jtag430_tclk_flashpulses
 .type jtag430_tclk_flashpulses,@function    /* declare main as a function */
-       
+
+
+//! At 3.68MHz, 7 to 14 cycles/loop are allowed for 257 to 475kHz
 jtag430_tclk_flashpulses:
-       sub #1, r15
-       bis.b #2, &0x0031       ;SETTCLK
-       nop
-       nop
-       nop
-       bic.b #2, &0x0031       ;CLRTCLK
-       tst r15
-       jnz jtag430_tclk_flashpulses
+       mov #0x0031, r14
+pulseloop:     
+       bis.b #2, @r14          ;SETTCLK, 3 cycles
+       sub #1, r15             ; 1 cycle
+       ;;  1+3+3+1+2=10, within limits
+       bic.b #2, @r14          ;CLRTCLK, 3 cycles
+       tst r15                 ; 1 cycle
+       jnz pulseloop           ; 2 cycles
        ret