--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f4xx.c\r
+ * @author MCD Application Team\r
+ * @version V1.0.0\r
+ * @date 19-September-2011\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\r
+ * This file contains the system clock configuration for STM32F4xx devices,\r
+ * and is generated by the clock configuration tool\r
+ * stm32f4xx_Clock_Configuration_V1.0.0.xls\r
+ * \r
+ * 1. This file provides two functions and one global variable to be called from \r
+ * user application:\r
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\r
+ * and Divider factors, AHB/APBx prescalers and Flash settings),\r
+ * depending on the configuration made in the clock xls tool. \r
+ * This function is called at startup just after reset and \r
+ * before branch to main program. This call is made inside\r
+ * the "startup_stm32f4xx.s" file.\r
+ *\r
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
+ * by the user application to setup the SysTick \r
+ * timer or configure other parameters.\r
+ * \r
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
+ * be called whenever the core clock is changed\r
+ * during program execution.\r
+ *\r
+ * 2. After each device reset the HSI (16 MHz) is used as system clock source.\r
+ * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to\r
+ * configure the system clock before to branch to main program.\r
+ *\r
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()\r
+ * function will do nothing and HSI still used as system clock source. User can \r
+ * add some code to deal with this issue inside the SetSysClock() function.\r
+ *\r
+ * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define\r
+ * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or\r
+ * through PLL, and you are using different crystal you have to adapt the HSE\r
+ * value to your own configuration.\r
+ *\r
+ * 5. This file configures the system clock as follows:\r
+ *=============================================================================\r
+ *=============================================================================\r
+ * Supported STM32F4xx device revision | Rev A\r
+ *-----------------------------------------------------------------------------\r
+ * System Clock source | PLL (HSE)\r
+ *-----------------------------------------------------------------------------\r
+ * SYSCLK(Hz) | 168000000\r
+ *-----------------------------------------------------------------------------\r
+ * HCLK(Hz) | 168000000\r
+ *-----------------------------------------------------------------------------\r
+ * AHB Prescaler | 1\r
+ *-----------------------------------------------------------------------------\r
+ * APB1 Prescaler | 4\r
+ *-----------------------------------------------------------------------------\r
+ * APB2 Prescaler | 2\r
+ *-----------------------------------------------------------------------------\r
+ * HSE Frequency(Hz) | 8000000\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_M | 8\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_N | 336\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_P | 2\r
+ *-----------------------------------------------------------------------------\r
+ * PLL_Q | 7\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_N | 192\r
+ *-----------------------------------------------------------------------------\r
+ * PLLI2S_R | 5\r
+ *-----------------------------------------------------------------------------\r
+ * I2S input clock(Hz) | 38400000\r
+ *-----------------------------------------------------------------------------\r
+ * VDD(V) | 3.3\r
+ *-----------------------------------------------------------------------------\r
+ * High Performance mode | Enabled\r
+ *-----------------------------------------------------------------------------\r
+ * Flash Latency(WS) | 5\r
+ *-----------------------------------------------------------------------------\r
+ * Prefetch Buffer | OFF\r
+ *-----------------------------------------------------------------------------\r
+ * Instruction cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Data cache | ON\r
+ *-----------------------------------------------------------------------------\r
+ * Require 48MHz for USB OTG FS, | Enabled\r
+ * SDIO and RNG clock |\r
+ *-----------------------------------------------------------------------------\r
+ *=============================================================================\r
+ ****************************************************************************** \r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F4xx_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f4xx.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM324xG_EVAL board as data memory */\r
+/* #define DATA_IN_ExtSRAM */\r
+\r
+/*!< Uncomment the following line if you need to relocate your vector Table in\r
+ Internal SRAM. */\r
+/* #define VECT_TAB_SRAM */\r
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. \r
+ This value must be a multiple of 0x200. */\r
+\r
+\r
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */\r
+#define PLL_M 8\r
+#define PLL_N 336\r
+\r
+/* SYSCLK = PLL_VCO / PLL_P */\r
+#define PLL_P 2\r
+\r
+/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */\r
+#define PLL_Q 7\r
+\r
+/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N\r
+ I2SCLK = PLLI2S_VCO / PLLI2S_R */\r
+#define PLLI2S_N 192\r
+#define PLLI2S_R 5\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+ uint32_t SystemCoreClock = 168000000;\r
+\r
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+#ifdef DATA_IN_ExtSRAM\r
+ static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F4xx_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the \r
+ * SystemFrequency variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* Reset the RCC clock configuration to the default reset state ------------*/\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset CFGR register */\r
+ RCC->CFGR = 0x00000000;\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset PLLCFGR register */\r
+ RCC->PLLCFGR = 0x24003010;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Disable all interrupts */\r
+ RCC->CIR = 0x00000000;\r
+\r
+#ifdef DATA_IN_ExtSRAM\r
+ SystemInit_ExtMemCtl(); \r
+#endif /* DATA_IN_ExtSRAM */\r
+ \r
+ /* Configure the System clock source, PLL Multiplier and Divider factors, \r
+ AHB/APBx prescalers and Flash settings ----------------------------------*/\r
+ SetSysClock();\r
+\r
+ /* Configure the Vector Table location add offset address ------------------*/\r
+#ifdef VECT_TAB_SRAM\r
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r
+#else\r
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock variable according to Clock Register Values.\r
+ * The SystemCoreClock variable contains the core clock (HCLK), it can\r
+ * be used by the user application to setup the SysTick timer or configure\r
+ * other parameters.\r
+ * \r
+ * @note Each time the core clock (HCLK) changes, this function must be called\r
+ * to update SystemCoreClock variable value. Otherwise, any configuration\r
+ * based on this variable will be incorrect. \r
+ * \r
+ * @note - The system frequency computed by this function is not the real \r
+ * frequency in the chip. It is calculated based on the predefined \r
+ * constant and the selected clock source:\r
+ * \r
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
+ * \r
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
+ * \r
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
+ * \r
+ * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 16 MHz) but the real value may vary depending on the variations\r
+ * in voltage and temperature. \r
+ * \r
+ * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value\r
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real\r
+ * frequency of the crystal used. Otherwise, this function may\r
+ * have wrong result.\r
+ * \r
+ * - The result of this function could be not correct when using fractional\r
+ * value for HSE crystal.\r
+ * \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock source */\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock source */\r
+ SystemCoreClock = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock source */\r
+\r
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r
+ SYSCLK = PLL_VCO / PLL_P\r
+ */ \r
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r
+ \r
+ if (pllsource != 0)\r
+ {\r
+ /* HSE used as PLL clock source */\r
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r
+ }\r
+ else\r
+ {\r
+ /* HSI used as PLL clock source */\r
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); \r
+ }\r
+\r
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r
+ SystemCoreClock = pllvco/pllp;\r
+ break;\r
+ default:\r
+ SystemCoreClock = HSI_VALUE;\r
+ break;\r
+ }\r
+ /* Compute HCLK frequency --------------------------------------------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+ /* HCLK frequency */\r
+ SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors, \r
+ * AHB/APBx prescalers and Flash settings\r
+ * @Note This function should be called only once the RCC clock configuration \r
+ * is reset to the default reset state (done in SystemInit() function). \r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+/******************************************************************************/\r
+/* PLL (clocked by HSE) used as System clock source */\r
+/******************************************************************************/\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable high performance mode, System frequency up to 168 MHz */\r
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+ PWR->CR |= PWR_CR_PMODE; \r
+\r
+ /* HCLK = SYSCLK / 1*/\r
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK / 2*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;\r
+ \r
+ /* PCLK1 = HCLK / 4*/\r
+ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;\r
+\r
+ /* Configure the main PLL */\r
+ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |\r
+ (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);\r
+\r
+ /* Enable the main PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till the main PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+ \r
+ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */\r
+ FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;\r
+\r
+ /* Select the main PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till the main PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock\r
+ configuration. User can add here some code to deal with this error */\r
+ }\r
+\r
+/******************************************************************************/\r
+/* I2S clock configuration */\r
+/******************************************************************************/\r
+ /* PLLI2S clock used as I2S clock source */\r
+ RCC->CFGR &= ~RCC_CFGR_I2SSRC;\r
+\r
+ /* Configure PLLI2S */\r
+ RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);\r
+\r
+ /* Enable PLLI2S */\r
+ RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);\r
+\r
+ /* Wait till PLLI2S is ready */\r
+ while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Setup the external memory controller. Called in startup_stm32f4xx.s \r
+ * before jump to __main\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller.\r
+ * Called in startup_stm32f4xx.s before jump to main.\r
+ * This function configures the external SRAM mounted on STM324xG_EVAL board\r
+ * This SRAM will be used as program data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit_ExtMemCtl(void)\r
+{\r
+/*-- GPIOs Configuration -----------------------------------------------------*/\r
+/*\r
+ +-------------------+--------------------+------------------+------------------+\r
+ + SRAM pins assignment +\r
+ +-------------------+--------------------+------------------+------------------+\r
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | \r
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | \r
+ | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | \r
+ | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | \r
+ | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | \r
+ | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | \r
+ | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | \r
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+\r
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | \r
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | \r
+ | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+\r
+ | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |\r
+ | | PE15 <-> FSMC_D12 |\r
+ +-------------------+--------------------+\r
+*/\r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\r
+ RCC->AHB1ENR = 0x00000078;\r
+ \r
+ /* Connect PDx pins to FSMC Alternate function */\r
+ GPIOD->AFR[0] = 0x00cc00cc;\r
+ GPIOD->AFR[1] = 0xcc0ccccc;\r
+ /* Configure PDx pins in Alternate function mode */ \r
+ GPIOD->MODER = 0xaaaa0a0a;\r
+ /* Configure PDx pins speed to 100 MHz */ \r
+ GPIOD->OSPEEDR = 0xffff0f0f;\r
+ /* Configure PDx pins Output type to push-pull */ \r
+ GPIOD->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PDx pins */ \r
+ GPIOD->PUPDR = 0x00000000;\r
+\r
+ /* Connect PEx pins to FSMC Alternate function */\r
+ GPIOE->AFR[0] = 0xc00cc0cc;\r
+ GPIOE->AFR[1] = 0xcccccccc;\r
+ /* Configure PEx pins in Alternate function mode */ \r
+ GPIOE->MODER = 0xaaaa828a;\r
+ /* Configure PEx pins speed to 100 MHz */ \r
+ GPIOE->OSPEEDR = 0xffffc3cf;\r
+ /* Configure PEx pins Output type to push-pull */ \r
+ GPIOE->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PEx pins */ \r
+ GPIOE->PUPDR = 0x00000000;\r
+\r
+ /* Connect PFx pins to FSMC Alternate function */\r
+ GPIOF->AFR[0] = 0x00cccccc;\r
+ GPIOF->AFR[1] = 0xcccc0000;\r
+ /* Configure PFx pins in Alternate function mode */ \r
+ GPIOF->MODER = 0xaa000aaa;\r
+ /* Configure PFx pins speed to 100 MHz */ \r
+ GPIOF->OSPEEDR = 0xff000fff;\r
+ /* Configure PFx pins Output type to push-pull */ \r
+ GPIOF->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PFx pins */ \r
+ GPIOF->PUPDR = 0x00000000;\r
+\r
+ /* Connect PGx pins to FSMC Alternate function */\r
+ GPIOG->AFR[0] = 0x00cccccc;\r
+ GPIOG->AFR[1] = 0x000000c0;\r
+ /* Configure PGx pins in Alternate function mode */ \r
+ GPIOG->MODER = 0x00080aaa;\r
+ /* Configure PGx pins speed to 100 MHz */ \r
+ GPIOG->OSPEEDR = 0x000c0fff;\r
+ /* Configure PGx pins Output type to push-pull */ \r
+ GPIOG->OTYPER = 0x00000000;\r
+ /* No pull-up, pull-down for PGx pins */ \r
+ GPIOG->PUPDR = 0x00000000;\r
+ \r
+/*-- FSMC Configuration ------------------------------------------------------*/\r
+ /* Enable the FSMC interface clock */\r
+ RCC->AHB3ENR = 0x00000001;\r
+\r
+ /* Configure and enable Bank1_SRAM2 */\r
+ FSMC_Bank1->BTCR[2] = 0x00001015;\r
+ FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;\r
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;\r
+/*\r
+ Bank1_SRAM2 is configured as follow:\r
+\r
+ p.FSMC_AddressSetupTime = 3;//0;\r
+ p.FSMC_AddressHoldTime = 0;\r
+ p.FSMC_DataSetupTime = 6;//4;\r
+ p.FSMC_BusTurnAroundDuration = 1;\r
+ p.FSMC_CLKDivision = 0;\r
+ p.FSMC_DataLatency = 0;\r
+ p.FSMC_AccessMode = FSMC_AccessMode_A;\r
+\r
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;\r
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;\r
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;\r
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; \r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;\r
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;\r
+*/\r
+ \r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
+\r
projects / goodfet / blobdiff