git.rot13.org Git - linux/blob - arch/arm/boot/dts/tegra20-ventana.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/input/input.h>
   5 #include "tegra20.dtsi"
   6
   7 / {
   8         model = "NVIDIA Tegra20 Ventana evaluation board";
   9         compatible = "nvidia,ventana", "nvidia,tegra20";
  10
  11         aliases {
  12                 rtc0 = "/i2c@7000d000/tps6586x@34";
  13                 rtc1 = "/rtc@7000e000";
  14                 serial0 = &uartd;
  15         };
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19                 bootargs = "mem=1024M@0M usbcore.old_scheme_first=1";
  20         };
  21
  22         memory@0 {
  23                 reg = <0x00000000 0x40000000>;
  24         };
  25
  26         host1x@50000000 {
  27                 dc@54200000 {
  28                         rgb {
  29                                 status = "okay";
  30
  31                                 nvidia,panel = <&panel>;
  32
  33                         };
  34                 };
  35
  36                 hdmi@54280000 {
  37                         status = "okay";
  38
  39                         vdd-supply = <&hdmi_vdd_reg>;
  40                         pll-supply = <&hdmi_pll_reg>;
  41
  42                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  43                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  44                                 GPIO_ACTIVE_HIGH>;
  45                 };
  46         };
  47
  48         pinmux@70000014 {
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&state_default>;
  51
  52                 state_default: pinmux {
  53                         ata {
  54                                 nvidia,pins = "ata";
  55                                 nvidia,function = "ide";
  56                         };
  57                         atb {
  58                                 nvidia,pins = "atb", "gma", "gme";
  59                                 nvidia,function = "sdio4";
  60                         };
  61                         atc {
  62                                 nvidia,pins = "atc";
  63                                 nvidia,function = "nand";
  64                         };
  65                         atd {
  66                                 nvidia,pins = "atd", "ate", "gmb", "spia",
  67                                         "spib", "spic";
  68                                 nvidia,function = "gmi";
  69                         };
  70                         cdev1 {
  71                                 nvidia,pins = "cdev1";
  72                                 nvidia,function = "plla_out";
  73                         };
  74                         cdev2 {
  75                                 nvidia,pins = "cdev2";
  76                                 nvidia,function = "pllp_out4";
  77                         };
  78                         crtp {
  79                                 nvidia,pins = "crtp", "lm1";
  80                                 nvidia,function = "crt";
  81                         };
  82                         csus {
  83                                 nvidia,pins = "csus";
  84                                 nvidia,function = "vi_sensor_clk";
  85                         };
  86                         dap1 {
  87                                 nvidia,pins = "dap1";
  88                                 nvidia,function = "dap1";
  89                         };
  90                         dap2 { /* touch */
  91                                 nvidia,pins = "dap2";
  92                                 nvidia,function = "dap2";
  93                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  94                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  95                         };
  96                         dap3 {
  97                                 nvidia,pins = "dap3";
  98                                 nvidia,function = "dap3";
  99                         };
 100                         dap4 {
 101                                 nvidia,pins = "dap4";
 102                                 nvidia,function = "dap4";
 103                         };
 104                         dta {
 105                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
 106                                 nvidia,function = "vi";
 107                         };
 108                         dtf {
 109                                 nvidia,pins = "dtf";
 110                                 nvidia,function = "i2c3";
 111                         };
 112                         gmc {
 113                                 nvidia,pins = "gmc";
 114                                 nvidia,function = "uartd";
 115                         };
 116                         gmd {
 117                                 nvidia,pins = "gmd";
 118                                 nvidia,function = "sflash";
 119                         };
 120                         gpu {
 121                                 nvidia,pins = "gpu";
 122                                 nvidia,function = "pwm";
 123                         };
 124                         gpu7 {
 125                                 nvidia,pins = "gpu7";
 126                                 nvidia,function = "rtck";
 127                         };
 128                         gpv {
 129                                 nvidia,pins = "gpv", "slxa", "slxk";
 130                                 nvidia,function = "pcie";
 131                         };
 132                         hdint {
 133                                 nvidia,pins = "hdint";
 134                                 nvidia,function = "hdmi";
 135                         };
 136                         i2cp {
 137                                 nvidia,pins = "i2cp";
 138                                 nvidia,function = "i2cp";
 139                         };
 140                         irrx {
 141                                 nvidia,pins = "irrx", "irtx";
 142                                 nvidia,function = "uartb";
 143                         };
 144                         kbca {
 145                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 146                                         "kbcf";
 147                                 nvidia,function = "kbc";
 148                         };
 149                         kbce { /* touch */
 150                                 nvidia,pins = "kbce";
 151                                 nvidia,function = "kbc";
 152                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 153                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 154                         };
 155                         lcsn {
 156                                 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
 157                                         "lsdi", "lvp0";
 158                                 nvidia,function = "rsvd4";
 159                         };
 160                         ld0 {
 161                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
 162                                         "ld5", "ld6", "ld7", "ld8", "ld9",
 163                                         "ld10", "ld11", "ld12", "ld13", "ld14",
 164                                         "ld15", "ld16", "ld17", "ldi", "lhp0",
 165                                         "lhp1", "lhp2", "lhs", "lpp", "lpw0",
 166                                         "lpw2", "lsc0", "lsc1", "lsck", "lsda",
 167                                         "lspi", "lvp1", "lvs";
 168                                 nvidia,function = "displaya";
 169                         };
 170                         owc {
 171                                 nvidia,pins = "owc", "spdi", "spdo", "uac";
 172                                 nvidia,function = "rsvd2";
 173                         };
 174                         pmc {
 175                                 nvidia,pins = "pmc";
 176                                 nvidia,function = "pwr_on";
 177                         };
 178                         rm {
 179                                 nvidia,pins = "rm";
 180                                 nvidia,function = "i2c1";
 181                         };
 182                         sdb {
 183                                 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
 184                                 nvidia,function = "sdio3";
 185                         };
 186                         sdio1 {
 187                                 nvidia,pins = "sdio1";
 188                                 nvidia,function = "sdio1";
 189                         };
 190                         slxd {
 191                                 nvidia,pins = "slxd";
 192                                 nvidia,function = "spdif";
 193                         };
 194                         spid { /* touch */
 195                                 nvidia,pins = "spid", "spif";
 196                                 nvidia,function = "spi1";
 197                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 198                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 199                         };
 200                         spie { /* touch */
 201                                 nvidia,pins = "spie";
 202                                 nvidia,function = "spi1";
 203                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 204                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 205                         };
 206                         spig {
 207                                 nvidia,pins = "spig", "spih";
 208                                 nvidia,function = "spi2_alt";
 209                         };
 210                         uaa {
 211                                 nvidia,pins = "uaa", "uab", "uda";
 212                                 nvidia,function = "ulpi";
 213                         };
 214                         uad {
 215                                 nvidia,pins = "uad";
 216                                 nvidia,function = "irda";
 217                         };
 218                         uca {
 219                                 nvidia,pins = "uca", "ucb";
 220                                 nvidia,function = "uartc";
 221                         };
 222                         conf_ata {
 223                                 nvidia,pins = "ata", "atb", "atc", "atd",
 224                                         "cdev1", "cdev2", "dap1", "dap2",
 225                                         "dap4", "ddc", "dtf", "gma", "gmc",
 226                                         "gme", "gpu", "gpu7", "i2cp", "irrx",
 227                                         "irtx", "pta", "rm", "sdc", "sdd",
 228                                         "slxc", "slxd", "slxk", "spdi", "spdo",
 229                                         "uac", "uad", "uca", "ucb", "uda";
 230                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 231                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 232                         };
 233                         conf_ate {
 234                                 nvidia,pins = "ate", "csus", "dap3", "gmd",
 235                                         "gpv", "owc", "spia", "spib", "spic",
 236                                         "spid", "spie", "spig";
 237                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 238                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 239                         };
 240                         conf_ck32 {
 241                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
 242                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
 243                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 244                         };
 245                         conf_crtp {
 246                                 nvidia,pins = "crtp", "gmb", "slxa", "spih";
 247                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 248                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 249                         };
 250                         conf_dta {
 251                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
 252                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 253                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 254                         };
 255                         conf_dte {
 256                                 nvidia,pins = "dte", "spif";
 257                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 258                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 259                         };
 260                         conf_hdint {
 261                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
 262                                         "lpw1", "lsck", "lsda", "lsdi", "lvp0";
 263                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 264                         };
 265                         conf_kbca {
 266                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 267                                         "kbce", "kbcf", "sdio1", "uaa", "uab";
 268                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 269                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 270                         };
 271                         conf_lc {
 272                                 nvidia,pins = "lc", "ls";
 273                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 274                         };
 275                         conf_ld0 {
 276                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
 277                                         "ld5", "ld6", "ld7", "ld8", "ld9",
 278                                         "ld10", "ld11", "ld12", "ld13", "ld14",
 279                                         "ld15", "ld16", "ld17", "ldi", "lhp0",
 280                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
 281                                         "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
 282                                         "lvp1", "lvs", "pmc", "sdb";
 283                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 284                         };
 285                         conf_ld17_0 {
 286                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
 287                                         "ld23_22";
 288                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 289                         };
 290                         drive_sdio1 {
 291                                 nvidia,pins = "drive_sdio1";
 292                                 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
 293                                 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
 294                                 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
 295                                 nvidia,pull-down-strength = <31>;
 296                                 nvidia,pull-up-strength = <31>;
 297                                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
 298                                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
 299                         };
 300                 };
 301
 302                 state_i2cmux_ddc: pinmux_i2cmux_ddc {
 303                         ddc {
 304                                 nvidia,pins = "ddc";
 305                                 nvidia,function = "i2c2";
 306                         };
 307                         pta {
 308                                 nvidia,pins = "pta";
 309                                 nvidia,function = "rsvd4";
 310                         };
 311                 };
 312
 313                 state_i2cmux_pta: pinmux_i2cmux_pta {
 314                         ddc {
 315                                 nvidia,pins = "ddc";
 316                                 nvidia,function = "rsvd4";
 317                         };
 318                         pta {
 319                                 nvidia,pins = "pta";
 320                                 nvidia,function = "i2c2";
 321                         };
 322                 };
 323
 324                 state_i2cmux_idle: pinmux_i2cmux_idle {
 325                         ddc {
 326                                 nvidia,pins = "ddc";
 327                                 nvidia,function = "rsvd4";
 328                         };
 329                         pta {
 330                                 nvidia,pins = "pta";
 331                                 nvidia,function = "rsvd4";
 332                         };
 333                 };
 334         };
 335
 336         i2s@70002800 {
 337                 status = "okay";
 338         };
 339
 340         serial@70006300 {
 341                 status = "okay";
 342         };
 343
 344         pwm: pwm@7000a000 {
 345                 status = "okay";
 346         };
 347
 348         i2c@7000c000 {
 349                 status = "okay";
 350                 clock-frequency = <400000>;
 351
 352                 wm8903: wm8903@1a {
 353                         compatible = "wlf,wm8903";
 354                         reg = <0x1a>;
 355                         interrupt-parent = <&gpio>;
 356                         interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 357
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360
 361                         micdet-cfg = <0>;
 362                         micdet-delay = <100>;
 363                         gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
 364                 };
 365
 366                 /* ALS and proximity sensor */
 367                 isl29018@44 {
 368                         compatible = "isil,isl29018";
 369                         reg = <0x44>;
 370                         interrupt-parent = <&gpio>;
 371                         interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
 372                 };
 373         };
 374
 375         i2c@7000c400 { /* i2c2 */
 376                 status = "okay";
 377                 clock-frequency = <100000>;
 378         };
 379
 380         i2cmux {
 381                 compatible = "i2c-mux-pinctrl";
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384
 385                 i2c-parent = <&{/i2c@7000c400}>;
 386
 387                 pinctrl-names = "ddc", "pta", "idle";
 388                 pinctrl-0 = <&state_i2cmux_ddc>;
 389                 pinctrl-1 = <&state_i2cmux_pta>;
 390                 pinctrl-2 = <&state_i2cmux_idle>;
 391
 392                 hdmi_ddc: i2c@0 {
 393                         reg = <0>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                 };
 397
 398                 lvds_ddc: i2c@1 {
 399                         reg = <1>;
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                 };
 403         };
 404
 405         i2c@7000c500 { /* i2c3 */
 406                 status = "okay";
 407                 clock-frequency = <100000>; /* 400000 */
 408         };
 409
 410         i2c@7000d000 { /* DVC according to Tegra2 TRM */
 411                 status = "okay";
 412                 clock-frequency = <400000>;
 413
 414                 pmic: tps6586x@34 {
 415                         compatible = "ti,tps6586x";
 416                         reg = <0x34>;
 417                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 418
 419                         ti,system-power-controller;
 420
 421                         #gpio-cells = <2>;
 422                         gpio-controller;
 423
 424                         sys-supply = <&vdd_5v0_reg>;
 425                         vin-sm0-supply = <&sys_reg>;
 426                         vin-sm1-supply = <&sys_reg>;
 427                         vin-sm2-supply = <&sys_reg>;
 428                         vinldo01-supply = <&sm2_reg>;
 429                         vinldo23-supply = <&sm2_reg>;
 430                         vinldo4-supply = <&sm2_reg>;
 431                         vinldo678-supply = <&sm2_reg>;
 432                         vinldo9-supply = <&sm2_reg>;
 433
 434                         regulators {
 435                                 sys_reg: sys {
 436                                         regulator-name = "vdd_sys";
 437                                         regulator-always-on;
 438                                 };
 439
 440                                 core_vdd_reg: sm0 {
 441                                         regulator-name = "vdd_sm0,vdd_core";
 442                                         regulator-min-microvolt = <1200000>;
 443                                         regulator-max-microvolt = <1300000>;
 444                                         regulator-coupled-with = <&rtc_vdd_reg>;
 445                                         regulator-coupled-max-spread = <150000>;
 446                                         regulator-always-on;
 447                                 };
 448
 449                                 cpu_vdd_reg: sm1 {
 450                                         regulator-name = "vdd_sm1,vdd_cpu";
 451                                         regulator-min-microvolt = <750000>;
 452                                         regulator-max-microvolt = <1125000>;
 453                                         regulator-always-on;
 454                                 };
 455
 456                                 sm2_reg: sm2 {
 457                                         regulator-name = "vdd_sm2,vin_ldo*";
 458                                         regulator-min-microvolt = <3700000>;
 459                                         regulator-max-microvolt = <3700000>;
 460                                         regulator-always-on;
 461                                 };
 462
 463                                 /* LDO0 is not connected to anything */
 464
 465                                 ldo1 {
 466                                         regulator-name = "vdd_ldo1,avdd_pll*";
 467                                         regulator-min-microvolt = <1100000>;
 468                                         regulator-max-microvolt = <1100000>;
 469                                         regulator-always-on;
 470                                 };
 471
 472                                 rtc_vdd_reg: ldo2 {
 473                                         regulator-name = "vdd_ldo2,vdd_rtc";
 474                                         regulator-min-microvolt = <1200000>;
 475                                         regulator-max-microvolt = <1300000>;
 476                                         regulator-coupled-with = <&core_vdd_reg>;
 477                                         regulator-coupled-max-spread = <150000>;
 478                                         regulator-always-on;
 479                                 };
 480
 481                                 ldo3 {
 482                                         regulator-name = "vdd_ldo3,avdd_usb*";
 483                                         regulator-min-microvolt = <3300000>;
 484                                         regulator-max-microvolt = <3300000>;
 485                                         regulator-always-on;
 486                                 };
 487
 488                                 ldo4 {
 489                                         regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
 490                                         regulator-min-microvolt = <1800000>;
 491                                         regulator-max-microvolt = <1800000>;
 492                                         regulator-always-on;
 493                                 };
 494
 495                                 ldo5 {
 496                                         regulator-name = "vdd_ldo5,vcore_mmc";
 497                                         regulator-min-microvolt = <2850000>;
 498                                         regulator-max-microvolt = <2850000>;
 499                                         regulator-always-on;
 500                                 };
 501
 502                                 ldo6 {
 503                                         regulator-name = "vdd_ldo6,avdd_vdac";
 504                                         regulator-min-microvolt = <1800000>;
 505                                         regulator-max-microvolt = <1800000>;
 506                                 };
 507
 508                                 hdmi_vdd_reg: ldo7 {
 509                                         regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
 510                                         regulator-min-microvolt = <3300000>;
 511                                         regulator-max-microvolt = <3300000>;
 512                                 };
 513
 514                                 hdmi_pll_reg: ldo8 {
 515                                         regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 516                                         regulator-min-microvolt = <1800000>;
 517                                         regulator-max-microvolt = <1800000>;
 518                                 };
 519
 520                                 ldo9 {
 521                                         regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
 522                                         regulator-min-microvolt = <2850000>;
 523                                         regulator-max-microvolt = <2850000>;
 524                                         regulator-always-on;
 525                                 };
 526
 527                                 ldo_rtc {
 528                                         regulator-name = "vdd_rtc_out,vdd_cell";
 529                                         regulator-min-microvolt = <3300000>;
 530                                         regulator-max-microvolt = <3300000>;
 531                                         regulator-always-on;
 532                                 };
 533                         };
 534                 };
 535
 536                 temperature-sensor@4c {
 537                         compatible = "onnn,nct1008";
 538                         reg = <0x4c>;
 539                 };
 540         };
 541
 542         pmc@7000e400 {
 543                 nvidia,invert-interrupt;
 544                 nvidia,suspend-mode = <1>;
 545                 nvidia,cpu-pwr-good-time = <2000>;
 546                 nvidia,cpu-pwr-off-time = <100>;
 547                 nvidia,core-pwr-good-time = <3845 3845>;
 548                 nvidia,core-pwr-off-time = <458>;
 549                 nvidia,sys-clock-req-active-high;
 550         };
 551
 552         usb@c5000000 {
 553                 status = "okay";
 554         };
 555
 556         usb-phy@c5000000 {
 557                 status = "okay";
 558         };
 559
 560         usb@c5004000 {
 561                 status = "okay";
 562                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
 563                         GPIO_ACTIVE_LOW>;
 564         };
 565
 566         usb-phy@c5004000 {
 567                 status = "okay";
 568                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
 569                         GPIO_ACTIVE_LOW>;
 570         };
 571
 572         usb@c5008000 {
 573                 status = "okay";
 574         };
 575
 576         usb-phy@c5008000 {
 577                 status = "okay";
 578         };
 579
 580         sdhci@c8000000 {
 581                 status = "okay";
 582                 bus-width = <8>;
 583                 keep-power-in-suspend;
 584         };
 585
 586         sdhci@c8000400 {
 587                 status = "okay";
 588                 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
 589                 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
 590                 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
 591                 bus-width = <4>;
 592         };
 593
 594         sdhci@c8000600 {
 595                 status = "okay";
 596                 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
 597                 bus-width = <8>;
 598                 non-removable;
 599         };
 600
 601         backlight: backlight {
 602                 compatible = "pwm-backlight";
 603
 604                 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 605                 power-supply = <&vdd_bl_reg>;
 606                 pwms = <&pwm 2 5000000>;
 607
 608                 brightness-levels = <0 4 8 16 32 64 128 255>;
 609                 default-brightness-level = <6>;
 610         };
 611
 612         clocks {
 613                 compatible = "simple-bus";
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616
 617                 clk32k_in: clock@0 {
 618                         compatible = "fixed-clock";
 619                         reg = <0>;
 620                         #clock-cells = <0>;
 621                         clock-frequency = <32768>;
 622                 };
 623         };
 624
 625         gpio-keys {
 626                 compatible = "gpio-keys";
 627
 628                 www {
 629                         label = "www";
 630                         gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
 631                         linux,code = <KEY_WWW>;
 632                 };
 633
 634                 homepage {
 635                         label = "homepage";
 636                         gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>;
 637                         linux,code = <KEY_HOMEPAGE>;
 638                 };
 639
 640                 back {
 641                         label = "back";
 642                         gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
 643                         linux,code = <KEY_BACK>;
 644                 };
 645
 646                 rotation {
 647                         label = "rotation";
 648                         gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_HIGH>;
 649                         linux,code = <KEY_ROTATE_DISPLAY>;
 650                 };
 651
 652                 volumedown {
 653                         label = "volumedown";
 654                         gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
 655                         linux,code = <KEY_VOLUMEDOWN>;
 656                 };
 657
 658                 volumeup {
 659                         label = "volumeup";
 660                         gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
 661                         linux,code = <KEY_VOLUMEUP>;
 662                 };
 663
 664                 power {
 665                         label = "Power";
 666                         gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* original */
 667                         linux,code = <KEY_POWER>;
 668                         wakeup-source;
 669                 };
 670
 671                 power2 {
 672                         label = "Power2";
 673                         gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_LOW>;
 674                         linux,code = <KEY_POWER2>;
 675                         wakeup-source;
 676                 };
 677
 678    /* Charl5es 0508 start
 679     * wakeup source
 680     *
 681     * PC7 EXIT_LP0
 682     * PV2 AP_ONKEY
 683     * PV3 AP_ACOK
 684     * PI3 POWEROFF_AP
 685     */
 686
 687         };
 688
 689         panel: panel {
 690                 compatible = "lg,lp101wx1", "simple-panel";
 691
 692                 power-supply = <&vdd_pnl_reg>;
 693                 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
 694
 695                 backlight = <&backlight>;
 696                 ddc-i2c-bus = <&lvds_ddc>;
 697
 698                                 x-display-timings {
 699                                         timing@0 {
 700                                                 /* XXX tegra_dc_mode ventana_panel_modes -- works for u-boot */
 701                                                 clock-frequency = <72072000>;
 702                                                 hactive = <1280>;
 703                                                 vactive = <800>;
 704                                                 hback-porch = <72>;
 705                                                 hfront-porch = <48>;
 706                                                 hsync-len = <32>;
 707                                                 vback-porch = <22>;
 708                                                 vfront-porch = <3>;
 709                                                 vsync-len = <7>;
 710                                                 hsync-active = <1>;
 711                                         };
 712                                 };
 713         };
 714
 715         regulators {
 716                 compatible = "simple-bus";
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719
 720                 vdd_5v0_reg: regulator@0 {
 721                         compatible = "regulator-fixed";
 722                         reg = <0>;
 723                         regulator-name = "vdd_5v0";
 724                         regulator-min-microvolt = <5000000>;
 725                         regulator-max-microvolt = <5000000>;
 726                         regulator-always-on;
 727                 };
 728
 729                 regulator@1 {
 730                         compatible = "regulator-fixed";
 731                         reg = <1>;
 732                         regulator-name = "vdd_1v5";
 733                         regulator-min-microvolt = <1500000>;
 734                         regulator-max-microvolt = <1500000>;
 735                         gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 736                 };
 737
 738                 regulator@2 {
 739                         compatible = "regulator-fixed";
 740                         reg = <2>;
 741                         regulator-name = "vdd_1v2";
 742                         regulator-min-microvolt = <1200000>;
 743                         regulator-max-microvolt = <1200000>;
 744                         gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
 745                         enable-active-high;
 746                 };
 747
 748                 vdd_pnl_reg: regulator@3 {
 749                         compatible = "regulator-fixed";
 750                         reg = <3>;
 751                         regulator-name = "vdd_pnl";
 752                         regulator-min-microvolt = <2800000>;
 753                         regulator-max-microvolt = <2800000>;
 754                         gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
 755                         enable-active-high;
 756                 };
 757
 758                 vdd_bl_reg: regulator@4 {
 759                         compatible = "regulator-fixed";
 760                         reg = <4>;
 761                         regulator-name = "vdd_bl";
 762                         regulator-min-microvolt = <2800000>;
 763                         regulator-max-microvolt = <2800000>;
 764                         gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
 765                         enable-active-high;
 766                 };
 767         };
 768
 769         sound {
 770                 compatible = "nvidia,tegra-audio-wm8903-ventana",
 771                              "nvidia,tegra-audio-wm8903";
 772                 nvidia,model = "NVIDIA Tegra Ventana";
 773
 774                 nvidia,audio-routing =
 775                         "Headphone Jack", "HPOUTR",
 776                         "Headphone Jack", "HPOUTL",
 777                         "Int Spk", "ROP",
 778                         "Int Spk", "RON",
 779                         "Int Spk", "LOP",
 780                         "Int Spk", "LON",
 781                         "Mic Jack", "MICBIAS",
 782                         "IN1L", "Mic Jack";
 783
 784                 nvidia,i2s-controller = <&tegra_i2s1>;
 785                 nvidia,audio-codec = <&wm8903>;
 786
 787                 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
 788                 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; /* ok */
 789 /*
 790                 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
 791                         GPIO_ACTIVE_HIGH>;
 792 */
 793                 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(W, 3) /* fixed */
 794                         GPIO_ACTIVE_HIGH>;
 795
 796                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
 797                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
 798                          <&tegra_car TEGRA20_CLK_CDEV1>;
 799                 clock-names = "pll_a", "pll_a_out0", "mclk";
 800         };
 801
 802         cpus {
 803                 cpu0: cpu@0 {
 804                         cpu-supply = <&cpu_vdd_reg>;
 805                         core-supply = <&core_vdd_reg>;
 806                         rtc-supply = <&rtc_vdd_reg>;
 807                 };
 808         };
 809 };