1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&lic>;
15 device_type = "memory";
20 compatible = "mmio-sram";
21 reg = <0x40000000 0x40000>;
24 ranges = <0 0x40000000 0x40000>;
27 reg = <0x400 0x3fc00>;
33 compatible = "nvidia,tegra20-host1x", "simple-bus";
34 reg = <0x50000000 0x00024000>;
35 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
36 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
37 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
38 resets = <&tegra_car 28>;
39 reset-names = "host1x";
44 ranges = <0x54000000 0x54000000 0x04000000>;
47 compatible = "nvidia,tegra20-mpe";
48 reg = <0x54040000 0x00040000>;
49 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
50 clocks = <&tegra_car TEGRA20_CLK_MPE>;
51 resets = <&tegra_car 60>;
58 compatible = "nvidia,tegra20-vi";
59 reg = <0x54080000 0x00040000>;
60 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
61 clocks = <&tegra_car TEGRA20_CLK_VI>;
62 resets = <&tegra_car 20>;
69 compatible = "nvidia,tegra20-epp";
70 reg = <0x540c0000 0x00040000>;
71 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&tegra_car TEGRA20_CLK_EPP>;
73 resets = <&tegra_car 19>;
80 compatible = "nvidia,tegra20-isp";
81 reg = <0x54100000 0x00040000>;
82 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&tegra_car TEGRA20_CLK_ISP>;
84 resets = <&tegra_car 23>;
91 compatible = "nvidia,tegra20-gr2d";
92 reg = <0x54140000 0x00040000>;
93 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
95 resets = <&tegra_car 21>;
102 compatible = "nvidia,tegra20-gr3d";
103 reg = <0x54180000 0x00040000>;
104 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
105 resets = <&tegra_car 24>;
112 compatible = "nvidia,tegra20-dc";
113 reg = <0x54200000 0x00040000>;
114 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
116 <&tegra_car TEGRA20_CLK_PLL_P>;
117 clock-names = "dc", "parent";
118 resets = <&tegra_car 27>;
131 compatible = "nvidia,tegra20-dc";
132 reg = <0x54240000 0x00040000>;
133 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
135 <&tegra_car TEGRA20_CLK_PLL_P>;
136 clock-names = "dc", "parent";
137 resets = <&tegra_car 26>;
150 compatible = "nvidia,tegra20-hdmi";
151 reg = <0x54280000 0x00040000>;
152 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
154 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
155 clock-names = "hdmi", "parent";
156 resets = <&tegra_car 51>;
157 reset-names = "hdmi";
162 compatible = "nvidia,tegra20-tvo";
163 reg = <0x542c0000 0x00040000>;
164 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&tegra_car TEGRA20_CLK_TVO>;
170 compatible = "nvidia,tegra20-dsi";
171 reg = <0x54300000 0x00040000>;
172 clocks = <&tegra_car TEGRA20_CLK_DSI>;
173 resets = <&tegra_car 48>;
180 compatible = "arm,cortex-a9-twd-timer";
181 interrupt-parent = <&intc>;
182 reg = <0x50040600 0x20>;
183 interrupts = <GIC_PPI 13
184 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
185 clocks = <&tegra_car TEGRA20_CLK_TWD>;
188 intc: interrupt-controller@50041000 {
189 compatible = "arm,cortex-a9-gic";
190 reg = <0x50041000 0x1000
192 interrupt-controller;
193 #interrupt-cells = <3>;
194 interrupt-parent = <&intc>;
197 cache-controller@50043000 {
198 compatible = "arm,pl310-cache";
199 reg = <0x50043000 0x1000>;
200 arm,data-latency = <5 5 2>;
201 arm,tag-latency = <4 4 2>;
206 lic: interrupt-controller@60004000 {
207 compatible = "nvidia,tegra20-ictlr";
208 reg = <0x60004000 0x100>,
212 interrupt-controller;
213 #interrupt-cells = <3>;
214 interrupt-parent = <&intc>;
218 compatible = "nvidia,tegra20-timer";
219 reg = <0x60005000 0x60>;
220 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
227 tegra_car: clock@60006000 {
228 compatible = "nvidia,tegra20-car";
229 reg = <0x60006000 0x1000>;
234 flow-controller@60007000 {
235 compatible = "nvidia,tegra20-flowctrl";
236 reg = <0x60007000 0x1000>;
239 apbdma: dma@6000a000 {
240 compatible = "nvidia,tegra20-apbdma";
241 reg = <0x6000a000 0x1200>;
242 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
259 resets = <&tegra_car 34>;
265 compatible = "nvidia,tegra20-ahb";
266 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
269 gpio: gpio@6000d000 {
270 compatible = "nvidia,tegra20-gpio";
271 reg = <0x6000d000 0x1000>;
272 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
281 #interrupt-cells = <2>;
282 interrupt-controller;
284 gpio-ranges = <&pinmux 0 0 224>;
289 compatible = "nvidia,tegra20-vde";
290 reg = <0x6001a000 0x1000 /* Syntax Engine */
291 0x6001b000 0x1000 /* Video Bitstream Engine */
292 0x6001c000 0x100 /* Macroblock Engine */
293 0x6001c200 0x100 /* Post-processing Engine */
294 0x6001c400 0x100 /* Motion Compensation Engine */
295 0x6001c600 0x100 /* Transform Engine */
296 0x6001c800 0x100 /* Pixel prediction block */
297 0x6001ca00 0x100 /* Video DMA */
298 0x6001d800 0x300>; /* Video frame controls */
299 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
300 "tfe", "ppb", "vdma", "frameid";
301 iram = <&vde_pool>; /* IRAM region */
302 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
303 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
304 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
305 interrupt-names = "sync-token", "bsev", "sxe";
306 clocks = <&tegra_car TEGRA20_CLK_VDE>;
307 reset-names = "vde", "mc";
308 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
312 compatible = "nvidia,tegra20-apbmisc";
313 reg = <0x70000800 0x64 /* Chip revision */
314 0x70000008 0x04>; /* Strapping options */
317 pinmux: pinmux@70000014 {
318 compatible = "nvidia,tegra20-pinmux";
319 reg = <0x70000014 0x10 /* Tri-state registers */
320 0x70000080 0x20 /* Mux registers */
321 0x700000a0 0x14 /* Pull-up/down registers */
322 0x70000868 0xa8>; /* Pad control registers */
326 compatible = "nvidia,tegra20-das";
327 reg = <0x70000c00 0x80>;
330 tegra_ac97: ac97@70002000 {
331 compatible = "nvidia,tegra20-ac97";
332 reg = <0x70002000 0x200>;
333 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&tegra_car TEGRA20_CLK_AC97>;
335 resets = <&tegra_car 3>;
336 reset-names = "ac97";
337 dmas = <&apbdma 12>, <&apbdma 12>;
338 dma-names = "rx", "tx";
342 tegra_i2s1: i2s@70002800 {
343 compatible = "nvidia,tegra20-i2s";
344 reg = <0x70002800 0x200>;
345 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
347 resets = <&tegra_car 11>;
349 dmas = <&apbdma 2>, <&apbdma 2>;
350 dma-names = "rx", "tx";
354 tegra_i2s2: i2s@70002a00 {
355 compatible = "nvidia,tegra20-i2s";
356 reg = <0x70002a00 0x200>;
357 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
359 resets = <&tegra_car 18>;
361 dmas = <&apbdma 1>, <&apbdma 1>;
362 dma-names = "rx", "tx";
367 * There are two serial driver i.e. 8250 based simple serial
368 * driver and APB DMA based serial driver for higher baudrate
369 * and performace. To enable the 8250 based driver, the compatible
370 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
371 * driver, the compatible is "nvidia,tegra20-hsuart".
373 uarta: serial@70006000 {
374 compatible = "nvidia,tegra20-uart";
375 reg = <0x70006000 0x40>;
377 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
379 resets = <&tegra_car 6>;
380 reset-names = "serial";
381 dmas = <&apbdma 8>, <&apbdma 8>;
382 dma-names = "rx", "tx";
386 uartb: serial@70006040 {
387 compatible = "nvidia,tegra20-uart";
388 reg = <0x70006040 0x40>;
390 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
392 resets = <&tegra_car 7>;
393 reset-names = "serial";
394 dmas = <&apbdma 9>, <&apbdma 9>;
395 dma-names = "rx", "tx";
399 uartc: serial@70006200 {
400 compatible = "nvidia,tegra20-uart";
401 reg = <0x70006200 0x100>;
403 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
405 resets = <&tegra_car 55>;
406 reset-names = "serial";
407 dmas = <&apbdma 10>, <&apbdma 10>;
408 dma-names = "rx", "tx";
412 uartd: serial@70006300 {
413 compatible = "nvidia,tegra20-uart";
414 reg = <0x70006300 0x100>;
416 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
418 resets = <&tegra_car 65>;
419 reset-names = "serial";
420 dmas = <&apbdma 19>, <&apbdma 19>;
421 dma-names = "rx", "tx";
425 uarte: serial@70006400 {
426 compatible = "nvidia,tegra20-uart";
427 reg = <0x70006400 0x100>;
429 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
431 resets = <&tegra_car 66>;
432 reset-names = "serial";
433 dmas = <&apbdma 20>, <&apbdma 20>;
434 dma-names = "rx", "tx";
438 nand-controller@70008000 {
439 compatible = "nvidia,tegra20-nand";
440 reg = <0x70008000 0x100>;
441 #address-cells = <1>;
443 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
445 clock-names = "nand";
446 resets = <&tegra_car 13>;
447 reset-names = "nand";
448 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
449 assigned-clock-rates = <150000000>;
454 compatible = "nvidia,tegra20-gmi";
455 reg = <0x70009000 0x1000>;
456 #address-cells = <2>;
458 ranges = <0 0 0xd0000000 0xfffffff>;
459 clocks = <&tegra_car TEGRA20_CLK_NOR>;
461 resets = <&tegra_car 42>;
467 compatible = "nvidia,tegra20-pwm";
468 reg = <0x7000a000 0x100>;
470 clocks = <&tegra_car TEGRA20_CLK_PWM>;
471 resets = <&tegra_car 17>;
477 compatible = "nvidia,tegra20-rtc";
478 reg = <0x7000e000 0x100>;
479 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&tegra_car TEGRA20_CLK_RTC>;
484 compatible = "nvidia,tegra20-i2c";
485 reg = <0x7000c000 0x100>;
486 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
487 #address-cells = <1>;
489 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
490 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
491 clock-names = "div-clk", "fast-clk";
492 resets = <&tegra_car 12>;
494 dmas = <&apbdma 21>, <&apbdma 21>;
495 dma-names = "rx", "tx";
500 compatible = "nvidia,tegra20-sflash";
501 reg = <0x7000c380 0x80>;
502 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
505 clocks = <&tegra_car TEGRA20_CLK_SPI>;
506 resets = <&tegra_car 43>;
508 dmas = <&apbdma 11>, <&apbdma 11>;
509 dma-names = "rx", "tx";
514 compatible = "nvidia,tegra20-i2c";
515 reg = <0x7000c400 0x100>;
516 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
519 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
520 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
521 clock-names = "div-clk", "fast-clk";
522 resets = <&tegra_car 54>;
524 dmas = <&apbdma 22>, <&apbdma 22>;
525 dma-names = "rx", "tx";
530 compatible = "nvidia,tegra20-i2c";
531 reg = <0x7000c500 0x100>;
532 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
535 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
536 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
537 clock-names = "div-clk", "fast-clk";
538 resets = <&tegra_car 67>;
540 dmas = <&apbdma 23>, <&apbdma 23>;
541 dma-names = "rx", "tx";
546 compatible = "nvidia,tegra20-i2c-dvc";
547 reg = <0x7000d000 0x200>;
548 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
551 clocks = <&tegra_car TEGRA20_CLK_DVC>,
552 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
553 clock-names = "div-clk", "fast-clk";
554 resets = <&tegra_car 47>;
556 dmas = <&apbdma 24>, <&apbdma 24>;
557 dma-names = "rx", "tx";
562 compatible = "nvidia,tegra20-slink";
563 reg = <0x7000d400 0x200>;
564 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
565 #address-cells = <1>;
567 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
568 resets = <&tegra_car 41>;
570 dmas = <&apbdma 15>, <&apbdma 15>;
571 dma-names = "rx", "tx";
576 compatible = "nvidia,tegra20-slink";
577 reg = <0x7000d600 0x200>;
578 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
581 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
582 resets = <&tegra_car 44>;
584 dmas = <&apbdma 16>, <&apbdma 16>;
585 dma-names = "rx", "tx";
590 compatible = "nvidia,tegra20-slink";
591 reg = <0x7000d800 0x200>;
592 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
593 #address-cells = <1>;
595 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
596 resets = <&tegra_car 46>;
598 dmas = <&apbdma 17>, <&apbdma 17>;
599 dma-names = "rx", "tx";
604 compatible = "nvidia,tegra20-slink";
605 reg = <0x7000da00 0x200>;
606 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
609 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
610 resets = <&tegra_car 68>;
612 dmas = <&apbdma 18>, <&apbdma 18>;
613 dma-names = "rx", "tx";
618 compatible = "nvidia,tegra20-kbc";
619 reg = <0x7000e200 0x100>;
620 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&tegra_car TEGRA20_CLK_KBC>;
622 resets = <&tegra_car 36>;
628 compatible = "nvidia,tegra20-pmc";
629 reg = <0x7000e400 0x400>;
630 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
631 clock-names = "pclk", "clk32k_in";
634 mc: memory-controller@7000f000 {
635 compatible = "nvidia,tegra20-mc-gart";
636 reg = <0x7000f000 0x400 /* controller registers */
637 0x58000000 0x02000000>; /* GART aperture */
638 clocks = <&tegra_car TEGRA20_CLK_MC>;
640 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
645 memory-controller@7000f400 {
646 compatible = "nvidia,tegra20-emc";
647 reg = <0x7000f400 0x200>;
648 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&tegra_car TEGRA20_CLK_EMC>;
650 #address-cells = <1>;
655 compatible = "nvidia,tegra20-efuse";
656 reg = <0x7000f800 0x400>;
657 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
658 clock-names = "fuse";
659 resets = <&tegra_car 39>;
660 reset-names = "fuse";
664 compatible = "nvidia,tegra20-pcie";
666 reg = <0x80003000 0x00000800 /* PADS registers */
667 0x80003800 0x00000200 /* AFI registers */
668 0x90000000 0x10000000>; /* configuration space */
669 reg-names = "pads", "afi", "cs";
670 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
671 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
672 interrupt-names = "intr", "msi";
674 #interrupt-cells = <1>;
675 interrupt-map-mask = <0 0 0 0>;
676 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
678 bus-range = <0x00 0xff>;
679 #address-cells = <3>;
682 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
683 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
684 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
685 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
686 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
688 clocks = <&tegra_car TEGRA20_CLK_PEX>,
689 <&tegra_car TEGRA20_CLK_AFI>,
690 <&tegra_car TEGRA20_CLK_PLL_E>;
691 clock-names = "pex", "afi", "pll_e";
692 resets = <&tegra_car 70>,
695 reset-names = "pex", "afi", "pcie_x";
700 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
701 reg = <0x000800 0 0 0 0>;
702 bus-range = <0x00 0xff>;
705 #address-cells = <3>;
709 nvidia,num-lanes = <2>;
714 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
715 reg = <0x001000 0 0 0 0>;
716 bus-range = <0x00 0xff>;
719 #address-cells = <3>;
723 nvidia,num-lanes = <2>;
728 compatible = "nvidia,tegra20-ehci", "usb-ehci";
729 reg = <0xc5000000 0x4000>;
730 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
732 nvidia,has-legacy-mode;
733 clocks = <&tegra_car TEGRA20_CLK_USBD>;
734 resets = <&tegra_car 22>;
736 nvidia,needs-double-reset;
737 nvidia,phy = <&phy1>;
741 phy1: usb-phy@c5000000 {
742 compatible = "nvidia,tegra20-usb-phy";
743 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
745 clocks = <&tegra_car TEGRA20_CLK_USBD>,
746 <&tegra_car TEGRA20_CLK_PLL_U>,
747 <&tegra_car TEGRA20_CLK_CLK_M>,
748 <&tegra_car TEGRA20_CLK_USBD>;
749 clock-names = "reg", "pll_u", "timer", "utmi-pads";
750 resets = <&tegra_car 22>, <&tegra_car 22>;
751 reset-names = "usb", "utmi-pads";
752 nvidia,has-legacy-mode;
753 nvidia,hssync-start-delay = <9>;
754 nvidia,idle-wait-delay = <17>;
755 nvidia,elastic-limit = <16>;
756 nvidia,term-range-adj = <6>;
757 nvidia,xcvr-setup = <9>;
758 nvidia,xcvr-lsfslew = <1>;
759 nvidia,xcvr-lsrslew = <1>;
760 nvidia,has-utmi-pad-registers;
765 compatible = "nvidia,tegra20-ehci", "usb-ehci";
766 reg = <0xc5004000 0x4000>;
767 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&tegra_car TEGRA20_CLK_USB2>;
770 resets = <&tegra_car 58>;
772 nvidia,phy = <&phy2>;
776 phy2: usb-phy@c5004000 {
777 compatible = "nvidia,tegra20-usb-phy";
778 reg = <0xc5004000 0x4000>;
780 clocks = <&tegra_car TEGRA20_CLK_USB2>,
781 <&tegra_car TEGRA20_CLK_PLL_U>,
782 <&tegra_car TEGRA20_CLK_CDEV2>;
783 clock-names = "reg", "pll_u", "ulpi-link";
784 resets = <&tegra_car 58>, <&tegra_car 22>;
785 reset-names = "usb", "utmi-pads";
790 compatible = "nvidia,tegra20-ehci", "usb-ehci";
791 reg = <0xc5008000 0x4000>;
792 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&tegra_car TEGRA20_CLK_USB3>;
795 resets = <&tegra_car 59>;
797 nvidia,phy = <&phy3>;
801 phy3: usb-phy@c5008000 {
802 compatible = "nvidia,tegra20-usb-phy";
803 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
805 clocks = <&tegra_car TEGRA20_CLK_USB3>,
806 <&tegra_car TEGRA20_CLK_PLL_U>,
807 <&tegra_car TEGRA20_CLK_CLK_M>,
808 <&tegra_car TEGRA20_CLK_USBD>;
809 clock-names = "reg", "pll_u", "timer", "utmi-pads";
810 resets = <&tegra_car 59>, <&tegra_car 22>;
811 reset-names = "usb", "utmi-pads";
812 nvidia,hssync-start-delay = <9>;
813 nvidia,idle-wait-delay = <17>;
814 nvidia,elastic-limit = <16>;
815 nvidia,term-range-adj = <6>;
816 nvidia,xcvr-setup = <9>;
817 nvidia,xcvr-lsfslew = <2>;
818 nvidia,xcvr-lsrslew = <2>;
823 compatible = "nvidia,tegra20-sdhci";
824 reg = <0xc8000000 0x200>;
825 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
827 resets = <&tegra_car 14>;
828 reset-names = "sdhci";
833 compatible = "nvidia,tegra20-sdhci";
834 reg = <0xc8000200 0x200>;
835 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
837 resets = <&tegra_car 9>;
838 reset-names = "sdhci";
843 compatible = "nvidia,tegra20-sdhci";
844 reg = <0xc8000400 0x200>;
845 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
847 resets = <&tegra_car 69>;
848 reset-names = "sdhci";
853 compatible = "nvidia,tegra20-sdhci";
854 reg = <0xc8000600 0x200>;
855 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
857 resets = <&tegra_car 15>;
858 reset-names = "sdhci";
862 cpu0_opp_table: opp_table0 {
863 compatible = "operating-points-v2";
867 clock-latency-ns = <2000>;
868 opp-microvolt = <750000 750000 1125000>;
869 opp-supported-hw = <0xFF 0xFFFF>;
870 opp-hz = /bits/ 64 <216000000>;
875 clock-latency-ns = <125000>;
876 opp-microvolt = <750000 750000 1125000>;
877 opp-supported-hw = <0x03 0x0001>;
878 opp-hz = /bits/ 64 <314000000>;
882 clock-latency-ns = <125000>;
883 opp-microvolt = <750000 750000 1125000>;
884 opp-supported-hw = <0x01 0x0002>;
885 opp-hz = /bits/ 64 <380000000>;
889 clock-latency-ns = <125000>;
890 opp-microvolt = <750000 750000 1125000>;
891 opp-supported-hw = <0x02 0x0002>;
892 opp-hz = /bits/ 64 <389000000>;
896 clock-latency-ns = <125000>;
897 opp-microvolt = <825000 825000 1125000>;
898 opp-supported-hw = <0x03 0x0001>;
899 opp-hz = /bits/ 64 <456000000>;
903 clock-latency-ns = <125000>;
904 opp-microvolt = <750000 750000 1125000>;
905 opp-supported-hw = <0x04 0x0001>;
906 opp-hz = /bits/ 64 <494000000>;
910 clock-latency-ns = <125000>;
911 opp-microvolt = <800000 800000 1125000>;
912 opp-supported-hw = <0x03 0x0002>;
913 opp-hz = /bits/ 64 <503000000>;
917 clock-latency-ns = <125000>;
918 opp-microvolt = <750000 750000 1125000>;
919 opp-supported-hw = <0x04 0x0002>;
920 opp-hz = /bits/ 64 <598000000>;
924 clock-latency-ns = <125000>;
925 opp-microvolt = <900000 900000 1125000>;
926 opp-supported-hw = <0x01 0x0001>;
927 opp-hz = /bits/ 64 <608000000>;
931 clock-latency-ns = <125000>;
932 opp-microvolt = <900000 900000 1125000>;
933 opp-supported-hw = <0x02 0x0001>;
934 opp-hz = /bits/ 64 <618000000>;
938 clock-latency-ns = <125000>;
939 opp-microvolt = <850000 850000 1125000>;
940 opp-supported-hw = <0x03 0x0002>;
941 opp-hz = /bits/ 64 <655000000>;
945 clock-latency-ns = <125000>;
946 opp-microvolt = <825000 825000 1125000>;
947 opp-supported-hw = <0x04 0x0001>;
948 opp-hz = /bits/ 64 <675000000>;
952 clock-latency-ns = <125000>;
953 opp-microvolt = <750000 750000 1125000>;
954 opp-supported-hw = <0x08 0x0003>;
955 opp-hz = /bits/ 64 <730000000>;
959 clock-latency-ns = <125000>;
960 opp-microvolt = <800000 800000 1125000>;
961 opp-supported-hw = <0x04 0x0002>;
962 opp-hz = /bits/ 64 <750000000>;
966 clock-latency-ns = <125000>;
967 opp-microvolt = <775000 775000 1125000>;
968 opp-supported-hw = <0x08 0x0003>;
969 opp-hz = /bits/ 64 <760000000>;
973 clock-latency-ns = <125000>;
974 opp-microvolt = <875000 875000 1125000>;
975 opp-supported-hw = <0x02 0x0002>;
976 opp-hz = /bits/ 64 <760000000>;
980 clock-latency-ns = <125000>;
981 opp-microvolt = <975000 975000 1125000>;
982 opp-supported-hw = <0x01 0x0001>;
983 opp-hz = /bits/ 64 <760000000>;
987 clock-latency-ns = <125000>;
988 opp-microvolt = <975000 975000 1125000>;
989 opp-supported-hw = <0x02 0x0001>;
990 opp-hz = /bits/ 64 <770000000>;
994 clock-latency-ns = <125000>;
995 opp-microvolt = <900000 900000 1125000>;
996 opp-supported-hw = <0x03 0x0002>;
997 opp-hz = /bits/ 64 <798000000>;
1001 clock-latency-ns = <125000>;
1002 opp-microvolt = <875000 875000 1125000>;
1003 opp-supported-hw = <0x04 0x0001>;
1004 opp-hz = /bits/ 64 <817000000>;
1007 opp@817000000_1000 {
1008 clock-latency-ns = <125000>;
1009 opp-microvolt = <1000000 1000000 1125000>;
1010 opp-supported-hw = <0x01 0x0001>;
1011 opp-hz = /bits/ 64 <817000000>;
1014 opp@827000000_1000 {
1015 clock-latency-ns = <125000>;
1016 opp-microvolt = <1000000 1000000 1125000>;
1017 opp-supported-hw = <0x02 0x0001>;
1018 opp-hz = /bits/ 64 <827000000>;
1022 clock-latency-ns = <125000>;
1023 opp-microvolt = <800000 800000 1125000>;
1024 opp-supported-hw = <0x08 0x0003>;
1025 opp-hz = /bits/ 64 <845000000>;
1029 clock-latency-ns = <125000>;
1030 opp-microvolt = <850000 850000 1125000>;
1031 opp-supported-hw = <0x04 0x0002>;
1032 opp-hz = /bits/ 64 <893000000>;
1036 clock-latency-ns = <125000>;
1037 opp-microvolt = <950000 950000 1125000>;
1038 opp-supported-hw = <0x01 0x0002>;
1039 opp-hz = /bits/ 64 <902000000>;
1042 opp@912000000_1050 {
1043 clock-latency-ns = <125000>;
1044 opp-microvolt = <1050000 1050000 1125000>;
1045 opp-supported-hw = <0x01 0x0001>;
1046 opp-hz = /bits/ 64 <912000000>;
1050 clock-latency-ns = <125000>;
1051 opp-microvolt = <925000 925000 1125000>;
1052 opp-supported-hw = <0x04 0x0001>;
1053 opp-hz = /bits/ 64 <922000000>;
1056 opp@922000000_1050 {
1057 clock-latency-ns = <125000>;
1058 opp-microvolt = <1050000 1050000 1125000>;
1059 opp-supported-hw = <0x02 0x0001>;
1060 opp-hz = /bits/ 64 <922000000>;
1064 clock-latency-ns = <125000>;
1065 opp-microvolt = <850000 850000 1125000>;
1066 opp-supported-hw = <0x08 0x0003>;
1067 opp-hz = /bits/ 64 <940000000>;
1071 clock-latency-ns = <125000>;
1072 opp-microvolt = <950000 950000 1125000>;
1073 opp-supported-hw = <0x02 0x0002>;
1074 opp-hz = /bits/ 64 <950000000>;
1077 opp@960000000_1000 {
1078 clock-latency-ns = <125000>;
1079 opp-microvolt = <1000000 1000000 1125000>;
1080 opp-supported-hw = <0x01 0x0002>;
1081 opp-hz = /bits/ 64 <960000000>;
1084 opp@1000000000_875 {
1085 clock-latency-ns = <125000>;
1086 opp-microvolt = <875000 875000 1125000>;
1087 opp-supported-hw = <0x08 0x0003>;
1088 opp-hz = /bits/ 64 <1000000000>;
1091 opp@1000000000_900 {
1092 clock-latency-ns = <125000>;
1093 opp-microvolt = <900000 900000 1125000>;
1094 opp-supported-hw = <0x04 0x0002>;
1095 opp-hz = /bits/ 64 <1000000000>;
1098 opp@1000000000_975 {
1099 clock-latency-ns = <125000>;
1100 opp-microvolt = <975000 975000 1125000>;
1101 opp-supported-hw = <0x04 0x0001>;
1102 opp-hz = /bits/ 64 <1000000000>;
1105 opp@1000000000_1000 {
1106 clock-latency-ns = <125000>;
1107 opp-microvolt = <1000000 1000000 1125000>;
1108 opp-supported-hw = <0x02 0x0002>;
1109 opp-hz = /bits/ 64 <1000000000>;
1112 opp@1000000000_1025 {
1113 clock-latency-ns = <125000>;
1114 opp-microvolt = <1025000 1025000 1125000>;
1115 opp-supported-hw = <0x01 0x0002>;
1116 opp-hz = /bits/ 64 <1000000000>;
1119 opp@1000000000_1100 {
1120 clock-latency-ns = <125000>;
1121 opp-microvolt = <1100000 1100000 1125000>;
1122 opp-supported-hw = <0x03 0x0001>;
1123 opp-hz = /bits/ 64 <1000000000>;
1128 #address-cells = <1>;
1132 device_type = "cpu";
1133 compatible = "arm,cortex-a9";
1135 clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
1136 <&tegra_car TEGRA20_CLK_PLL_P>,
1137 <&tegra_car TEGRA20_CLK_CCLK>;
1138 clock-names = "pll_x", "intermediate", "cclk";
1139 operating-points-v2 = <&cpu0_opp_table>;
1140 #cooling-cells = <2>;
1144 device_type = "cpu";
1145 compatible = "arm,cortex-a9";
1147 clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
1148 <&tegra_car TEGRA20_CLK_PLL_P>,
1149 <&tegra_car TEGRA20_CLK_CCLK>;
1150 clock-names = "pll_x", "intermediate", "cclk";
1151 operating-points-v2 = <&cpu0_opp_table>;
1152 #cooling-cells = <2>;
1157 compatible = "arm,cortex-a9-pmu";
1158 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1160 interrupt-affinity = <&{/cpus/cpu@0}>,