arch/arm/mach-ixp2000/core.c

   1 /*
   2  * arch/arm/mach-ixp2000/common.c
   3  *
   4  * Common routines used by all IXP2400/2800 based platforms.
   5  *
   6  * Author: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2004 (C) MontaVista Software, Inc.
   9  *
  10  * Based on work Copyright (C) 2002-2003 Intel Corporation
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2. This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/sched.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/serial.h>
  24 #include <linux/tty.h>
  25 #include <linux/bitops.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/mm.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/irq.h>
  35 #include <asm/system.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/pgtable.h>
  38
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/time.h>
  41 #include <asm/mach/irq.h>
  42
  43 #include <asm/arch/gpio.h>
  44
  45 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
  46 static unsigned long ixp2000_slowport_irq_flags;
  47
  48 /*************************************************************************
  49  * Slowport access routines
  50  *************************************************************************/
  51 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
  52 {
  53
  54         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
  55
  56         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
  57         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
  58         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
  59         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
  60         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
  61
  62         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
  63         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
  64         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
  65         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
  66         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
  67 }
  68
  69 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
  70 {
  71         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
  72         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
  73         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
  74         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
  75         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
  76
  77         spin_unlock_irqrestore(&ixp2000_slowport_lock,
  78                                         ixp2000_slowport_irq_flags);
  79 }
  80
  81 /*************************************************************************
  82  * Chip specific mappings shared by all IXP2000 systems
  83  *************************************************************************/
  84 static struct map_desc ixp2000_io_desc[] __initdata = {
  85         {
  86                 .virtual        = IXP2000_CAP_VIRT_BASE,
  87                 .physical       = IXP2000_CAP_PHYS_BASE,
  88                 .length         = IXP2000_CAP_SIZE,
  89                 .type           = MT_DEVICE
  90         }, {
  91                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
  92                 .physical       = IXP2000_INTCTL_PHYS_BASE,
  93                 .length         = IXP2000_INTCTL_SIZE,
  94                 .type           = MT_DEVICE
  95         }, {
  96                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
  97                 .physical       = IXP2000_PCI_CREG_PHYS_BASE,
  98                 .length         = IXP2000_PCI_CREG_SIZE,
  99                 .type           = MT_DEVICE
 100         }, {
 101                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
 102                 .physical       = IXP2000_PCI_CSR_PHYS_BASE,
 103                 .length         = IXP2000_PCI_CSR_SIZE,
 104                 .type           = MT_DEVICE
 105         }, {
 106                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
 107                 .physical       = IXP2000_PCI_IO_PHYS_BASE,
 108                 .length         = IXP2000_PCI_IO_SIZE,
 109                 .type           = MT_DEVICE
 110         }, {
 111                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
 112                 .physical       = IXP2000_PCI_CFG0_PHYS_BASE,
 113                 .length         = IXP2000_PCI_CFG0_SIZE,
 114                 .type           = MT_DEVICE
 115         }, {
 116                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
 117                 .physical       = IXP2000_PCI_CFG1_PHYS_BASE,
 118                 .length         = IXP2000_PCI_CFG1_SIZE,
 119                 .type           = MT_DEVICE
 120         }
 121 };
 122
 123 static struct uart_port ixp2000_serial_port = {
 124         .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
 125         .mapbase        = IXP2000_UART_PHYS_BASE + 3,
 126         .irq            = IRQ_IXP2000_UART,
 127         .flags          = UPF_SKIP_TEST,
 128         .iotype         = UPIO_MEM,
 129         .regshift       = 2,
 130         .uartclk        = 50000000,
 131         .line           = 0,
 132         .type           = PORT_XSCALE,
 133         .fifosize       = 16
 134 };
 135
 136 void __init ixp2000_map_io(void)
 137 {
 138         extern unsigned int processor_id;
 139
 140         /*
 141          * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
 142          * tweaking the PMDs so XCB=101. On IXP2800s we use the normal
 143          * PMD flags.
 144          */
 145         if ((processor_id & 0xfffffff0) == 0x69054190) {
 146                 int i;
 147
 148                 printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
 149
 150                 for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
 151                         ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
 152         }
 153
 154         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
 155         early_serial_setup(&ixp2000_serial_port);
 156
 157         /* Set slowport to 8-bit mode.  */
 158         ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
 159 }
 160
 161 /*************************************************************************
 162  * Timer-tick functions for IXP2000
 163  *************************************************************************/
 164 static unsigned ticks_per_jiffy;
 165 static unsigned ticks_per_usec;
 166 static unsigned next_jiffy_time;
 167 static volatile unsigned long *missing_jiffy_timer_csr;
 168
 169 unsigned long ixp2000_gettimeoffset (void)
 170 {
 171         unsigned long offset;
 172
 173         offset = next_jiffy_time - *missing_jiffy_timer_csr;
 174
 175         return offset / ticks_per_usec;
 176 }
 177
 178 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 179 {
 180         write_seqlock(&xtime_lock);
 181
 182         /* clear timer 1 */
 183         ixp2000_reg_write(IXP2000_T1_CLR, 1);
 184
 185         while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
 186                 timer_tick(regs);
 187                 next_jiffy_time -= ticks_per_jiffy;
 188         }
 189
 190         write_sequnlock(&xtime_lock);
 191
 192         return IRQ_HANDLED;
 193 }
 194
 195 static struct irqaction ixp2000_timer_irq = {
 196         .name           = "IXP2000 Timer Tick",
 197         .flags          = SA_INTERRUPT,
 198         .handler        = ixp2000_timer_interrupt
 199 };
 200
 201 void __init ixp2000_init_time(unsigned long tick_rate)
 202 {
 203         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
 204         ticks_per_usec = tick_rate / 1000000;
 205
 206         /*
 207          * We use timer 1 as our timer interrupt.
 208          */
 209         ixp2000_reg_write(IXP2000_T1_CLR, 0);
 210         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
 211         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
 212
 213         /*
 214          * We use a second timer as a monotonic counter for tracking
 215          * missed jiffies.  The IXP2000 has four timers, but if we're
 216          * on an A-step IXP2800, timer 2 and 3 don't work, so on those
 217          * chips we use timer 4.  Timer 4 is the only timer that can
 218          * be used for the watchdog, so we use timer 2 if we're on a
 219          * non-buggy chip.
 220          */
 221         if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
 222                 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
 223
 224                 ixp2000_reg_write(IXP2000_T4_CLR, 0);
 225                 ixp2000_reg_write(IXP2000_T4_CLD, -1);
 226                 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
 227                 missing_jiffy_timer_csr = IXP2000_T4_CSR;
 228         } else {
 229                 ixp2000_reg_write(IXP2000_T2_CLR, 0);
 230                 ixp2000_reg_write(IXP2000_T2_CLD, -1);
 231                 ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
 232                 missing_jiffy_timer_csr = IXP2000_T2_CSR;
 233         }
 234         next_jiffy_time = 0xffffffff;
 235
 236         /* register for interrupt */
 237         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
 238 }
 239
 240 /*************************************************************************
 241  * GPIO helpers
 242  *************************************************************************/
 243 static unsigned long GPIO_IRQ_falling_edge;
 244 static unsigned long GPIO_IRQ_rising_edge;
 245 static unsigned long GPIO_IRQ_level_low;
 246 static unsigned long GPIO_IRQ_level_high;
 247
 248 static void update_gpio_int_csrs(void)
 249 {
 250         ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
 251         ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
 252         ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
 253         ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
 254 }
 255
 256 void gpio_line_config(int line, int direction)
 257 {
 258         unsigned long flags;
 259
 260         local_irq_save(flags);
 261         if (direction == GPIO_OUT) {
 262                 irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
 263
 264                 /* if it's an output, it ain't an interrupt anymore */
 265                 GPIO_IRQ_falling_edge &= ~(1 << line);
 266                 GPIO_IRQ_rising_edge &= ~(1 << line);
 267                 GPIO_IRQ_level_low &= ~(1 << line);
 268                 GPIO_IRQ_level_high &= ~(1 << line);
 269                 update_gpio_int_csrs();
 270
 271                 ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line);
 272         } else if (direction == GPIO_IN) {
 273                 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
 274         }
 275         local_irq_restore(flags);
 276 }
 277
 278
 279 /*************************************************************************
 280  * IRQ handling IXP2000
 281  *************************************************************************/
 282 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 283 {
 284         int i;
 285         unsigned long status = *IXP2000_GPIO_INST;
 286
 287         for (i = 0; i <= 7; i++) {
 288                 if (status & (1<<i)) {
 289                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
 290                         desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
 291                 }
 292         }
 293 }
 294
 295 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
 296 {
 297         int line = irq - IRQ_IXP2000_GPIO0;
 298
 299         /*
 300          * First, configure this GPIO line as an input.
 301          */
 302         ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
 303
 304         /*
 305          * Then, set the proper trigger type.
 306          */
 307         if (type & IRQT_FALLING)
 308                 GPIO_IRQ_falling_edge |= 1 << line;
 309         else
 310                 GPIO_IRQ_falling_edge &= ~(1 << line);
 311         if (type & IRQT_RISING)
 312                 GPIO_IRQ_rising_edge |= 1 << line;
 313         else
 314                 GPIO_IRQ_rising_edge &= ~(1 << line);
 315         if (type & IRQT_LOW)
 316                 GPIO_IRQ_level_low |= 1 << line;
 317         else
 318                 GPIO_IRQ_level_low &= ~(1 << line);
 319         if (type & IRQT_HIGH)
 320                 GPIO_IRQ_level_high |= 1 << line;
 321         else
 322                 GPIO_IRQ_level_high &= ~(1 << line);
 323         update_gpio_int_csrs();
 324
 325         /*
 326          * Finally, mark the corresponding IRQ as valid.
 327          */
 328         irq_desc[irq].valid = 1;
 329
 330         return 0;
 331 }
 332
 333 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
 334 {
 335         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 336
 337         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 338         ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 339         ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
 340 }
 341
 342 static void ixp2000_GPIO_irq_mask(unsigned int irq)
 343 {
 344         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 345 }
 346
 347 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
 348 {
 349         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
 350 }
 351
 352 static struct irqchip ixp2000_GPIO_irq_chip = {
 353         .type   = ixp2000_GPIO_irq_type,
 354         .ack    = ixp2000_GPIO_irq_mask_ack,
 355         .mask   = ixp2000_GPIO_irq_mask,
 356         .unmask = ixp2000_GPIO_irq_unmask
 357 };
 358
 359 static void ixp2000_pci_irq_mask(unsigned int irq)
 360 {
 361         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 362         if (irq == IRQ_IXP2000_PCIA)
 363                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
 364         else if (irq == IRQ_IXP2000_PCIB)
 365                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
 366 }
 367
 368 static void ixp2000_pci_irq_unmask(unsigned int irq)
 369 {
 370         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
 371         if (irq == IRQ_IXP2000_PCIA)
 372                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
 373         else if (irq == IRQ_IXP2000_PCIB)
 374                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
 375 }
 376
 377 static struct irqchip ixp2000_pci_irq_chip = {
 378         .ack    = ixp2000_pci_irq_mask,
 379         .mask   = ixp2000_pci_irq_mask,
 380         .unmask = ixp2000_pci_irq_unmask
 381 };
 382
 383 static void ixp2000_irq_mask(unsigned int irq)
 384 {
 385         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
 386 }
 387
 388 static void ixp2000_irq_unmask(unsigned int irq)
 389 {
 390         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
 391 }
 392
 393 static struct irqchip ixp2000_irq_chip = {
 394         .ack    = ixp2000_irq_mask,
 395         .mask   = ixp2000_irq_mask,
 396         .unmask = ixp2000_irq_unmask
 397 };
 398
 399 void __init ixp2000_init_irq(void)
 400 {
 401         int irq;
 402
 403         /*
 404          * Mask all sources
 405          */
 406         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
 407         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
 408
 409         /* clear all GPIO edge/level detects */
 410         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
 411         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
 412         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
 413         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
 414         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
 415
 416         /* clear PCI interrupt sources */
 417         ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
 418
 419         /*
 420          * Certain bits in the IRQ status register of the
 421          * IXP2000 are reserved. Instead of trying to map
 422          * things non 1:1 from bit position to IRQ number,
 423          * we mark the reserved IRQs as invalid. This makes
 424          * our mask/unmask code much simpler.
 425          */
 426         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
 427                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
 428                         set_irq_chip(irq, &ixp2000_irq_chip);
 429                         set_irq_handler(irq, do_level_IRQ);
 430                         set_irq_flags(irq, IRQF_VALID);
 431                 } else set_irq_flags(irq, 0);
 432         }
 433
 434         /*
 435          * GPIO IRQs are invalid until someone sets the interrupt mode
 436          * by calling set_irq_type().
 437          */
 438         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
 439                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
 440                 set_irq_handler(irq, do_level_IRQ);
 441                 set_irq_flags(irq, 0);
 442         }
 443         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 444
 445         /*
 446          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
 447          * entry-macro.S, so we don't need a chained handler for the
 448          * PCI interrupt source.
 449          */
 450         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 451         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
 452                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
 453                 set_irq_handler(irq, do_level_IRQ);
 454                 set_irq_flags(irq, IRQF_VALID);
 455         }
 456 }
 457