1 /* linux/arch/arm/mach-s3c2410/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Core clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/sysdev.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
40 #include <linux/mutex.h>
41 #include <linux/delay.h>
43 #include <asm/hardware.h>
47 #include <asm/arch/regs-clock.h>
48 #include <asm/arch/regs-gpio.h>
53 /* clock information */
55 static LIST_HEAD(clocks);
57 DEFINE_MUTEX(clocks_mutex);
59 /* enable and disable calls for use with the clk struct */
61 static int clk_null_enable(struct clk *clk, int enable)
68 struct clk *clk_get(struct device *dev, const char *id)
71 struct clk *clk = ERR_PTR(-ENOENT);
74 if (dev == NULL || dev->bus != &platform_bus_type)
77 idno = to_platform_device(dev)->id;
79 mutex_lock(&clocks_mutex);
81 list_for_each_entry(p, &clocks, list) {
83 strcmp(id, p->name) == 0 &&
84 try_module_get(p->owner)) {
90 /* check for the case where a device was supplied, but the
91 * clock that was being searched for is not device specific */
94 list_for_each_entry(p, &clocks, list) {
95 if (p->id == -1 && strcmp(id, p->name) == 0 &&
96 try_module_get(p->owner)) {
103 mutex_unlock(&clocks_mutex);
107 void clk_put(struct clk *clk)
109 module_put(clk->owner);
112 int clk_enable(struct clk *clk)
114 if (IS_ERR(clk) || clk == NULL)
117 clk_enable(clk->parent);
119 mutex_lock(&clocks_mutex);
121 if ((clk->usage++) == 0)
122 (clk->enable)(clk, 1);
124 mutex_unlock(&clocks_mutex);
128 void clk_disable(struct clk *clk)
130 if (IS_ERR(clk) || clk == NULL)
133 mutex_lock(&clocks_mutex);
135 if ((--clk->usage) == 0)
136 (clk->enable)(clk, 0);
138 mutex_unlock(&clocks_mutex);
139 clk_disable(clk->parent);
143 unsigned long clk_get_rate(struct clk *clk)
151 while (clk->parent != NULL && clk->rate == 0)
157 long clk_round_rate(struct clk *clk, unsigned long rate)
159 if (!IS_ERR(clk) && clk->round_rate)
160 return (clk->round_rate)(clk, rate);
165 int clk_set_rate(struct clk *clk, unsigned long rate)
172 mutex_lock(&clocks_mutex);
173 ret = (clk->set_rate)(clk, rate);
174 mutex_unlock(&clocks_mutex);
179 struct clk *clk_get_parent(struct clk *clk)
184 int clk_set_parent(struct clk *clk, struct clk *parent)
191 mutex_lock(&clocks_mutex);
194 ret = (clk->set_parent)(clk, parent);
196 mutex_unlock(&clocks_mutex);
201 EXPORT_SYMBOL(clk_get);
202 EXPORT_SYMBOL(clk_put);
203 EXPORT_SYMBOL(clk_enable);
204 EXPORT_SYMBOL(clk_disable);
205 EXPORT_SYMBOL(clk_get_rate);
206 EXPORT_SYMBOL(clk_round_rate);
207 EXPORT_SYMBOL(clk_set_rate);
208 EXPORT_SYMBOL(clk_get_parent);
209 EXPORT_SYMBOL(clk_set_parent);
213 static struct clk clk_xtal = {
221 struct clk clk_upll = {
252 struct clk clk_usb_bus = {
259 /* clocks that could be registered by external code */
261 static int s3c24xx_dclk_enable(struct clk *clk, int enable)
263 unsigned long dclkcon = __raw_readl(S3C2410_DCLKCON);
266 dclkcon |= clk->ctrlbit;
268 dclkcon &= ~clk->ctrlbit;
270 __raw_writel(dclkcon, S3C2410_DCLKCON);
275 static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
277 unsigned long dclkcon;
280 if (parent == &clk_upll)
282 else if (parent == &clk_p)
287 clk->parent = parent;
289 dclkcon = __raw_readl(S3C2410_DCLKCON);
291 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
293 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
295 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
298 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
300 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
303 __raw_writel(dclkcon, S3C2410_DCLKCON);
309 static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
312 unsigned long source;
314 /* calculate the MISCCR setting for the clock */
316 if (parent == &clk_xtal)
317 source = S3C2410_MISCCR_CLK0_MPLL;
318 else if (parent == &clk_upll)
319 source = S3C2410_MISCCR_CLK0_UPLL;
320 else if (parent == &clk_f)
321 source = S3C2410_MISCCR_CLK0_FCLK;
322 else if (parent == &clk_h)
323 source = S3C2410_MISCCR_CLK0_HCLK;
324 else if (parent == &clk_p)
325 source = S3C2410_MISCCR_CLK0_PCLK;
326 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
327 source = S3C2410_MISCCR_CLK0_DCLK0;
328 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
329 source = S3C2410_MISCCR_CLK0_DCLK0;
333 clk->parent = parent;
335 if (clk == &s3c24xx_dclk0)
336 mask = S3C2410_MISCCR_CLK0_MASK;
339 mask = S3C2410_MISCCR_CLK1_MASK;
342 s3c2410_modify_misccr(mask, source);
346 /* external clock definitions */
348 struct clk s3c24xx_dclk0 = {
351 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
352 .enable = s3c24xx_dclk_enable,
353 .set_parent = s3c24xx_dclk_setparent,
356 struct clk s3c24xx_dclk1 = {
359 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
360 .enable = s3c24xx_dclk_enable,
361 .set_parent = s3c24xx_dclk_setparent,
364 struct clk s3c24xx_clkout0 = {
367 .set_parent = s3c24xx_clkout_setparent,
370 struct clk s3c24xx_clkout1 = {
373 .set_parent = s3c24xx_clkout_setparent,
376 struct clk s3c24xx_uclk = {
381 /* initialise the clock system */
383 int s3c24xx_register_clock(struct clk *clk)
385 clk->owner = THIS_MODULE;
387 if (clk->enable == NULL)
388 clk->enable = clk_null_enable;
390 /* add to the list of available clocks */
392 mutex_lock(&clocks_mutex);
393 list_add(&clk->list, &clocks);
394 mutex_unlock(&clocks_mutex);
399 /* initalise all the clocks */
401 int __init s3c24xx_setup_clocks(unsigned long xtal,
406 printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
408 /* initialise the main system clocks */
410 clk_xtal.rate = xtal;
411 clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
417 /* assume uart clocks are correctly setup */
419 /* register our clocks */
421 if (s3c24xx_register_clock(&clk_xtal) < 0)
422 printk(KERN_ERR "failed to register master xtal\n");
424 if (s3c24xx_register_clock(&clk_upll) < 0)
425 printk(KERN_ERR "failed to register upll clock\n");
427 if (s3c24xx_register_clock(&clk_f) < 0)
428 printk(KERN_ERR "failed to register cpu fclk\n");
430 if (s3c24xx_register_clock(&clk_h) < 0)
431 printk(KERN_ERR "failed to register cpu hclk\n");
433 if (s3c24xx_register_clock(&clk_p) < 0)
434 printk(KERN_ERR "failed to register cpu pclk\n");