git.rot13.org Git - linux/blob - arch/arm64/boot/dts/renesas/r8a774a1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a774a1 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  11
  12 / {
  13         compatible = "renesas,r8a774a1";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         aliases {
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c1;
  20                 i2c2 = &i2c2;
  21                 i2c3 = &i2c3;
  22                 i2c4 = &i2c4;
  23                 i2c5 = &i2c5;
  24                 i2c6 = &i2c6;
  25                 i2c7 = &i2c_dvfs;
  26         };
  27
  28         /*
  29          * The external audio clocks are configured as 0 Hz fixed frequency
  30          * clocks by default.
  31          * Boards that provide audio clocks should override them.
  32          */
  33         audio_clk_a: audio_clk_a {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <0>;
  37         };
  38
  39         audio_clk_b: audio_clk_b {
  40                 compatible = "fixed-clock";
  41                 #clock-cells = <0>;
  42                 clock-frequency = <0>;
  43         };
  44
  45         audio_clk_c: audio_clk_c {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 clock-frequency = <0>;
  49         };
  50
  51         /* External CAN clock - to be overridden by boards that provide it */
  52         can_clk: can {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 clock-frequency = <0>;
  56         };
  57
  58         cpus {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 a57_0: cpu@0 {
  63                         compatible = "arm,cortex-a57", "arm,armv8";
  64                         reg = <0x0>;
  65                         device_type = "cpu";
  66                         power-domains = <&sysc 0>;
  67                         next-level-cache = <&L2_CA57>;
  68                         enable-method = "psci";
  69                         clocks =<&cpg CPG_CORE 0>;
  70                 };
  71
  72                 a57_1: cpu@1 {
  73                         compatible = "arm,cortex-a57", "arm,armv8";
  74                         reg = <0x1>;
  75                         device_type = "cpu";
  76                         power-domains = <&sysc 1>;
  77                         next-level-cache = <&L2_CA57>;
  78                         enable-method = "psci";
  79                         clocks =<&cpg CPG_CORE 0>;
  80                 };
  81
  82                 L2_CA57: cache-controller-0 {
  83                         compatible = "cache";
  84                         power-domains = <&sysc 12>;
  85                         cache-unified;
  86                         cache-level = <2>;
  87                 };
  88         };
  89
  90         extal_clk: extal {
  91                 compatible = "fixed-clock";
  92                 #clock-cells = <0>;
  93                 /* This value must be overridden by the board */
  94                 clock-frequency = <0>;
  95         };
  96
  97         extalr_clk: extalr {
  98                 compatible = "fixed-clock";
  99                 #clock-cells = <0>;
 100                 /* This value must be overridden by the board */
 101                 clock-frequency = <0>;
 102         };
 103
 104         /* External PCIe clock - can be overridden by the board */
 105         pcie_bus_clk: pcie_bus {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <0>;
 109         };
 110
 111         pmu_a57 {
 112                 compatible = "arm,cortex-a57-pmu";
 113                 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 114                                       <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 115                 interrupt-affinity = <&a57_0>, <&a57_1>;
 116         };
 117
 118         psci {
 119                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 120                 method = "smc";
 121         };
 122
 123         /* External SCIF clock - to be overridden by boards that provide it */
 124         scif_clk: scif {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <0>;
 128         };
 129
 130         soc {
 131                 compatible = "simple-bus";
 132                 interrupt-parent = <&gic>;
 133                 #address-cells = <2>;
 134                 #size-cells = <2>;
 135                 ranges;
 136
 137                 rwdt: watchdog@e6020000 {
 138                         compatible = "renesas,r8a774a1-wdt",
 139                                      "renesas,rcar-gen3-wdt";
 140                         reg = <0 0xe6020000 0 0x0c>;
 141                         clocks = <&cpg CPG_MOD 402>;
 142                         power-domains = <&sysc 32>;
 143                         resets = <&cpg 402>;
 144                         status = "disabled";
 145                 };
 146
 147                 gpio0: gpio@e6050000 {
 148                         compatible = "renesas,gpio-r8a774a1",
 149                                      "renesas,rcar-gen3-gpio";
 150                         reg = <0 0xe6050000 0 0x50>;
 151                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 152                         #gpio-cells = <2>;
 153                         gpio-controller;
 154                         gpio-ranges = <&pfc 0 0 16>;
 155                         #interrupt-cells = <2>;
 156                         interrupt-controller;
 157                         clocks = <&cpg CPG_MOD 912>;
 158                         power-domains = <&sysc 32>;
 159                         resets = <&cpg 912>;
 160                 };
 161
 162                 gpio1: gpio@e6051000 {
 163                         compatible = "renesas,gpio-r8a774a1",
 164                                      "renesas,rcar-gen3-gpio";
 165                         reg = <0 0xe6051000 0 0x50>;
 166                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 167                         #gpio-cells = <2>;
 168                         gpio-controller;
 169                         gpio-ranges = <&pfc 0 32 29>;
 170                         #interrupt-cells = <2>;
 171                         interrupt-controller;
 172                         clocks = <&cpg CPG_MOD 911>;
 173                         power-domains = <&sysc 32>;
 174                         resets = <&cpg 911>;
 175                 };
 176
 177                 gpio2: gpio@e6052000 {
 178                         compatible = "renesas,gpio-r8a774a1",
 179                                      "renesas,rcar-gen3-gpio";
 180                         reg = <0 0xe6052000 0 0x50>;
 181                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 182                         #gpio-cells = <2>;
 183                         gpio-controller;
 184                         gpio-ranges = <&pfc 0 64 15>;
 185                         #interrupt-cells = <2>;
 186                         interrupt-controller;
 187                         clocks = <&cpg CPG_MOD 910>;
 188                         power-domains = <&sysc 32>;
 189                         resets = <&cpg 910>;
 190                 };
 191
 192                 gpio3: gpio@e6053000 {
 193                         compatible = "renesas,gpio-r8a774a1",
 194                                      "renesas,rcar-gen3-gpio";
 195                         reg = <0 0xe6053000 0 0x50>;
 196                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 197                         #gpio-cells = <2>;
 198                         gpio-controller;
 199                         gpio-ranges = <&pfc 0 96 16>;
 200                         #interrupt-cells = <2>;
 201                         interrupt-controller;
 202                         clocks = <&cpg CPG_MOD 909>;
 203                         power-domains = <&sysc 32>;
 204                         resets = <&cpg 909>;
 205                 };
 206
 207                 gpio4: gpio@e6054000 {
 208                         compatible = "renesas,gpio-r8a774a1",
 209                                      "renesas,rcar-gen3-gpio";
 210                         reg = <0 0xe6054000 0 0x50>;
 211                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 212                         #gpio-cells = <2>;
 213                         gpio-controller;
 214                         gpio-ranges = <&pfc 0 128 18>;
 215                         #interrupt-cells = <2>;
 216                         interrupt-controller;
 217                         clocks = <&cpg CPG_MOD 908>;
 218                         power-domains = <&sysc 32>;
 219                         resets = <&cpg 908>;
 220                 };
 221
 222                 gpio5: gpio@e6055000 {
 223                         compatible = "renesas,gpio-r8a774a1",
 224                                      "renesas,rcar-gen3-gpio";
 225                         reg = <0 0xe6055000 0 0x50>;
 226                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 227                         #gpio-cells = <2>;
 228                         gpio-controller;
 229                         gpio-ranges = <&pfc 0 160 26>;
 230                         #interrupt-cells = <2>;
 231                         interrupt-controller;
 232                         clocks = <&cpg CPG_MOD 907>;
 233                         power-domains = <&sysc 32>;
 234                         resets = <&cpg 907>;
 235                 };
 236
 237                 gpio6: gpio@e6055400 {
 238                         compatible = "renesas,gpio-r8a774a1",
 239                                      "renesas,rcar-gen3-gpio";
 240                         reg = <0 0xe6055400 0 0x50>;
 241                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 242                         #gpio-cells = <2>;
 243                         gpio-controller;
 244                         gpio-ranges = <&pfc 0 192 32>;
 245                         #interrupt-cells = <2>;
 246                         interrupt-controller;
 247                         clocks = <&cpg CPG_MOD 906>;
 248                         power-domains = <&sysc 32>;
 249                         resets = <&cpg 906>;
 250                 };
 251
 252                 gpio7: gpio@e6055800 {
 253                         compatible = "renesas,gpio-r8a774a1",
 254                                      "renesas,rcar-gen3-gpio";
 255                         reg = <0 0xe6055800 0 0x50>;
 256                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 257                         #gpio-cells = <2>;
 258                         gpio-controller;
 259                         gpio-ranges = <&pfc 0 224 4>;
 260                         #interrupt-cells = <2>;
 261                         interrupt-controller;
 262                         clocks = <&cpg CPG_MOD 905>;
 263                         power-domains = <&sysc 32>;
 264                         resets = <&cpg 905>;
 265                 };
 266
 267                 pfc: pin-controller@e6060000 {
 268                         compatible = "renesas,pfc-r8a774a1";
 269                         reg = <0 0xe6060000 0 0x50c>;
 270                 };
 271
 272                 cpg: clock-controller@e6150000 {
 273                         compatible = "renesas,r8a774a1-cpg-mssr";
 274                         reg = <0 0xe6150000 0 0x0bb0>;
 275                         clocks = <&extal_clk>, <&extalr_clk>;
 276                         clock-names = "extal", "extalr";
 277                         #clock-cells = <2>;
 278                         #power-domain-cells = <0>;
 279                         #reset-cells = <1>;
 280                 };
 281
 282                 rst: reset-controller@e6160000 {
 283                         compatible = "renesas,r8a774a1-rst";
 284                         reg = <0 0xe6160000 0 0x018c>;
 285                 };
 286
 287                 sysc: system-controller@e6180000 {
 288                         compatible = "renesas,r8a774a1-sysc";
 289                         reg = <0 0xe6180000 0 0x0400>;
 290                         #power-domain-cells = <1>;
 291                 };
 292
 293                 tsc: thermal@e6198000 {
 294                         compatible = "renesas,r8a774a1-thermal";
 295                         reg = <0 0xe6198000 0 0x100>,
 296                               <0 0xe61a0000 0 0x100>,
 297                               <0 0xe61a8000 0 0x100>;
 298                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&cpg CPG_MOD 522>;
 302                         power-domains = <&sysc 32>;
 303                         resets = <&cpg 522>;
 304                         #thermal-sensor-cells = <1>;
 305                         status = "okay";
 306                 };
 307
 308                 intc_ex: interrupt-controller@e61c0000 {
 309                         compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
 310                         #interrupt-cells = <2>;
 311                         interrupt-controller;
 312                         reg = <0 0xe61c0000 0 0x200>;
 313                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 314                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 315                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 316                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 317                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 318                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 319                         clocks = <&cpg CPG_MOD 407>;
 320                         power-domains = <&sysc 32>;
 321                         resets = <&cpg 407>;
 322                 };
 323
 324                 i2c0: i2c@e6500000 {
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         compatible = "renesas,i2c-r8a774a1",
 328                                      "renesas,rcar-gen3-i2c";
 329                         reg = <0 0xe6500000 0 0x40>;
 330                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&cpg CPG_MOD 931>;
 332                         power-domains = <&sysc 32>;
 333                         resets = <&cpg 931>;
 334                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 335                                <&dmac2 0x91>, <&dmac2 0x90>;
 336                         dma-names = "tx", "rx", "tx", "rx";
 337                         i2c-scl-internal-delay-ns = <110>;
 338                         status = "disabled";
 339                 };
 340
 341                 i2c1: i2c@e6508000 {
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         compatible = "renesas,i2c-r8a774a1",
 345                                      "renesas,rcar-gen3-i2c";
 346                         reg = <0 0xe6508000 0 0x40>;
 347                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&cpg CPG_MOD 930>;
 349                         power-domains = <&sysc 32>;
 350                         resets = <&cpg 930>;
 351                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 352                                <&dmac2 0x93>, <&dmac2 0x92>;
 353                         dma-names = "tx", "rx", "tx", "rx";
 354                         i2c-scl-internal-delay-ns = <6>;
 355                         status = "disabled";
 356                 };
 357
 358                 i2c2: i2c@e6510000 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         compatible = "renesas,i2c-r8a774a1",
 362                                      "renesas,rcar-gen3-i2c";
 363                         reg = <0 0xe6510000 0 0x40>;
 364                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&cpg CPG_MOD 929>;
 366                         power-domains = <&sysc 32>;
 367                         resets = <&cpg 929>;
 368                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 369                                <&dmac2 0x95>, <&dmac2 0x94>;
 370                         dma-names = "tx", "rx", "tx", "rx";
 371                         i2c-scl-internal-delay-ns = <6>;
 372                         status = "disabled";
 373                 };
 374
 375                 i2c3: i2c@e66d0000 {
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         compatible = "renesas,i2c-r8a774a1",
 379                                      "renesas,rcar-gen3-i2c";
 380                         reg = <0 0xe66d0000 0 0x40>;
 381                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&cpg CPG_MOD 928>;
 383                         power-domains = <&sysc 32>;
 384                         resets = <&cpg 928>;
 385                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 386                         dma-names = "tx", "rx";
 387                         i2c-scl-internal-delay-ns = <110>;
 388                         status = "disabled";
 389                 };
 390
 391                 i2c4: i2c@e66d8000 {
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         compatible = "renesas,i2c-r8a774a1",
 395                                      "renesas,rcar-gen3-i2c";
 396                         reg = <0 0xe66d8000 0 0x40>;
 397                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&cpg CPG_MOD 927>;
 399                         power-domains = <&sysc 32>;
 400                         resets = <&cpg 927>;
 401                         dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 402                         dma-names = "tx", "rx";
 403                         i2c-scl-internal-delay-ns = <110>;
 404                         status = "disabled";
 405                 };
 406
 407                 i2c5: i2c@e66e0000 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "renesas,i2c-r8a774a1",
 411                                      "renesas,rcar-gen3-i2c";
 412                         reg = <0 0xe66e0000 0 0x40>;
 413                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&cpg CPG_MOD 919>;
 415                         power-domains = <&sysc 32>;
 416                         resets = <&cpg 919>;
 417                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 418                         dma-names = "tx", "rx";
 419                         i2c-scl-internal-delay-ns = <110>;
 420                         status = "disabled";
 421                 };
 422
 423                 i2c6: i2c@e66e8000 {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         compatible = "renesas,i2c-r8a774a1",
 427                                      "renesas,rcar-gen3-i2c";
 428                         reg = <0 0xe66e8000 0 0x40>;
 429                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&cpg CPG_MOD 918>;
 431                         power-domains = <&sysc 32>;
 432                         resets = <&cpg 918>;
 433                         dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 434                         dma-names = "tx", "rx";
 435                         i2c-scl-internal-delay-ns = <6>;
 436                         status = "disabled";
 437                 };
 438
 439                 i2c_dvfs: i2c@e60b0000 {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         compatible = "renesas,iic-r8a774a1",
 443                                      "renesas,rcar-gen3-iic",
 444                                      "renesas,rmobile-iic";
 445                         reg = <0 0xe60b0000 0 0x425>;
 446                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&cpg CPG_MOD 926>;
 448                         power-domains = <&sysc 32>;
 449                         resets = <&cpg 926>;
 450                         dmas = <&dmac0 0x11>, <&dmac0 0x10>;
 451                         dma-names = "tx", "rx";
 452                         status = "disabled";
 453                 };
 454
 455                 hscif0: serial@e6540000 {
 456                         compatible = "renesas,hscif-r8a774a1",
 457                                      "renesas,rcar-gen3-hscif",
 458                                      "renesas,hscif";
 459                         reg = <0 0xe6540000 0 0x60>;
 460                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&cpg CPG_MOD 520>,
 462                                  <&cpg CPG_CORE 19>,
 463                                  <&scif_clk>;
 464                         clock-names = "fck", "brg_int", "scif_clk";
 465                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 466                                <&dmac2 0x31>, <&dmac2 0x30>;
 467                         dma-names = "tx", "rx", "tx", "rx";
 468                         power-domains = <&sysc 32>;
 469                         resets = <&cpg 520>;
 470                         status = "disabled";
 471                 };
 472
 473                 hscif1: serial@e6550000 {
 474                         compatible = "renesas,hscif-r8a774a1",
 475                                      "renesas,rcar-gen3-hscif",
 476                                      "renesas,hscif";
 477                         reg = <0 0xe6550000 0 0x60>;
 478                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&cpg CPG_MOD 519>,
 480                                  <&cpg CPG_CORE 19>,
 481                                  <&scif_clk>;
 482                         clock-names = "fck", "brg_int", "scif_clk";
 483                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 484                                <&dmac2 0x33>, <&dmac2 0x32>;
 485                         dma-names = "tx", "rx", "tx", "rx";
 486                         power-domains = <&sysc 32>;
 487                         resets = <&cpg 519>;
 488                         status = "disabled";
 489                 };
 490
 491                 hscif2: serial@e6560000 {
 492                         compatible = "renesas,hscif-r8a774a1",
 493                                      "renesas,rcar-gen3-hscif",
 494                                      "renesas,hscif";
 495                         reg = <0 0xe6560000 0 0x60>;
 496                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&cpg CPG_MOD 518>,
 498                                  <&cpg CPG_CORE 19>,
 499                                  <&scif_clk>;
 500                         clock-names = "fck", "brg_int", "scif_clk";
 501                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 502                                <&dmac2 0x35>, <&dmac2 0x34>;
 503                         dma-names = "tx", "rx", "tx", "rx";
 504                         power-domains = <&sysc 32>;
 505                         resets = <&cpg 518>;
 506                         status = "disabled";
 507                 };
 508
 509                 hscif3: serial@e66a0000 {
 510                         compatible = "renesas,hscif-r8a774a1",
 511                                      "renesas,rcar-gen3-hscif",
 512                                      "renesas,hscif";
 513                         reg = <0 0xe66a0000 0 0x60>;
 514                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&cpg CPG_MOD 517>,
 516                                  <&cpg CPG_CORE 19>,
 517                                  <&scif_clk>;
 518                         clock-names = "fck", "brg_int", "scif_clk";
 519                         dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 520                         dma-names = "tx", "rx";
 521                         power-domains = <&sysc 32>;
 522                         resets = <&cpg 517>;
 523                         status = "disabled";
 524                 };
 525
 526                 hscif4: serial@e66b0000 {
 527                         compatible = "renesas,hscif-r8a774a1",
 528                                      "renesas,rcar-gen3-hscif",
 529                                      "renesas,hscif";
 530                         reg = <0 0xe66b0000 0 0x60>;
 531                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&cpg CPG_MOD 516>,
 533                                  <&cpg CPG_CORE 19>,
 534                                  <&scif_clk>;
 535                         clock-names = "fck", "brg_int", "scif_clk";
 536                         dmas = <&dmac0 0x39>, <&dmac0 0x38>;
 537                         dma-names = "tx", "rx";
 538                         power-domains = <&sysc 32>;
 539                         resets = <&cpg 516>;
 540                         status = "disabled";
 541                 };
 542
 543                 dmac0: dma-controller@e6700000 {
 544                         compatible = "renesas,dmac-r8a774a1",
 545                                      "renesas,rcar-dmac";
 546                         reg = <0 0xe6700000 0 0x10000>;
 547                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
 548                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 549                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 550                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 551                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 552                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 553                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 554                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 555                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 556                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 557                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 558                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 559                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 560                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 561                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 562                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
 563                                       GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 564                         interrupt-names = "error",
 565                                         "ch0", "ch1", "ch2", "ch3",
 566                                         "ch4", "ch5", "ch6", "ch7",
 567                                         "ch8", "ch9", "ch10", "ch11",
 568                                         "ch12", "ch13", "ch14", "ch15";
 569                         clocks = <&cpg CPG_MOD 219>;
 570                         clock-names = "fck";
 571                         power-domains = <&sysc 32>;
 572                         resets = <&cpg 219>;
 573                         #dma-cells = <1>;
 574                         dma-channels = <16>;
 575                 };
 576
 577                 dmac1: dma-controller@e7300000 {
 578                         compatible = "renesas,dmac-r8a774a1",
 579                                      "renesas,rcar-dmac";
 580                         reg = <0 0xe7300000 0 0x10000>;
 581                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 582                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 583                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 584                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 585                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 586                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 587                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 588                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 589                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 590                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 591                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 592                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 593                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 594                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 595                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 596                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 597                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 598                         interrupt-names = "error",
 599                                         "ch0", "ch1", "ch2", "ch3",
 600                                         "ch4", "ch5", "ch6", "ch7",
 601                                         "ch8", "ch9", "ch10", "ch11",
 602                                         "ch12", "ch13", "ch14", "ch15";
 603                         clocks = <&cpg CPG_MOD 218>;
 604                         clock-names = "fck";
 605                         power-domains = <&sysc 32>;
 606                         resets = <&cpg 218>;
 607                         #dma-cells = <1>;
 608                         dma-channels = <16>;
 609                 };
 610
 611                 dmac2: dma-controller@e7310000 {
 612                         compatible = "renesas,dmac-r8a774a1",
 613                                      "renesas,rcar-dmac";
 614                         reg = <0 0xe7310000 0 0x10000>;
 615                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
 616                                       GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
 617                                       GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
 618                                       GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
 619                                       GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
 620                                       GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
 621                                       GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
 622                                       GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
 623                                       GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
 624                                       GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
 625                                       GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
 626                                       GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
 627                                       GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
 628                                       GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
 629                                       GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
 630                                       GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
 631                                       GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 632                         interrupt-names = "error",
 633                                         "ch0", "ch1", "ch2", "ch3",
 634                                         "ch4", "ch5", "ch6", "ch7",
 635                                         "ch8", "ch9", "ch10", "ch11",
 636                                         "ch12", "ch13", "ch14", "ch15";
 637                         clocks = <&cpg CPG_MOD 217>;
 638                         clock-names = "fck";
 639                         power-domains = <&sysc 32>;
 640                         resets = <&cpg 217>;
 641                         #dma-cells = <1>;
 642                         dma-channels = <16>;
 643                 };
 644
 645                 avb: ethernet@e6800000 {
 646                         compatible = "renesas,etheravb-r8a774a1",
 647                                      "renesas,etheravb-rcar-gen3";
 648                         reg = <0 0xe6800000 0 0x800>;
 649                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 653                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 654                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 655                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 656                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 657                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 658                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 665                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 666                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 674                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 675                                           "ch4", "ch5", "ch6", "ch7",
 676                                           "ch8", "ch9", "ch10", "ch11",
 677                                           "ch12", "ch13", "ch14", "ch15",
 678                                           "ch16", "ch17", "ch18", "ch19",
 679                                           "ch20", "ch21", "ch22", "ch23",
 680                                           "ch24";
 681                         clocks = <&cpg CPG_MOD 812>;
 682                         power-domains = <&sysc 32>;
 683                         resets = <&cpg 812>;
 684                         phy-mode = "rgmii";
 685                         #address-cells = <1>;
 686                         #size-cells = <0>;
 687                         status = "disabled";
 688                 };
 689
 690                 scif0: serial@e6e60000 {
 691                         compatible = "renesas,scif-r8a774a1",
 692                                      "renesas,rcar-gen3-scif", "renesas,scif";
 693                         reg = <0 0xe6e60000 0 0x40>;
 694                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&cpg CPG_MOD 207>,
 696                                  <&cpg CPG_CORE 19>,
 697                                  <&scif_clk>;
 698                         clock-names = "fck", "brg_int", "scif_clk";
 699                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 700                                <&dmac2 0x51>, <&dmac2 0x50>;
 701                         dma-names = "tx", "rx", "tx", "rx";
 702                         power-domains = <&sysc 32>;
 703                         resets = <&cpg 207>;
 704                         status = "disabled";
 705                 };
 706
 707                 scif1: serial@e6e68000 {
 708                         compatible = "renesas,scif-r8a774a1",
 709                                      "renesas,rcar-gen3-scif", "renesas,scif";
 710                         reg = <0 0xe6e68000 0 0x40>;
 711                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 712                         clocks = <&cpg CPG_MOD 206>,
 713                                  <&cpg CPG_CORE 19>,
 714                                  <&scif_clk>;
 715                         clock-names = "fck", "brg_int", "scif_clk";
 716                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 717                                <&dmac2 0x53>, <&dmac2 0x52>;
 718                         dma-names = "tx", "rx", "tx", "rx";
 719                         power-domains = <&sysc 32>;
 720                         resets = <&cpg 206>;
 721                         status = "disabled";
 722                 };
 723
 724                 scif2: serial@e6e88000 {
 725                         compatible = "renesas,scif-r8a774a1",
 726                                      "renesas,rcar-gen3-scif", "renesas,scif";
 727                         reg = <0 0xe6e88000 0 0x40>;
 728                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 729                         clocks = <&cpg CPG_MOD 310>,
 730                                  <&cpg CPG_CORE 19>,
 731                                  <&scif_clk>;
 732                         clock-names = "fck", "brg_int", "scif_clk";
 733                         power-domains = <&sysc 32>;
 734                         resets = <&cpg 310>;
 735                         status = "disabled";
 736                 };
 737
 738                 scif3: serial@e6c50000 {
 739                         compatible = "renesas,scif-r8a774a1",
 740                                      "renesas,rcar-gen3-scif", "renesas,scif";
 741                         reg = <0 0xe6c50000 0 0x40>;
 742                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 743                         clocks = <&cpg CPG_MOD 204>,
 744                                  <&cpg CPG_CORE 19>,
 745                                  <&scif_clk>;
 746                         clock-names = "fck", "brg_int", "scif_clk";
 747                         dmas = <&dmac0 0x57>, <&dmac0 0x56>;
 748                         dma-names = "tx", "rx";
 749                         power-domains = <&sysc 32>;
 750                         resets = <&cpg 204>;
 751                         status = "disabled";
 752                 };
 753
 754                 scif4: serial@e6c40000 {
 755                         compatible = "renesas,scif-r8a774a1",
 756                                      "renesas,rcar-gen3-scif", "renesas,scif";
 757                         reg = <0 0xe6c40000 0 0x40>;
 758                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 759                         clocks = <&cpg CPG_MOD 203>,
 760                                  <&cpg CPG_CORE 19>,
 761                                  <&scif_clk>;
 762                         clock-names = "fck", "brg_int", "scif_clk";
 763                         dmas = <&dmac0 0x59>, <&dmac0 0x58>;
 764                         dma-names = "tx", "rx";
 765                         power-domains = <&sysc 32>;
 766                         resets = <&cpg 203>;
 767                         status = "disabled";
 768                 };
 769
 770                 scif5: serial@e6f30000 {
 771                         compatible = "renesas,scif-r8a774a1",
 772                                      "renesas,rcar-gen3-scif", "renesas,scif";
 773                         reg = <0 0xe6f30000 0 0x40>;
 774                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 775                         clocks = <&cpg CPG_MOD 202>,
 776                                  <&cpg CPG_CORE 19>,
 777                                  <&scif_clk>;
 778                         clock-names = "fck", "brg_int", "scif_clk";
 779                         dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
 780                                <&dmac2 0x5b>, <&dmac2 0x5a>;
 781                         dma-names = "tx", "rx", "tx", "rx";
 782                         power-domains = <&sysc 32>;
 783                         resets = <&cpg 202>;
 784                         status = "disabled";
 785                 };
 786
 787                 sdhi0: sd@ee100000 {
 788                         compatible = "renesas,sdhi-r8a774a1",
 789                                      "renesas,rcar-gen3-sdhi";
 790                         reg = <0 0xee100000 0 0x2000>;
 791                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 792                         clocks = <&cpg CPG_MOD 314>;
 793                         max-frequency = <200000000>;
 794                         power-domains = <&sysc 32>;
 795                         resets = <&cpg 314>;
 796                         status = "disabled";
 797                 };
 798
 799                 sdhi1: sd@ee120000 {
 800                         compatible = "renesas,sdhi-r8a774a1",
 801                                      "renesas,rcar-gen3-sdhi";
 802                         reg = <0 0xee120000 0 0x2000>;
 803                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 804                         clocks = <&cpg CPG_MOD 313>;
 805                         max-frequency = <200000000>;
 806                         power-domains = <&sysc 32>;
 807                         resets = <&cpg 313>;
 808                         status = "disabled";
 809                 };
 810
 811                 sdhi2: sd@ee140000 {
 812                         compatible = "renesas,sdhi-r8a774a1",
 813                                      "renesas,rcar-gen3-sdhi";
 814                         reg = <0 0xee140000 0 0x2000>;
 815                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&cpg CPG_MOD 312>;
 817                         max-frequency = <200000000>;
 818                         power-domains = <&sysc 32>;
 819                         resets = <&cpg 312>;
 820                         status = "disabled";
 821                 };
 822
 823                 sdhi3: sd@ee160000 {
 824                         compatible = "renesas,sdhi-r8a774a1",
 825                                      "renesas,rcar-gen3-sdhi";
 826                         reg = <0 0xee160000 0 0x2000>;
 827                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 828                         clocks = <&cpg CPG_MOD 311>;
 829                         max-frequency = <200000000>;
 830                         power-domains = <&sysc 32>;
 831                         resets = <&cpg 311>;
 832                         status = "disabled";
 833                 };
 834
 835                 gic: interrupt-controller@f1010000 {
 836                         compatible = "arm,gic-400";
 837                         #interrupt-cells = <3>;
 838                         #address-cells = <0>;
 839                         interrupt-controller;
 840                         reg = <0x0 0xf1010000 0 0x1000>,
 841                               <0x0 0xf1020000 0 0x20000>,
 842                               <0x0 0xf1040000 0 0x20000>,
 843                               <0x0 0xf1060000 0 0x20000>;
 844                         interrupts = <GIC_PPI 9
 845                                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 846                         clocks = <&cpg CPG_MOD 408>;
 847                         clock-names = "clk";
 848                         power-domains = <&sysc 32>;
 849                         resets = <&cpg 408>;
 850                 };
 851
 852                 prr: chipid@fff00044 {
 853                         compatible = "renesas,prr";
 854                         reg = <0 0xfff00044 0 4>;
 855                 };
 856         };
 857
 858         thermal-zones {
 859                 sensor_thermal1: sensor-thermal1 {
 860                         polling-delay-passive = <250>;
 861                         polling-delay = <1000>;
 862                         thermal-sensors = <&tsc 0>;
 863
 864                         trips {
 865                                 sensor1_crit: sensor1-crit {
 866                                         temperature = <120000>;
 867                                         hysteresis = <1000>;
 868                                         type = "critical";
 869                                 };
 870                         };
 871                 };
 872
 873                 sensor_thermal2: sensor-thermal2 {
 874                         polling-delay-passive = <250>;
 875                         polling-delay = <1000>;
 876                         thermal-sensors = <&tsc 1>;
 877
 878                         trips {
 879                                 sensor2_crit: sensor2-crit {
 880                                         temperature = <120000>;
 881                                         hysteresis = <1000>;
 882                                         type = "critical";
 883                                 };
 884                         };
 885
 886                 };
 887
 888                 sensor_thermal3: sensor-thermal3 {
 889                         polling-delay-passive = <250>;
 890                         polling-delay = <1000>;
 891                         thermal-sensors = <&tsc 2>;
 892
 893                         trips {
 894                                 sensor3_crit: sensor3-crit {
 895                                         temperature = <120000>;
 896                                         hysteresis = <1000>;
 897                                         type = "critical";
 898                                 };
 899                         };
 900                 };
 901         };
 902
 903         timer {
 904                 compatible = "arm,armv8-timer";
 905                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 906                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 907                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 908                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 909         };
 910
 911         /* External USB clocks - can be overridden by the board */
 912         usb3s0_clk: usb3s0 {
 913                 compatible = "fixed-clock";
 914                 #clock-cells = <0>;
 915                 clock-frequency = <0>;
 916         };
 917
 918         usb_extal_clk: usb_extal {
 919                 compatible = "fixed-clock";
 920                 #clock-cells = <0>;
 921                 clock-frequency = <0>;
 922         };
 923 };