2 * File: arch/blackfin/kernel/bfin_dma_5xx.c
7 * Description: This file contains the simple DMA Implementation for Blackfin
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/interrupt.h>
34 #include <linux/kernel.h>
35 #include <linux/param.h>
37 #include <asm/blackfin.h>
39 #include <asm/cacheflush.h>
41 /* Remove unused code not exported by symbol or internally called */
42 #define REMOVE_DEAD_CODE
44 /**************************************************************************
46 ***************************************************************************/
48 static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
50 /*------------------------------------------------------------------------------
51 * Set the Buffer Clear bit in the Configuration register of specific DMA
52 * channel. This will stop the descriptor based DMA operation.
53 *-----------------------------------------------------------------------------*/
54 static void clear_dma_buffer(unsigned int channel)
56 dma_ch[channel].regs->cfg |= RESTART;
58 dma_ch[channel].regs->cfg &= ~RESTART;
62 static int __init blackfin_dma_init(void)
66 printk(KERN_INFO "Blackfin DMA Controller\n");
68 for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
69 dma_ch[i].chan_status = DMA_CHANNEL_FREE;
70 dma_ch[i].regs = base_addr[i];
71 mutex_init(&(dma_ch[i].dmalock));
73 /* Mark MEMDMA Channel 0 as requested since we're using it internally */
74 dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED;
75 dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED;
77 #if defined(CONFIG_DEB_DMA_URGENT)
78 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
79 | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
84 arch_initcall(blackfin_dma_init);
86 /*------------------------------------------------------------------------------
87 * Request the specific DMA channel from the system.
88 *-----------------------------------------------------------------------------*/
89 int request_dma(unsigned int channel, char *device_id)
92 pr_debug("request_dma() : BEGIN \n");
93 mutex_lock(&(dma_ch[channel].dmalock));
95 if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
96 || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
97 mutex_unlock(&(dma_ch[channel].dmalock));
98 pr_debug("DMA CHANNEL IN USE \n");
101 dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
102 pr_debug("DMA CHANNEL IS ALLOCATED \n");
105 mutex_unlock(&(dma_ch[channel].dmalock));
107 dma_ch[channel].device_id = device_id;
108 dma_ch[channel].irq_callback = NULL;
110 /* This is to be enabled by putting a restriction -
111 * you have to request DMA, before doing any operations on
114 pr_debug("request_dma() : END \n");
117 EXPORT_SYMBOL(request_dma);
119 int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
123 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
124 && channel < MAX_BLACKFIN_DMA_CHANNEL));
126 if (callback != NULL) {
128 ret_irq = channel2irq(channel);
130 dma_ch[channel].data = data;
133 request_irq(ret_irq, (void *)callback, IRQF_DISABLED,
134 dma_ch[channel].device_id, data);
137 "Request irq in DMA engine failed.\n");
140 dma_ch[channel].irq_callback = callback;
144 EXPORT_SYMBOL(set_dma_callback);
146 void free_dma(unsigned int channel)
150 pr_debug("freedma() : BEGIN \n");
151 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
152 && channel < MAX_BLACKFIN_DMA_CHANNEL));
155 disable_dma(channel);
156 clear_dma_buffer(channel);
158 if (dma_ch[channel].irq_callback != NULL) {
159 ret_irq = channel2irq(channel);
160 free_irq(ret_irq, dma_ch[channel].data);
163 /* Clear the DMA Variable in the Channel */
164 mutex_lock(&(dma_ch[channel].dmalock));
165 dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
166 mutex_unlock(&(dma_ch[channel].dmalock));
168 pr_debug("freedma() : END \n");
170 EXPORT_SYMBOL(free_dma);
172 void dma_enable_irq(unsigned int channel)
176 pr_debug("dma_enable_irq() : BEGIN \n");
177 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
178 && channel < MAX_BLACKFIN_DMA_CHANNEL));
180 ret_irq = channel2irq(channel);
183 EXPORT_SYMBOL(dma_enable_irq);
185 void dma_disable_irq(unsigned int channel)
189 pr_debug("dma_disable_irq() : BEGIN \n");
190 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
191 && channel < MAX_BLACKFIN_DMA_CHANNEL));
193 ret_irq = channel2irq(channel);
194 disable_irq(ret_irq);
196 EXPORT_SYMBOL(dma_disable_irq);
198 int dma_channel_active(unsigned int channel)
200 if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) {
206 EXPORT_SYMBOL(dma_channel_active);
208 /*------------------------------------------------------------------------------
209 * stop the specific DMA channel.
210 *-----------------------------------------------------------------------------*/
211 void disable_dma(unsigned int channel)
213 pr_debug("stop_dma() : BEGIN \n");
215 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
216 && channel < MAX_BLACKFIN_DMA_CHANNEL));
218 dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
220 dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
221 /* Needs to be enabled Later */
222 pr_debug("stop_dma() : END \n");
225 EXPORT_SYMBOL(disable_dma);
227 void enable_dma(unsigned int channel)
229 pr_debug("enable_dma() : BEGIN \n");
231 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
232 && channel < MAX_BLACKFIN_DMA_CHANNEL));
234 dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
235 dma_ch[channel].regs->curr_x_count = 0;
236 dma_ch[channel].regs->curr_y_count = 0;
238 dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
240 pr_debug("enable_dma() : END \n");
243 EXPORT_SYMBOL(enable_dma);
245 /*------------------------------------------------------------------------------
246 * Set the Start Address register for the specific DMA channel
247 * This function can be used for register based DMA,
248 * to setup the start address
249 * addr: Starting address of the DMA Data to be transferred.
250 *-----------------------------------------------------------------------------*/
251 void set_dma_start_addr(unsigned int channel, unsigned long addr)
253 pr_debug("set_dma_start_addr() : BEGIN \n");
255 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
256 && channel < MAX_BLACKFIN_DMA_CHANNEL));
258 dma_ch[channel].regs->start_addr = addr;
260 pr_debug("set_dma_start_addr() : END\n");
262 EXPORT_SYMBOL(set_dma_start_addr);
264 void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
266 pr_debug("set_dma_next_desc_addr() : BEGIN \n");
268 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
269 && channel < MAX_BLACKFIN_DMA_CHANNEL));
271 dma_ch[channel].regs->next_desc_ptr = addr;
273 pr_debug("set_dma_next_desc_addr() : END\n");
275 EXPORT_SYMBOL(set_dma_next_desc_addr);
277 void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr)
279 pr_debug("set_dma_curr_desc_addr() : BEGIN \n");
281 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
282 && channel < MAX_BLACKFIN_DMA_CHANNEL));
284 dma_ch[channel].regs->curr_desc_ptr = addr;
286 pr_debug("set_dma_curr_desc_addr() : END\n");
288 EXPORT_SYMBOL(set_dma_curr_desc_addr);
290 void set_dma_x_count(unsigned int channel, unsigned short x_count)
292 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
293 && channel < MAX_BLACKFIN_DMA_CHANNEL));
295 dma_ch[channel].regs->x_count = x_count;
298 EXPORT_SYMBOL(set_dma_x_count);
300 void set_dma_y_count(unsigned int channel, unsigned short y_count)
302 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
303 && channel < MAX_BLACKFIN_DMA_CHANNEL));
305 dma_ch[channel].regs->y_count = y_count;
308 EXPORT_SYMBOL(set_dma_y_count);
310 void set_dma_x_modify(unsigned int channel, short x_modify)
312 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
313 && channel < MAX_BLACKFIN_DMA_CHANNEL));
315 dma_ch[channel].regs->x_modify = x_modify;
318 EXPORT_SYMBOL(set_dma_x_modify);
320 void set_dma_y_modify(unsigned int channel, short y_modify)
322 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
323 && channel < MAX_BLACKFIN_DMA_CHANNEL));
325 dma_ch[channel].regs->y_modify = y_modify;
328 EXPORT_SYMBOL(set_dma_y_modify);
330 void set_dma_config(unsigned int channel, unsigned short config)
332 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
333 && channel < MAX_BLACKFIN_DMA_CHANNEL));
335 dma_ch[channel].regs->cfg = config;
338 EXPORT_SYMBOL(set_dma_config);
341 set_bfin_dma_config(char direction, char flow_mode,
342 char intr_mode, char dma_mode, char width)
344 unsigned short config;
347 ((direction << 1) | (width << 2) | (dma_mode << 4) |
348 (intr_mode << 6) | (flow_mode << 12) | RESTART);
351 EXPORT_SYMBOL(set_bfin_dma_config);
353 void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
355 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
356 && channel < MAX_BLACKFIN_DMA_CHANNEL));
358 dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8);
360 dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg;
364 EXPORT_SYMBOL(set_dma_sg);
366 void set_dma_curr_addr(unsigned int channel, unsigned long addr)
368 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
369 && channel < MAX_BLACKFIN_DMA_CHANNEL));
371 dma_ch[channel].regs->curr_addr_ptr = addr;
374 EXPORT_SYMBOL(set_dma_curr_addr);
376 /*------------------------------------------------------------------------------
377 * Get the DMA status of a specific DMA channel from the system.
378 *-----------------------------------------------------------------------------*/
379 unsigned short get_dma_curr_irqstat(unsigned int channel)
381 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
382 && channel < MAX_BLACKFIN_DMA_CHANNEL));
384 return dma_ch[channel].regs->irq_status;
386 EXPORT_SYMBOL(get_dma_curr_irqstat);
388 /*------------------------------------------------------------------------------
389 * Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt.
390 *-----------------------------------------------------------------------------*/
391 void clear_dma_irqstat(unsigned int channel)
393 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
394 && channel < MAX_BLACKFIN_DMA_CHANNEL));
395 dma_ch[channel].regs->irq_status |= 3;
397 EXPORT_SYMBOL(clear_dma_irqstat);
399 /*------------------------------------------------------------------------------
400 * Get current DMA xcount of a specific DMA channel from the system.
401 *-----------------------------------------------------------------------------*/
402 unsigned short get_dma_curr_xcount(unsigned int channel)
404 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
405 && channel < MAX_BLACKFIN_DMA_CHANNEL));
407 return dma_ch[channel].regs->curr_x_count;
409 EXPORT_SYMBOL(get_dma_curr_xcount);
411 /*------------------------------------------------------------------------------
412 * Get current DMA ycount of a specific DMA channel from the system.
413 *-----------------------------------------------------------------------------*/
414 unsigned short get_dma_curr_ycount(unsigned int channel)
416 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
417 && channel < MAX_BLACKFIN_DMA_CHANNEL));
419 return dma_ch[channel].regs->curr_y_count;
421 EXPORT_SYMBOL(get_dma_curr_ycount);
423 static void *__dma_memcpy(void *dest, const void *src, size_t size)
425 int direction; /* 1 - address decrease, 0 - address increase */
426 int flag_align; /* 1 - address aligned, 0 - address unaligned */
427 int flag_2D; /* 1 - 2D DMA needed, 0 - 1D DMA needed */
433 local_irq_save(flags);
435 if ((unsigned long)src < memory_end)
436 blackfin_dcache_flush_range((unsigned int)src,
437 (unsigned int)(src + size));
439 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
441 if ((unsigned long)src < (unsigned long)dest)
446 if ((((unsigned long)dest % 2) == 0) && (((unsigned long)src % 2) == 0)
447 && ((size % 2) == 0))
452 if (size > 0x10000) /* size > 64K */
457 /* Setup destination and source start address */
460 bfin_write_MDMA_D0_START_ADDR(dest + size - 2);
461 bfin_write_MDMA_S0_START_ADDR(src + size - 2);
463 bfin_write_MDMA_D0_START_ADDR(dest + size - 1);
464 bfin_write_MDMA_S0_START_ADDR(src + size - 1);
467 bfin_write_MDMA_D0_START_ADDR(dest);
468 bfin_write_MDMA_S0_START_ADDR(src);
471 /* Setup destination and source xcount */
474 bfin_write_MDMA_D0_X_COUNT(1024 / 2);
475 bfin_write_MDMA_S0_X_COUNT(1024 / 2);
477 bfin_write_MDMA_D0_X_COUNT(1024);
478 bfin_write_MDMA_S0_X_COUNT(1024);
480 bfin_write_MDMA_D0_Y_COUNT(size >> 10);
481 bfin_write_MDMA_S0_Y_COUNT(size >> 10);
484 bfin_write_MDMA_D0_X_COUNT(size / 2);
485 bfin_write_MDMA_S0_X_COUNT(size / 2);
487 bfin_write_MDMA_D0_X_COUNT(size);
488 bfin_write_MDMA_S0_X_COUNT(size);
492 /* Setup destination and source xmodify and ymodify */
495 bfin_write_MDMA_D0_X_MODIFY(-2);
496 bfin_write_MDMA_S0_X_MODIFY(-2);
498 bfin_write_MDMA_D0_Y_MODIFY(-2);
499 bfin_write_MDMA_S0_Y_MODIFY(-2);
502 bfin_write_MDMA_D0_X_MODIFY(-1);
503 bfin_write_MDMA_S0_X_MODIFY(-1);
505 bfin_write_MDMA_D0_Y_MODIFY(-1);
506 bfin_write_MDMA_S0_Y_MODIFY(-1);
511 bfin_write_MDMA_D0_X_MODIFY(2);
512 bfin_write_MDMA_S0_X_MODIFY(2);
514 bfin_write_MDMA_D0_Y_MODIFY(2);
515 bfin_write_MDMA_S0_Y_MODIFY(2);
518 bfin_write_MDMA_D0_X_MODIFY(1);
519 bfin_write_MDMA_S0_X_MODIFY(1);
521 bfin_write_MDMA_D0_Y_MODIFY(1);
522 bfin_write_MDMA_S0_Y_MODIFY(1);
527 /* Enable source DMA */
530 bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16);
531 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16);
533 bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D);
534 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D);
538 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
539 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
541 bfin_write_MDMA_S0_CONFIG(DMAEN);
542 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN);
546 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
549 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() |
550 (DMA_DONE | DMA_ERR));
552 bfin_write_MDMA_S0_CONFIG(0);
553 bfin_write_MDMA_D0_CONFIG(0);
555 if ((unsigned long)dest < memory_end)
556 blackfin_dcache_invalidate_range((unsigned int)dest,
557 (unsigned int)(dest + size));
558 local_irq_restore(flags);
563 void *dma_memcpy(void *dest, const void *src, size_t size)
569 bulk = (size >> 16) << 16;
572 __dma_memcpy(dest, src, bulk);
573 addr = __dma_memcpy(dest+bulk, src+bulk, rest);
576 EXPORT_SYMBOL(dma_memcpy);
578 void *safe_dma_memcpy(void *dest, const void *src, size_t size)
581 addr = dma_memcpy(dest, src, size);
584 EXPORT_SYMBOL(safe_dma_memcpy);
586 void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
590 local_irq_save(flags);
592 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
594 bfin_write_MDMA_D0_START_ADDR(addr);
595 bfin_write_MDMA_D0_X_COUNT(len);
596 bfin_write_MDMA_D0_X_MODIFY(0);
597 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
599 bfin_write_MDMA_S0_START_ADDR(buf);
600 bfin_write_MDMA_S0_X_COUNT(len);
601 bfin_write_MDMA_S0_X_MODIFY(1);
602 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
604 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
605 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
607 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
609 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
611 bfin_write_MDMA_S0_CONFIG(0);
612 bfin_write_MDMA_D0_CONFIG(0);
613 local_irq_restore(flags);
616 EXPORT_SYMBOL(dma_outsb);
619 void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
623 local_irq_save(flags);
624 bfin_write_MDMA_D0_START_ADDR(buf);
625 bfin_write_MDMA_D0_X_COUNT(len);
626 bfin_write_MDMA_D0_X_MODIFY(1);
627 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
629 bfin_write_MDMA_S0_START_ADDR(addr);
630 bfin_write_MDMA_S0_X_COUNT(len);
631 bfin_write_MDMA_S0_X_MODIFY(0);
632 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
634 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
635 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
637 blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
639 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
641 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
643 bfin_write_MDMA_S0_CONFIG(0);
644 bfin_write_MDMA_D0_CONFIG(0);
645 local_irq_restore(flags);
648 EXPORT_SYMBOL(dma_insb);
650 void dma_outsw(void __iomem *addr, const void *buf, unsigned short len)
654 local_irq_save(flags);
656 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
658 bfin_write_MDMA_D0_START_ADDR(addr);
659 bfin_write_MDMA_D0_X_COUNT(len);
660 bfin_write_MDMA_D0_X_MODIFY(0);
661 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
663 bfin_write_MDMA_S0_START_ADDR(buf);
664 bfin_write_MDMA_S0_X_COUNT(len);
665 bfin_write_MDMA_S0_X_MODIFY(2);
666 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
668 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
669 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
671 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
673 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
675 bfin_write_MDMA_S0_CONFIG(0);
676 bfin_write_MDMA_D0_CONFIG(0);
677 local_irq_restore(flags);
680 EXPORT_SYMBOL(dma_outsw);
682 void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
686 local_irq_save(flags);
688 bfin_write_MDMA_D0_START_ADDR(buf);
689 bfin_write_MDMA_D0_X_COUNT(len);
690 bfin_write_MDMA_D0_X_MODIFY(2);
691 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
693 bfin_write_MDMA_S0_START_ADDR(addr);
694 bfin_write_MDMA_S0_X_COUNT(len);
695 bfin_write_MDMA_S0_X_MODIFY(0);
696 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
698 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
699 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
701 blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
703 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
705 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
707 bfin_write_MDMA_S0_CONFIG(0);
708 bfin_write_MDMA_D0_CONFIG(0);
709 local_irq_restore(flags);
712 EXPORT_SYMBOL(dma_insw);
714 void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
718 local_irq_save(flags);
720 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
722 bfin_write_MDMA_D0_START_ADDR(addr);
723 bfin_write_MDMA_D0_X_COUNT(len);
724 bfin_write_MDMA_D0_X_MODIFY(0);
725 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
727 bfin_write_MDMA_S0_START_ADDR(buf);
728 bfin_write_MDMA_S0_X_COUNT(len);
729 bfin_write_MDMA_S0_X_MODIFY(4);
730 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
732 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
733 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
735 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
737 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
739 bfin_write_MDMA_S0_CONFIG(0);
740 bfin_write_MDMA_D0_CONFIG(0);
741 local_irq_restore(flags);
744 EXPORT_SYMBOL(dma_outsl);
746 void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
750 local_irq_save(flags);
752 bfin_write_MDMA_D0_START_ADDR(buf);
753 bfin_write_MDMA_D0_X_COUNT(len);
754 bfin_write_MDMA_D0_X_MODIFY(4);
755 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
757 bfin_write_MDMA_S0_START_ADDR(addr);
758 bfin_write_MDMA_S0_X_COUNT(len);
759 bfin_write_MDMA_S0_X_MODIFY(0);
760 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
762 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
763 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
765 blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
767 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
769 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
771 bfin_write_MDMA_S0_CONFIG(0);
772 bfin_write_MDMA_D0_CONFIG(0);
773 local_irq_restore(flags);
776 EXPORT_SYMBOL(dma_insl);