2 * File: arch/blackfin/kernel/bfin_dma_5xx.c
7 * Description: This file contains the simple DMA Implementation for Blackfin
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/interrupt.h>
34 #include <linux/kernel.h>
35 #include <linux/param.h>
37 #include <asm/blackfin.h>
39 #include <asm/cacheflush.h>
41 /* Remove unused code not exported by symbol or internally called */
42 #define REMOVE_DEAD_CODE
44 /**************************************************************************
46 ***************************************************************************/
48 static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
50 /*------------------------------------------------------------------------------
51 * Set the Buffer Clear bit in the Configuration register of specific DMA
52 * channel. This will stop the descriptor based DMA operation.
53 *-----------------------------------------------------------------------------*/
54 static void clear_dma_buffer(unsigned int channel)
56 dma_ch[channel].regs->cfg |= RESTART;
58 dma_ch[channel].regs->cfg &= ~RESTART;
62 static int __init blackfin_dma_init(void)
66 printk(KERN_INFO "Blackfin DMA Controller\n");
68 for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
69 dma_ch[i].chan_status = DMA_CHANNEL_FREE;
70 dma_ch[i].regs = base_addr[i];
71 mutex_init(&(dma_ch[i].dmalock));
73 /* Mark MEMDMA Channel 0 as requested since we're using it internally */
74 dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED;
75 dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED;
77 #if defined(CONFIG_DEB_DMA_URGENT)
78 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
79 | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
84 arch_initcall(blackfin_dma_init);
86 /*------------------------------------------------------------------------------
87 * Request the specific DMA channel from the system.
88 *-----------------------------------------------------------------------------*/
89 int request_dma(unsigned int channel, char *device_id)
92 pr_debug("request_dma() : BEGIN \n");
93 mutex_lock(&(dma_ch[channel].dmalock));
95 if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
96 || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
97 mutex_unlock(&(dma_ch[channel].dmalock));
98 pr_debug("DMA CHANNEL IN USE \n");
101 dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
102 pr_debug("DMA CHANNEL IS ALLOCATED \n");
105 mutex_unlock(&(dma_ch[channel].dmalock));
107 dma_ch[channel].device_id = device_id;
108 dma_ch[channel].irq_callback = NULL;
110 /* This is to be enabled by putting a restriction -
111 * you have to request DMA, before doing any operations on
114 pr_debug("request_dma() : END \n");
117 EXPORT_SYMBOL(request_dma);
119 int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
123 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
124 && channel < MAX_BLACKFIN_DMA_CHANNEL));
126 if (callback != NULL) {
128 ret_irq = channel2irq(channel);
130 dma_ch[channel].data = data;
133 request_irq(ret_irq, (void *)callback, IRQF_DISABLED,
134 dma_ch[channel].device_id, data);
137 "Request irq in DMA engine failed.\n");
140 dma_ch[channel].irq_callback = callback;
144 EXPORT_SYMBOL(set_dma_callback);
146 void free_dma(unsigned int channel)
150 pr_debug("freedma() : BEGIN \n");
151 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
152 && channel < MAX_BLACKFIN_DMA_CHANNEL));
155 disable_dma(channel);
156 clear_dma_buffer(channel);
158 if (dma_ch[channel].irq_callback != NULL) {
159 ret_irq = channel2irq(channel);
160 free_irq(ret_irq, dma_ch[channel].data);
163 /* Clear the DMA Variable in the Channel */
164 mutex_lock(&(dma_ch[channel].dmalock));
165 dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
166 mutex_unlock(&(dma_ch[channel].dmalock));
168 pr_debug("freedma() : END \n");
170 EXPORT_SYMBOL(free_dma);
172 void dma_enable_irq(unsigned int channel)
176 pr_debug("dma_enable_irq() : BEGIN \n");
177 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
178 && channel < MAX_BLACKFIN_DMA_CHANNEL));
180 ret_irq = channel2irq(channel);
183 EXPORT_SYMBOL(dma_enable_irq);
185 void dma_disable_irq(unsigned int channel)
189 pr_debug("dma_disable_irq() : BEGIN \n");
190 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
191 && channel < MAX_BLACKFIN_DMA_CHANNEL));
193 ret_irq = channel2irq(channel);
194 disable_irq(ret_irq);
196 EXPORT_SYMBOL(dma_disable_irq);
198 int dma_channel_active(unsigned int channel)
200 if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) {
206 EXPORT_SYMBOL(dma_channel_active);
208 /*------------------------------------------------------------------------------
209 * stop the specific DMA channel.
210 *-----------------------------------------------------------------------------*/
211 void disable_dma(unsigned int channel)
213 pr_debug("stop_dma() : BEGIN \n");
215 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
216 && channel < MAX_BLACKFIN_DMA_CHANNEL));
218 dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
220 dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
221 /* Needs to be enabled Later */
222 pr_debug("stop_dma() : END \n");
225 EXPORT_SYMBOL(disable_dma);
227 void enable_dma(unsigned int channel)
229 pr_debug("enable_dma() : BEGIN \n");
231 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
232 && channel < MAX_BLACKFIN_DMA_CHANNEL));
234 dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
235 dma_ch[channel].regs->curr_x_count = 0;
236 dma_ch[channel].regs->curr_y_count = 0;
238 dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
240 pr_debug("enable_dma() : END \n");
243 EXPORT_SYMBOL(enable_dma);
245 /*------------------------------------------------------------------------------
246 * Set the Start Address register for the specific DMA channel
247 * This function can be used for register based DMA,
248 * to setup the start address
249 * addr: Starting address of the DMA Data to be transferred.
250 *-----------------------------------------------------------------------------*/
251 void set_dma_start_addr(unsigned int channel, unsigned long addr)
253 pr_debug("set_dma_start_addr() : BEGIN \n");
255 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
256 && channel < MAX_BLACKFIN_DMA_CHANNEL));
258 dma_ch[channel].regs->start_addr = addr;
260 pr_debug("set_dma_start_addr() : END\n");
262 EXPORT_SYMBOL(set_dma_start_addr);
264 void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
266 pr_debug("set_dma_next_desc_addr() : BEGIN \n");
268 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
269 && channel < MAX_BLACKFIN_DMA_CHANNEL));
271 dma_ch[channel].regs->next_desc_ptr = addr;
273 pr_debug("set_dma_start_addr() : END\n");
275 EXPORT_SYMBOL(set_dma_next_desc_addr);
277 void set_dma_x_count(unsigned int channel, unsigned short x_count)
279 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
280 && channel < MAX_BLACKFIN_DMA_CHANNEL));
282 dma_ch[channel].regs->x_count = x_count;
285 EXPORT_SYMBOL(set_dma_x_count);
287 void set_dma_y_count(unsigned int channel, unsigned short y_count)
289 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
290 && channel < MAX_BLACKFIN_DMA_CHANNEL));
292 dma_ch[channel].regs->y_count = y_count;
295 EXPORT_SYMBOL(set_dma_y_count);
297 void set_dma_x_modify(unsigned int channel, short x_modify)
299 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
300 && channel < MAX_BLACKFIN_DMA_CHANNEL));
302 dma_ch[channel].regs->x_modify = x_modify;
305 EXPORT_SYMBOL(set_dma_x_modify);
307 void set_dma_y_modify(unsigned int channel, short y_modify)
309 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
310 && channel < MAX_BLACKFIN_DMA_CHANNEL));
312 dma_ch[channel].regs->y_modify = y_modify;
315 EXPORT_SYMBOL(set_dma_y_modify);
317 void set_dma_config(unsigned int channel, unsigned short config)
319 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
320 && channel < MAX_BLACKFIN_DMA_CHANNEL));
322 dma_ch[channel].regs->cfg = config;
325 EXPORT_SYMBOL(set_dma_config);
328 set_bfin_dma_config(char direction, char flow_mode,
329 char intr_mode, char dma_mode, char width)
331 unsigned short config;
334 ((direction << 1) | (width << 2) | (dma_mode << 4) |
335 (intr_mode << 6) | (flow_mode << 12) | RESTART);
338 EXPORT_SYMBOL(set_bfin_dma_config);
340 void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
342 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
343 && channel < MAX_BLACKFIN_DMA_CHANNEL));
345 dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8);
347 dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg;
351 EXPORT_SYMBOL(set_dma_sg);
353 void set_dma_curr_addr(unsigned int channel, unsigned long addr)
355 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
356 && channel < MAX_BLACKFIN_DMA_CHANNEL));
358 dma_ch[channel].regs->curr_addr_ptr = addr;
361 EXPORT_SYMBOL(set_dma_curr_addr);
363 /*------------------------------------------------------------------------------
364 * Get the DMA status of a specific DMA channel from the system.
365 *-----------------------------------------------------------------------------*/
366 unsigned short get_dma_curr_irqstat(unsigned int channel)
368 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
369 && channel < MAX_BLACKFIN_DMA_CHANNEL));
371 return dma_ch[channel].regs->irq_status;
373 EXPORT_SYMBOL(get_dma_curr_irqstat);
375 /*------------------------------------------------------------------------------
376 * Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt.
377 *-----------------------------------------------------------------------------*/
378 void clear_dma_irqstat(unsigned int channel)
380 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
381 && channel < MAX_BLACKFIN_DMA_CHANNEL));
382 dma_ch[channel].regs->irq_status |= 3;
384 EXPORT_SYMBOL(clear_dma_irqstat);
386 /*------------------------------------------------------------------------------
387 * Get current DMA xcount of a specific DMA channel from the system.
388 *-----------------------------------------------------------------------------*/
389 unsigned short get_dma_curr_xcount(unsigned int channel)
391 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
392 && channel < MAX_BLACKFIN_DMA_CHANNEL));
394 return dma_ch[channel].regs->curr_x_count;
396 EXPORT_SYMBOL(get_dma_curr_xcount);
398 /*------------------------------------------------------------------------------
399 * Get current DMA ycount of a specific DMA channel from the system.
400 *-----------------------------------------------------------------------------*/
401 unsigned short get_dma_curr_ycount(unsigned int channel)
403 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
404 && channel < MAX_BLACKFIN_DMA_CHANNEL));
406 return dma_ch[channel].regs->curr_y_count;
408 EXPORT_SYMBOL(get_dma_curr_ycount);
410 static void *__dma_memcpy(void *dest, const void *src, size_t size)
412 int direction; /* 1 - address decrease, 0 - address increase */
413 int flag_align; /* 1 - address aligned, 0 - address unaligned */
414 int flag_2D; /* 1 - 2D DMA needed, 0 - 1D DMA needed */
420 local_irq_save(flags);
422 if ((unsigned long)src < memory_end)
423 blackfin_dcache_flush_range((unsigned int)src,
424 (unsigned int)(src + size));
426 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
428 if ((unsigned long)src < (unsigned long)dest)
433 if ((((unsigned long)dest % 2) == 0) && (((unsigned long)src % 2) == 0)
434 && ((size % 2) == 0))
439 if (size > 0x10000) /* size > 64K */
444 /* Setup destination and source start address */
447 bfin_write_MDMA_D0_START_ADDR(dest + size - 2);
448 bfin_write_MDMA_S0_START_ADDR(src + size - 2);
450 bfin_write_MDMA_D0_START_ADDR(dest + size - 1);
451 bfin_write_MDMA_S0_START_ADDR(src + size - 1);
454 bfin_write_MDMA_D0_START_ADDR(dest);
455 bfin_write_MDMA_S0_START_ADDR(src);
458 /* Setup destination and source xcount */
461 bfin_write_MDMA_D0_X_COUNT(1024 / 2);
462 bfin_write_MDMA_S0_X_COUNT(1024 / 2);
464 bfin_write_MDMA_D0_X_COUNT(1024);
465 bfin_write_MDMA_S0_X_COUNT(1024);
467 bfin_write_MDMA_D0_Y_COUNT(size >> 10);
468 bfin_write_MDMA_S0_Y_COUNT(size >> 10);
471 bfin_write_MDMA_D0_X_COUNT(size / 2);
472 bfin_write_MDMA_S0_X_COUNT(size / 2);
474 bfin_write_MDMA_D0_X_COUNT(size);
475 bfin_write_MDMA_S0_X_COUNT(size);
479 /* Setup destination and source xmodify and ymodify */
482 bfin_write_MDMA_D0_X_MODIFY(-2);
483 bfin_write_MDMA_S0_X_MODIFY(-2);
485 bfin_write_MDMA_D0_Y_MODIFY(-2);
486 bfin_write_MDMA_S0_Y_MODIFY(-2);
489 bfin_write_MDMA_D0_X_MODIFY(-1);
490 bfin_write_MDMA_S0_X_MODIFY(-1);
492 bfin_write_MDMA_D0_Y_MODIFY(-1);
493 bfin_write_MDMA_S0_Y_MODIFY(-1);
498 bfin_write_MDMA_D0_X_MODIFY(2);
499 bfin_write_MDMA_S0_X_MODIFY(2);
501 bfin_write_MDMA_D0_Y_MODIFY(2);
502 bfin_write_MDMA_S0_Y_MODIFY(2);
505 bfin_write_MDMA_D0_X_MODIFY(1);
506 bfin_write_MDMA_S0_X_MODIFY(1);
508 bfin_write_MDMA_D0_Y_MODIFY(1);
509 bfin_write_MDMA_S0_Y_MODIFY(1);
514 /* Enable source DMA */
517 bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16);
518 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16);
520 bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D);
521 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D);
525 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
526 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
528 bfin_write_MDMA_S0_CONFIG(DMAEN);
529 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN);
533 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
536 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() |
537 (DMA_DONE | DMA_ERR));
539 bfin_write_MDMA_S0_CONFIG(0);
540 bfin_write_MDMA_D0_CONFIG(0);
542 if ((unsigned long)dest < memory_end)
543 blackfin_dcache_invalidate_range((unsigned int)dest,
544 (unsigned int)(dest + size));
545 local_irq_restore(flags);
550 void *dma_memcpy(void *dest, const void *src, size_t size)
556 bulk = (size >> 16) << 16;
559 __dma_memcpy(dest, src, bulk);
560 addr = __dma_memcpy(dest+bulk, src+bulk, rest);
563 EXPORT_SYMBOL(dma_memcpy);
565 void *safe_dma_memcpy(void *dest, const void *src, size_t size)
568 addr = dma_memcpy(dest, src, size);
571 EXPORT_SYMBOL(safe_dma_memcpy);
573 void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
577 local_irq_save(flags);
579 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
581 bfin_write_MDMA_D0_START_ADDR(addr);
582 bfin_write_MDMA_D0_X_COUNT(len);
583 bfin_write_MDMA_D0_X_MODIFY(0);
584 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
586 bfin_write_MDMA_S0_START_ADDR(buf);
587 bfin_write_MDMA_S0_X_COUNT(len);
588 bfin_write_MDMA_S0_X_MODIFY(1);
589 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
591 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
592 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
594 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
596 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
598 bfin_write_MDMA_S0_CONFIG(0);
599 bfin_write_MDMA_D0_CONFIG(0);
600 local_irq_restore(flags);
603 EXPORT_SYMBOL(dma_outsb);
606 void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
610 local_irq_save(flags);
611 bfin_write_MDMA_D0_START_ADDR(buf);
612 bfin_write_MDMA_D0_X_COUNT(len);
613 bfin_write_MDMA_D0_X_MODIFY(1);
614 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
616 bfin_write_MDMA_S0_START_ADDR(addr);
617 bfin_write_MDMA_S0_X_COUNT(len);
618 bfin_write_MDMA_S0_X_MODIFY(0);
619 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
621 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
622 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
624 blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
626 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
628 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
630 bfin_write_MDMA_S0_CONFIG(0);
631 bfin_write_MDMA_D0_CONFIG(0);
632 local_irq_restore(flags);
635 EXPORT_SYMBOL(dma_insb);
637 void dma_outsw(void __iomem *addr, const void *buf, unsigned short len)
641 local_irq_save(flags);
643 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
645 bfin_write_MDMA_D0_START_ADDR(addr);
646 bfin_write_MDMA_D0_X_COUNT(len);
647 bfin_write_MDMA_D0_X_MODIFY(0);
648 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
650 bfin_write_MDMA_S0_START_ADDR(buf);
651 bfin_write_MDMA_S0_X_COUNT(len);
652 bfin_write_MDMA_S0_X_MODIFY(2);
653 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
655 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
656 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
658 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
660 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
662 bfin_write_MDMA_S0_CONFIG(0);
663 bfin_write_MDMA_D0_CONFIG(0);
664 local_irq_restore(flags);
667 EXPORT_SYMBOL(dma_outsw);
669 void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
673 local_irq_save(flags);
675 bfin_write_MDMA_D0_START_ADDR(buf);
676 bfin_write_MDMA_D0_X_COUNT(len);
677 bfin_write_MDMA_D0_X_MODIFY(2);
678 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
680 bfin_write_MDMA_S0_START_ADDR(addr);
681 bfin_write_MDMA_S0_X_COUNT(len);
682 bfin_write_MDMA_S0_X_MODIFY(0);
683 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
685 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
686 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
688 blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
690 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
692 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
694 bfin_write_MDMA_S0_CONFIG(0);
695 bfin_write_MDMA_D0_CONFIG(0);
696 local_irq_restore(flags);
699 EXPORT_SYMBOL(dma_insw);
701 void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
705 local_irq_save(flags);
707 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
709 bfin_write_MDMA_D0_START_ADDR(addr);
710 bfin_write_MDMA_D0_X_COUNT(len);
711 bfin_write_MDMA_D0_X_MODIFY(0);
712 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
714 bfin_write_MDMA_S0_START_ADDR(buf);
715 bfin_write_MDMA_S0_X_COUNT(len);
716 bfin_write_MDMA_S0_X_MODIFY(4);
717 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
719 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
720 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
722 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
724 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
726 bfin_write_MDMA_S0_CONFIG(0);
727 bfin_write_MDMA_D0_CONFIG(0);
728 local_irq_restore(flags);
731 EXPORT_SYMBOL(dma_outsl);
733 void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
737 local_irq_save(flags);
739 bfin_write_MDMA_D0_START_ADDR(buf);
740 bfin_write_MDMA_D0_X_COUNT(len);
741 bfin_write_MDMA_D0_X_MODIFY(4);
742 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
744 bfin_write_MDMA_S0_START_ADDR(addr);
745 bfin_write_MDMA_S0_X_COUNT(len);
746 bfin_write_MDMA_S0_X_MODIFY(0);
747 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
749 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
750 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
752 blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
754 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
756 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
758 bfin_write_MDMA_S0_CONFIG(0);
759 bfin_write_MDMA_D0_CONFIG(0);
760 local_irq_restore(flags);
763 EXPORT_SYMBOL(dma_insl);