2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
33 #include <asm/atomic.h>
36 #include <asm/mpspec.h>
38 #include <asm/arch_hooks.h>
40 #include <asm/i8253.h>
43 #include <mach_apic.h>
44 #include <mach_apicdef.h>
52 #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
53 # error SPURIOUS_APIC_VECTOR definition error
57 * Knob to control our willingness to enable the local APIC.
59 * -1=force-disable, +1=force-enable
61 static int enable_local_apic __initdata = 0;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled;
69 * Debug level, exported for io_apic.c
73 static unsigned int calibration_result;
75 static int lapic_next_event(unsigned long delta,
76 struct clock_event_device *evt);
77 static void lapic_timer_setup(enum clock_event_mode mode,
78 struct clock_event_device *evt);
79 static void lapic_timer_broadcast(cpumask_t mask);
80 static void apic_pm_activate(void);
83 * The local apic timer can be used for any function which is CPU local.
85 static struct clock_event_device lapic_clockevent = {
87 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
88 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
90 .set_mode = lapic_timer_setup,
91 .set_next_event = lapic_next_event,
92 .broadcast = lapic_timer_broadcast,
96 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase;
102 * Get the LAPIC version
104 static inline int lapic_get_version(void)
106 return GET_APIC_VERSION(apic_read(APIC_LVR));
110 * Check, if the APIC is integrated or a seperate chip
112 static inline int lapic_is_integrated(void)
114 return APIC_INTEGRATED(lapic_get_version());
118 * Check, whether this is a modern or a first generation APIC
120 static int modern_apic(void)
122 /* AMD systems use old APIC versions, so check the CPU */
123 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
124 boot_cpu_data.x86 >= 0xf)
126 return lapic_get_version() >= 0x14;
130 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
132 void enable_NMI_through_LVT0 (void * dummy)
134 unsigned int v = APIC_DM_NMI;
136 /* Level triggered for 82489DX */
137 if (!lapic_is_integrated())
138 v |= APIC_LVT_LEVEL_TRIGGER;
139 apic_write_around(APIC_LVT0, v);
143 * get_physical_broadcast - Get number of physical broadcast IDs
145 int get_physical_broadcast(void)
147 return modern_apic() ? 0xff : 0xf;
151 * lapic_get_maxlvt - get the maximum number of local vector table entries
153 int lapic_get_maxlvt(void)
155 unsigned int v = apic_read(APIC_LVR);
157 /* 82489DXs do not report # of LVT entries. */
158 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
165 /* Clock divisor is set to 16 */
166 #define APIC_DIVISOR 16
169 * This function sets up the local APIC timer, with a timeout of
170 * 'clocks' APIC bus clock. During calibration we actually call
171 * this function twice on the boot CPU, once with a bogus timeout
172 * value, second time for real. The other (noncalibrating) CPUs
173 * call this function only once, with the real, calibrated value.
175 * We do reads before writes even if unnecessary, to get around the
176 * P5 APIC double write bug.
178 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
180 unsigned int lvtt_value, tmp_value;
182 lvtt_value = LOCAL_TIMER_VECTOR;
184 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
185 if (!lapic_is_integrated())
186 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
189 lvtt_value |= APIC_LVT_MASKED;
191 apic_write_around(APIC_LVTT, lvtt_value);
196 tmp_value = apic_read(APIC_TDCR);
197 apic_write_around(APIC_TDCR, (tmp_value
198 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
202 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
206 * Program the next event, relative to now
208 static int lapic_next_event(unsigned long delta,
209 struct clock_event_device *evt)
211 apic_write_around(APIC_TMICT, delta);
216 * Setup the lapic timer in periodic or oneshot mode
218 static void lapic_timer_setup(enum clock_event_mode mode,
219 struct clock_event_device *evt)
224 /* Lapic used for broadcast ? */
225 if (!local_apic_timer_verify_ok)
228 local_irq_save(flags);
231 case CLOCK_EVT_MODE_PERIODIC:
232 case CLOCK_EVT_MODE_ONESHOT:
233 __setup_APIC_LVTT(calibration_result,
234 mode != CLOCK_EVT_MODE_PERIODIC, 1);
236 case CLOCK_EVT_MODE_UNUSED:
237 case CLOCK_EVT_MODE_SHUTDOWN:
238 v = apic_read(APIC_LVTT);
239 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
240 apic_write_around(APIC_LVTT, v);
244 local_irq_restore(flags);
248 * Local APIC timer broadcast function
250 static void lapic_timer_broadcast(cpumask_t mask)
253 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
258 * Setup the local APIC timer for this CPU. Copy the initilized values
259 * of the boot CPU and register the clock event in the framework.
261 static void __devinit setup_APIC_timer(void)
263 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
265 memcpy(levt, &lapic_clockevent, sizeof(*levt));
266 levt->cpumask = cpumask_of_cpu(smp_processor_id());
268 clockevents_register_device(levt);
272 * Detect systems with known broken BIOS implementations
274 static int __init lapic_check_broken_bios(struct dmi_system_id *d)
276 printk(KERN_NOTICE "%s detected: disabling lapic timer.\n",
278 local_apic_timer_disabled = 1;
282 static struct dmi_system_id __initdata broken_bios_dmi_table[] = {
285 * BIOS exports only C1 state, but uses deeper power
286 * modes behind the kernels back.
288 .callback = lapic_check_broken_bios,
289 .ident = "HP nx6325",
291 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
298 * In this functions we calibrate APIC bus clocks to the external timer.
300 * We want to do the calibration only once since we want to have local timer
301 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
304 * This was previously done by reading the PIT/HPET and waiting for a wrap
305 * around to find out, that a tick has elapsed. I have a box, where the PIT
306 * readout is broken, so it never gets out of the wait loop again. This was
307 * also reported by others.
309 * Monitoring the jiffies value is inaccurate and the clockevents
310 * infrastructure allows us to do a simple substitution of the interrupt
313 * The calibration routine also uses the pm_timer when possible, as the PIT
314 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
315 * back to normal later in the boot process).
318 #define LAPIC_CAL_LOOPS (HZ/10)
320 static __initdata volatile int lapic_cal_loops = -1;
321 static __initdata long lapic_cal_t1, lapic_cal_t2;
322 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
323 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
324 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
327 * Temporary interrupt handler.
329 static void __init lapic_cal_handler(struct clock_event_device *dev)
331 unsigned long long tsc = 0;
332 long tapic = apic_read(APIC_TMCCT);
333 unsigned long pm = acpi_pm_read_early();
338 switch (lapic_cal_loops++) {
340 lapic_cal_t1 = tapic;
341 lapic_cal_tsc1 = tsc;
343 lapic_cal_j1 = jiffies;
346 case LAPIC_CAL_LOOPS:
347 lapic_cal_t2 = tapic;
348 lapic_cal_tsc2 = tsc;
349 if (pm < lapic_cal_pm1)
350 pm += ACPI_PM_OVRRUN;
352 lapic_cal_j2 = jiffies;
358 * Setup the boot APIC
360 * Calibrate and verify the result.
362 void __init setup_boot_APIC_clock(void)
364 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
365 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
366 const long pm_thresh = pm_100ms/100;
367 void (*real_handler)(struct clock_event_device *dev);
368 unsigned long deltaj;
370 int pm_referenced = 0;
372 /* Detect know broken systems */
373 dmi_check_system(broken_bios_dmi_table);
376 * The local apic timer can be disabled via the kernel
377 * commandline or from the dmi quirk above. Register the lapic
378 * timer as a dummy clock event source on SMP systems, so the
379 * broadcast mechanism is used. On UP systems simply ignore it.
381 if (local_apic_timer_disabled) {
382 /* No broadcast on UP ! */
383 if (num_possible_cpus() > 1)
388 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
389 "calibrating APIC timer ...\n");
393 /* Replace the global interrupt handler */
394 real_handler = global_clock_event->event_handler;
395 global_clock_event->event_handler = lapic_cal_handler;
398 * Setup the APIC counter to 1e9. There is no way the lapic
399 * can underflow in the 100ms detection time frame
401 __setup_APIC_LVTT(1000000000, 0, 0);
403 /* Let the interrupts run */
406 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
411 /* Restore the real event handler */
412 global_clock_event->event_handler = real_handler;
414 /* Build delta t1-t2 as apic timer counts down */
415 delta = lapic_cal_t1 - lapic_cal_t2;
416 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
418 /* Check, if the PM timer is available */
419 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
420 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
426 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
428 if (deltapm > (pm_100ms - pm_thresh) &&
429 deltapm < (pm_100ms + pm_thresh)) {
430 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
432 res = (((u64) deltapm) * mult) >> 22;
433 do_div(res, 1000000);
434 printk(KERN_WARNING "APIC calibration not consistent "
435 "with PM Timer: %ldms instead of 100ms\n",
437 /* Correct the lapic counter value */
438 res = (((u64) delta ) * pm_100ms);
439 do_div(res, deltapm);
440 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
441 "%lu (%ld)\n", (unsigned long) res, delta);
447 /* Calculate the scaled math multiplication factor */
448 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32);
449 lapic_clockevent.max_delta_ns =
450 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
451 lapic_clockevent.min_delta_ns =
452 clockevent_delta2ns(0xF, &lapic_clockevent);
454 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
456 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
457 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
458 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
462 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
463 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
465 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
466 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
469 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
471 calibration_result / (1000000 / HZ),
472 calibration_result % (1000000 / HZ));
474 local_apic_timer_verify_ok = 1;
476 /* We trust the pm timer based calibration */
477 if (!pm_referenced) {
478 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
481 * Setup the apic timer manually
483 levt->event_handler = lapic_cal_handler;
484 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
485 lapic_cal_loops = -1;
487 /* Let the interrupts run */
490 while(lapic_cal_loops <= LAPIC_CAL_LOOPS)
495 /* Stop the lapic timer */
496 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
501 deltaj = lapic_cal_j2 - lapic_cal_j1;
502 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
504 /* Check, if the jiffies result is consistent */
505 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
506 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
508 local_apic_timer_verify_ok = 0;
511 if (!local_apic_timer_verify_ok) {
513 "APIC timer disabled due to verification failure.\n");
514 /* No broadcast on UP ! */
515 if (num_possible_cpus() == 1)
519 * If nmi_watchdog is set to IO_APIC, we need the
520 * PIT/HPET going. Otherwise register lapic as a dummy
523 if (nmi_watchdog != NMI_IO_APIC)
524 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
527 /* Setup the lapic or request the broadcast */
531 void __devinit setup_secondary_APIC_clock(void)
537 * The guts of the apic timer interrupt
539 static void local_apic_timer_interrupt(void)
541 int cpu = smp_processor_id();
542 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
545 * Normally we should not be here till LAPIC has been initialized but
546 * in some cases like kdump, its possible that there is a pending LAPIC
547 * timer interrupt from previous kernel's context and is delivered in
548 * new kernel the moment interrupts are enabled.
550 * Interrupts are enabled early and LAPIC is setup much later, hence
551 * its possible that when we get here evt->event_handler is NULL.
552 * Check for event_handler being NULL and discard the interrupt as
555 if (!evt->event_handler) {
557 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
559 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
563 per_cpu(irq_stat, cpu).apic_timer_irqs++;
565 evt->event_handler(evt);
569 * Local APIC timer interrupt. This is the most natural way for doing
570 * local interrupts, but local timer interrupts can be emulated by
571 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
573 * [ if a single-CPU system runs an SMP kernel then we call the local
574 * interrupt as well. Thus we cannot inline the local irq ... ]
577 void fastcall smp_apic_timer_interrupt(struct pt_regs *regs)
579 struct pt_regs *old_regs = set_irq_regs(regs);
582 * NOTE! We'd better ACK the irq immediately,
583 * because timer handling can be slow.
587 * update_process_times() expects us to have done irq_enter().
588 * Besides, if we don't timer interrupts ignore the global
589 * interrupt lock, which is the WrongThing (tm) to do.
592 local_apic_timer_interrupt();
595 set_irq_regs(old_regs);
598 int setup_profiling_timer(unsigned int multiplier)
604 * Local APIC start and shutdown
608 * clear_local_APIC - shutdown the local APIC
610 * This is called, when a CPU is disabled and before rebooting, so the state of
611 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
612 * leftovers during boot.
614 void clear_local_APIC(void)
616 int maxlvt = lapic_get_maxlvt();
620 * Masking an LVT entry can trigger a local APIC error
621 * if the vector is zero. Mask LVTERR first to prevent this.
624 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
625 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
628 * Careful: we have to set masks only first to deassert
629 * any level-triggered sources.
631 v = apic_read(APIC_LVTT);
632 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
633 v = apic_read(APIC_LVT0);
634 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
635 v = apic_read(APIC_LVT1);
636 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
638 v = apic_read(APIC_LVTPC);
639 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
642 /* lets not touch this if we didn't frob it */
643 #ifdef CONFIG_X86_MCE_P4THERMAL
645 v = apic_read(APIC_LVTTHMR);
646 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
650 * Clean APIC state for other OSs:
652 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
653 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
654 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
656 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
658 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
660 #ifdef CONFIG_X86_MCE_P4THERMAL
662 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
664 /* Integrated APIC (!82489DX) ? */
665 if (lapic_is_integrated()) {
667 /* Clear ESR due to Pentium errata 3AP and 11AP */
668 apic_write(APIC_ESR, 0);
674 * disable_local_APIC - clear and disable the local APIC
676 void disable_local_APIC(void)
683 * Disable APIC (implies clearing of registers
686 value = apic_read(APIC_SPIV);
687 value &= ~APIC_SPIV_APIC_ENABLED;
688 apic_write_around(APIC_SPIV, value);
691 * When LAPIC was disabled by the BIOS and enabled by the kernel,
692 * restore the disabled state.
694 if (enabled_via_apicbase) {
697 rdmsr(MSR_IA32_APICBASE, l, h);
698 l &= ~MSR_IA32_APICBASE_ENABLE;
699 wrmsr(MSR_IA32_APICBASE, l, h);
704 * If Linux enabled the LAPIC against the BIOS default disable it down before
705 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
706 * not power-off. Additionally clear all LVT entries before disable_local_APIC
707 * for the case where Linux didn't enable the LAPIC.
709 void lapic_shutdown(void)
716 local_irq_save(flags);
719 if (enabled_via_apicbase)
720 disable_local_APIC();
722 local_irq_restore(flags);
726 * This is to verify that we're looking at a real local APIC.
727 * Check these against your board if the CPUs aren't getting
728 * started for no apparent reason.
730 int __init verify_local_APIC(void)
732 unsigned int reg0, reg1;
735 * The version register is read-only in a real APIC.
737 reg0 = apic_read(APIC_LVR);
738 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
739 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
740 reg1 = apic_read(APIC_LVR);
741 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
744 * The two version reads above should print the same
745 * numbers. If the second one is different, then we
746 * poke at a non-APIC.
752 * Check if the version looks reasonably.
754 reg1 = GET_APIC_VERSION(reg0);
755 if (reg1 == 0x00 || reg1 == 0xff)
757 reg1 = lapic_get_maxlvt();
758 if (reg1 < 0x02 || reg1 == 0xff)
762 * The ID register is read/write in a real APIC.
764 reg0 = apic_read(APIC_ID);
765 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
768 * The next two are just to see if we have sane values.
769 * They're only really relevant if we're in Virtual Wire
770 * compatibility mode, but most boxes are anymore.
772 reg0 = apic_read(APIC_LVT0);
773 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
774 reg1 = apic_read(APIC_LVT1);
775 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
781 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
783 void __init sync_Arb_IDs(void)
786 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
794 apic_wait_icr_idle();
796 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
797 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
802 * An initial setup of the virtual wire mode.
804 void __init init_bsp_APIC(void)
809 * Don't do the setup now if we have a SMP BIOS as the
810 * through-I/O-APIC virtual wire mode might be active.
812 if (smp_found_config || !cpu_has_apic)
816 * Do not trust the local APIC being empty at bootup.
823 value = apic_read(APIC_SPIV);
824 value &= ~APIC_VECTOR_MASK;
825 value |= APIC_SPIV_APIC_ENABLED;
827 /* This bit is reserved on P4/Xeon and should be cleared */
828 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
829 (boot_cpu_data.x86 == 15))
830 value &= ~APIC_SPIV_FOCUS_DISABLED;
832 value |= APIC_SPIV_FOCUS_DISABLED;
833 value |= SPURIOUS_APIC_VECTOR;
834 apic_write_around(APIC_SPIV, value);
837 * Set up the virtual wire mode.
839 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
841 if (!lapic_is_integrated()) /* 82489DX */
842 value |= APIC_LVT_LEVEL_TRIGGER;
843 apic_write_around(APIC_LVT1, value);
847 * setup_local_APIC - setup the local APIC
849 void __devinit setup_local_APIC(void)
851 unsigned long oldvalue, value, maxlvt, integrated;
854 /* Pound the ESR really hard over the head with a big hammer - mbligh */
856 apic_write(APIC_ESR, 0);
857 apic_write(APIC_ESR, 0);
858 apic_write(APIC_ESR, 0);
859 apic_write(APIC_ESR, 0);
862 integrated = lapic_is_integrated();
865 * Double-check whether this APIC is really registered.
867 if (!apic_id_registered())
871 * Intel recommends to set DFR, LDR and TPR before enabling
872 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
873 * document number 292116). So here it goes...
878 * Set Task Priority to 'accept all'. We never change this
881 value = apic_read(APIC_TASKPRI);
882 value &= ~APIC_TPRI_MASK;
883 apic_write_around(APIC_TASKPRI, value);
886 * After a crash, we no longer service the interrupts and a pending
887 * interrupt from previous kernel might still have ISR bit set.
889 * Most probably by now CPU has serviced that pending interrupt and
890 * it might not have done the ack_APIC_irq() because it thought,
891 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
892 * does not clear the ISR bit and cpu thinks it has already serivced
893 * the interrupt. Hence a vector might get locked. It was noticed
894 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
896 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
897 value = apic_read(APIC_ISR + i*0x10);
898 for (j = 31; j >= 0; j--) {
905 * Now that we are all set up, enable the APIC
907 value = apic_read(APIC_SPIV);
908 value &= ~APIC_VECTOR_MASK;
912 value |= APIC_SPIV_APIC_ENABLED;
915 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
916 * certain networking cards. If high frequency interrupts are
917 * happening on a particular IOAPIC pin, plus the IOAPIC routing
918 * entry is masked/unmasked at a high rate as well then sooner or
919 * later IOAPIC line gets 'stuck', no more interrupts are received
920 * from the device. If focus CPU is disabled then the hang goes
923 * [ This bug can be reproduced easily with a level-triggered
924 * PCI Ne2000 networking cards and PII/PIII processors, dual
928 * Actually disabling the focus CPU check just makes the hang less
929 * frequent as it makes the interrupt distributon model be more
930 * like LRU than MRU (the short-term load is more even across CPUs).
931 * See also the comment in end_level_ioapic_irq(). --macro
934 /* Enable focus processor (bit==0) */
935 value &= ~APIC_SPIV_FOCUS_DISABLED;
938 * Set spurious IRQ vector
940 value |= SPURIOUS_APIC_VECTOR;
941 apic_write_around(APIC_SPIV, value);
946 * set up through-local-APIC on the BP's LINT0. This is not
947 * strictly necessery in pure symmetric-IO mode, but sometimes
948 * we delegate interrupts to the 8259A.
951 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
953 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
954 if (!smp_processor_id() && (pic_mode || !value)) {
955 value = APIC_DM_EXTINT;
956 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
959 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
960 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
963 apic_write_around(APIC_LVT0, value);
966 * only the BP should see the LINT1 NMI signal, obviously.
968 if (!smp_processor_id())
971 value = APIC_DM_NMI | APIC_LVT_MASKED;
972 if (!integrated) /* 82489DX */
973 value |= APIC_LVT_LEVEL_TRIGGER;
974 apic_write_around(APIC_LVT1, value);
976 if (integrated && !esr_disable) { /* !82489DX */
977 maxlvt = lapic_get_maxlvt();
978 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
979 apic_write(APIC_ESR, 0);
980 oldvalue = apic_read(APIC_ESR);
982 /* enables sending errors */
983 value = ERROR_APIC_VECTOR;
984 apic_write_around(APIC_LVTERR, value);
986 * spec says clear errors after enabling vector.
989 apic_write(APIC_ESR, 0);
990 value = apic_read(APIC_ESR);
991 if (value != oldvalue)
992 apic_printk(APIC_VERBOSE, "ESR value before enabling "
993 "vector: 0x%08lx after: 0x%08lx\n",
998 * Something untraceble is creating bad interrupts on
999 * secondary quads ... for the moment, just leave the
1000 * ESR disabled - we can't do anything useful with the
1001 * errors anyway - mbligh
1003 printk(KERN_INFO "Leaving ESR disabled.\n");
1005 printk(KERN_INFO "No ESR for 82489DX.\n");
1008 /* Disable the local apic timer */
1009 value = apic_read(APIC_LVTT);
1010 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1011 apic_write_around(APIC_LVTT, value);
1013 setup_apic_nmi_watchdog(NULL);
1018 * Detect and initialize APIC
1020 static int __init detect_init_APIC (void)
1024 /* Disabled by kernel option? */
1025 if (enable_local_apic < 0)
1028 switch (boot_cpu_data.x86_vendor) {
1029 case X86_VENDOR_AMD:
1030 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1031 (boot_cpu_data.x86 == 15))
1034 case X86_VENDOR_INTEL:
1035 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1036 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1043 if (!cpu_has_apic) {
1045 * Over-ride BIOS and try to enable the local APIC only if
1046 * "lapic" specified.
1048 if (enable_local_apic <= 0) {
1049 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1050 "you can enable it with \"lapic\"\n");
1054 * Some BIOSes disable the local APIC in the APIC_BASE
1055 * MSR. This can only be done in software for Intel P6 or later
1056 * and AMD K7 (Model > 1) or later.
1058 rdmsr(MSR_IA32_APICBASE, l, h);
1059 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1061 "Local APIC disabled by BIOS -- reenabling.\n");
1062 l &= ~MSR_IA32_APICBASE_BASE;
1063 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1064 wrmsr(MSR_IA32_APICBASE, l, h);
1065 enabled_via_apicbase = 1;
1069 * The APIC feature bit should now be enabled
1072 features = cpuid_edx(1);
1073 if (!(features & (1 << X86_FEATURE_APIC))) {
1074 printk(KERN_WARNING "Could not enable APIC!\n");
1077 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1078 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1080 /* The BIOS may have set up the APIC at some other address */
1081 rdmsr(MSR_IA32_APICBASE, l, h);
1082 if (l & MSR_IA32_APICBASE_ENABLE)
1083 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1085 if (nmi_watchdog != NMI_NONE)
1086 nmi_watchdog = NMI_LOCAL_APIC;
1088 printk(KERN_INFO "Found and enabled local APIC!\n");
1095 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1100 * init_apic_mappings - initialize APIC mappings
1102 void __init init_apic_mappings(void)
1104 unsigned long apic_phys;
1107 * If no local APIC can be found then set up a fake all
1108 * zeroes page to simulate the local APIC and another
1109 * one for the IO-APIC.
1111 if (!smp_found_config && detect_init_APIC()) {
1112 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1113 apic_phys = __pa(apic_phys);
1115 apic_phys = mp_lapic_addr;
1117 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1118 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1122 * Fetch the APIC ID of the BSP in case we have a
1123 * default configuration (or the MP table is broken).
1125 if (boot_cpu_physical_apicid == -1U)
1126 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1128 #ifdef CONFIG_X86_IO_APIC
1130 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
1133 for (i = 0; i < nr_ioapics; i++) {
1134 if (smp_found_config) {
1135 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
1138 "WARNING: bogus zero IO-APIC "
1139 "address found in MPTABLE, "
1140 "disabling IO/APIC support!\n");
1141 smp_found_config = 0;
1142 skip_ioapic_setup = 1;
1143 goto fake_ioapic_page;
1147 ioapic_phys = (unsigned long)
1148 alloc_bootmem_pages(PAGE_SIZE);
1149 ioapic_phys = __pa(ioapic_phys);
1151 set_fixmap_nocache(idx, ioapic_phys);
1152 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
1153 __fix_to_virt(idx), ioapic_phys);
1161 * This initializes the IO-APIC and APIC hardware if this is
1164 int __init APIC_init_uniprocessor (void)
1166 if (enable_local_apic < 0)
1167 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1169 if (!smp_found_config && !cpu_has_apic)
1173 * Complain if the BIOS pretends there is one.
1175 if (!cpu_has_apic &&
1176 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1177 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1178 boot_cpu_physical_apicid);
1179 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1183 verify_local_APIC();
1188 * Hack: In case of kdump, after a crash, kernel might be booting
1189 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1190 * might be zero if read from MP tables. Get it from LAPIC.
1192 #ifdef CONFIG_CRASH_DUMP
1193 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1195 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1199 #ifdef CONFIG_X86_IO_APIC
1200 if (smp_found_config)
1201 if (!skip_ioapic_setup && nr_ioapics)
1210 * APIC command line parameters
1212 static int __init parse_lapic(char *arg)
1214 enable_local_apic = 1;
1217 early_param("lapic", parse_lapic);
1219 static int __init parse_nolapic(char *arg)
1221 enable_local_apic = -1;
1222 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1225 early_param("nolapic", parse_nolapic);
1227 static int __init parse_disable_lapic_timer(char *arg)
1229 local_apic_timer_disabled = 1;
1232 early_param("nolapic_timer", parse_disable_lapic_timer);
1234 static int __init apic_set_verbosity(char *str)
1236 if (strcmp("debug", str) == 0)
1237 apic_verbosity = APIC_DEBUG;
1238 else if (strcmp("verbose", str) == 0)
1239 apic_verbosity = APIC_VERBOSE;
1243 __setup("apic=", apic_set_verbosity);
1247 * Local APIC interrupts
1251 * This interrupt should _never_ happen with our APIC/SMP architecture
1253 void smp_spurious_interrupt(struct pt_regs *regs)
1259 * Check if this really is a spurious interrupt and ACK it
1260 * if it is a vectored one. Just in case...
1261 * Spurious interrupts should not be ACKed.
1263 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1264 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1267 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1268 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1269 "should never happen.\n", smp_processor_id());
1274 * This interrupt should never happen with our APIC/SMP architecture
1276 void smp_error_interrupt(struct pt_regs *regs)
1278 unsigned long v, v1;
1281 /* First tickle the hardware, only then report what went on. -- REW */
1282 v = apic_read(APIC_ESR);
1283 apic_write(APIC_ESR, 0);
1284 v1 = apic_read(APIC_ESR);
1286 atomic_inc(&irq_err_count);
1288 /* Here is what the APIC error bits mean:
1291 2: Send accept error
1292 3: Receive accept error
1294 5: Send illegal vector
1295 6: Received illegal vector
1296 7: Illegal register address
1298 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1299 smp_processor_id(), v , v1);
1304 * Initialize APIC interrupts
1306 void __init apic_intr_init(void)
1311 /* self generated IPI for local APIC timer */
1312 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1314 /* IPI vectors for APIC spurious and error interrupts */
1315 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1316 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1318 /* thermal monitor LVT interrupt */
1319 #ifdef CONFIG_X86_MCE_P4THERMAL
1320 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1325 * connect_bsp_APIC - attach the APIC to the interrupt system
1327 void __init connect_bsp_APIC(void)
1331 * Do not trust the local APIC being empty at bootup.
1335 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1336 * local APIC to INT and NMI lines.
1338 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1339 "enabling APIC mode.\n");
1347 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1348 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1350 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1353 void disconnect_bsp_APIC(int virt_wire_setup)
1357 * Put the board back into PIC mode (has an effect only on
1358 * certain older boards). Note that APIC interrupts, including
1359 * IPIs, won't work beyond this point! The only exception are
1362 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1363 "entering PIC mode.\n");
1367 /* Go back to Virtual Wire compatibility mode */
1368 unsigned long value;
1370 /* For the spurious interrupt use vector F, and enable it */
1371 value = apic_read(APIC_SPIV);
1372 value &= ~APIC_VECTOR_MASK;
1373 value |= APIC_SPIV_APIC_ENABLED;
1375 apic_write_around(APIC_SPIV, value);
1377 if (!virt_wire_setup) {
1379 * For LVT0 make it edge triggered, active high,
1380 * external and enabled
1382 value = apic_read(APIC_LVT0);
1383 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1384 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1385 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
1386 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1387 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1388 apic_write_around(APIC_LVT0, value);
1391 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
1395 * For LVT1 make it edge triggered, active high, nmi and
1398 value = apic_read(APIC_LVT1);
1400 APIC_MODE_MASK | APIC_SEND_PENDING |
1401 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1402 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1403 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1404 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1405 apic_write_around(APIC_LVT1, value);
1416 /* r/w apic fields */
1417 unsigned int apic_id;
1418 unsigned int apic_taskpri;
1419 unsigned int apic_ldr;
1420 unsigned int apic_dfr;
1421 unsigned int apic_spiv;
1422 unsigned int apic_lvtt;
1423 unsigned int apic_lvtpc;
1424 unsigned int apic_lvt0;
1425 unsigned int apic_lvt1;
1426 unsigned int apic_lvterr;
1427 unsigned int apic_tmict;
1428 unsigned int apic_tdcr;
1429 unsigned int apic_thmr;
1432 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1434 unsigned long flags;
1437 if (!apic_pm_state.active)
1440 maxlvt = lapic_get_maxlvt();
1442 apic_pm_state.apic_id = apic_read(APIC_ID);
1443 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1444 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1445 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1446 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1447 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1449 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1450 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1451 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1452 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1453 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1454 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1455 #ifdef CONFIG_X86_MCE_P4THERMAL
1457 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1460 local_irq_save(flags);
1461 disable_local_APIC();
1462 local_irq_restore(flags);
1466 static int lapic_resume(struct sys_device *dev)
1469 unsigned long flags;
1472 if (!apic_pm_state.active)
1475 maxlvt = lapic_get_maxlvt();
1477 local_irq_save(flags);
1480 * Make sure the APICBASE points to the right address
1482 * FIXME! This will be wrong if we ever support suspend on
1483 * SMP! We'll need to do this as part of the CPU restore!
1485 rdmsr(MSR_IA32_APICBASE, l, h);
1486 l &= ~MSR_IA32_APICBASE_BASE;
1487 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1488 wrmsr(MSR_IA32_APICBASE, l, h);
1490 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1491 apic_write(APIC_ID, apic_pm_state.apic_id);
1492 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1493 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1494 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1495 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1496 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1497 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1498 #ifdef CONFIG_X86_MCE_P4THERMAL
1500 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1503 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1504 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1505 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1506 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1507 apic_write(APIC_ESR, 0);
1508 apic_read(APIC_ESR);
1509 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1510 apic_write(APIC_ESR, 0);
1511 apic_read(APIC_ESR);
1512 local_irq_restore(flags);
1517 * This device has no shutdown method - fully functioning local APICs
1518 * are needed on every CPU up until machine_halt/restart/poweroff.
1521 static struct sysdev_class lapic_sysclass = {
1522 set_kset_name("lapic"),
1523 .resume = lapic_resume,
1524 .suspend = lapic_suspend,
1527 static struct sys_device device_lapic = {
1529 .cls = &lapic_sysclass,
1532 static void __devinit apic_pm_activate(void)
1534 apic_pm_state.active = 1;
1537 static int __init init_lapic_sysfs(void)
1543 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1545 error = sysdev_class_register(&lapic_sysclass);
1547 error = sysdev_register(&device_lapic);
1550 device_initcall(init_lapic_sysfs);
1552 #else /* CONFIG_PM */
1554 static void apic_pm_activate(void) { }
1556 #endif /* CONFIG_PM */