2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is the same as v1, but adds voltage scaling.
12 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
13 * voltage scaling support has currently been disabled in this driver
14 * until we have code that gets it right.
15 * Version 3 of longhaul got renamed to Powersaver and redesigned
16 * to use the POWERSAVER MSR at 0x110a.
17 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
18 * It's pretty much the same feature wise to longhaul v2, though
19 * there is provision for scaling FSB too, but this doesn't work
20 * too well in practice so we don't even try to use this.
22 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/cpufreq.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
35 #include <asm/timex.h>
38 #include <linux/acpi.h>
39 #include <acpi/processor.h>
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
53 #define CPU_NEHEMIAH 5
56 #define USE_ACPI_C3 (1 << 1)
57 #define USE_NORTHBRIDGE (1 << 2)
60 static unsigned int numscales=16;
61 static unsigned int fsb;
63 static struct mV_pos *vrm_mV_table;
64 static unsigned char *mV_vrm_table;
68 static struct f_msr f_msr_table[32];
70 static unsigned int highest_speed, lowest_speed; /* kHz */
71 static unsigned int minmult, maxmult;
72 static int can_scale_voltage;
73 static struct acpi_processor *pr = NULL;
74 static struct acpi_processor_cx *cx = NULL;
75 static u8 longhaul_flags;
77 /* Module parameters */
78 static int scale_voltage;
79 static int ignore_latency;
81 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
84 /* Clock ratios multiplied by 10 */
85 static int clock_ratio[32];
86 static int eblcr_table[32];
87 static int longhaul_version;
88 static struct cpufreq_frequency_table *longhaul_table;
90 #ifdef CONFIG_CPU_FREQ_DEBUG
91 static char speedbuffer[8];
93 static char *print_speed(int speed)
96 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
101 snprintf(speedbuffer, sizeof(speedbuffer),
102 "%dGHz", speed/1000);
104 snprintf(speedbuffer, sizeof(speedbuffer),
105 "%d.%dGHz", speed/1000, (speed%1000)/100);
112 static unsigned int calc_speed(int mult)
123 static int longhaul_get_cpu_mult(void)
125 unsigned long invalue=0,lo, hi;
127 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
128 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
129 if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
133 return eblcr_table[invalue];
136 /* For processor with BCR2 MSR */
138 static void do_longhaul1(unsigned int clock_ratio_index)
142 rdmsrl(MSR_VIA_BCR2, bcr2.val);
143 /* Enable software clock multiplier */
144 bcr2.bits.ESOFTBF = 1;
145 bcr2.bits.CLOCKMUL = clock_ratio_index;
147 /* Sync to timer tick */
149 /* Change frequency on next halt or sleep */
150 wrmsrl(MSR_VIA_BCR2, bcr2.val);
151 /* Invoke transition */
152 ACPI_FLUSH_CPU_CACHE();
155 /* Disable software clock multiplier */
157 rdmsrl(MSR_VIA_BCR2, bcr2.val);
158 bcr2.bits.ESOFTBF = 0;
159 wrmsrl(MSR_VIA_BCR2, bcr2.val);
162 /* For processor with Longhaul MSR */
164 static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
166 union msr_longhaul longhaul;
169 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
170 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
171 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
172 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
173 longhaul.bits.EnableSoftBusRatio = 1;
175 if (can_scale_voltage) {
176 longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
177 longhaul.bits.EnableSoftVID = 1;
180 /* Sync to timer tick */
182 /* Change frequency on next halt or sleep */
183 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
185 ACPI_FLUSH_CPU_CACHE();
189 ACPI_FLUSH_CPU_CACHE();
192 /* Dummy op - must do something useless after P_LVL3 read */
193 t = inl(acpi_fadt.xpm_tmr_blk.address);
195 /* Disable bus ratio bit */
197 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
198 longhaul.bits.EnableSoftBusRatio = 0;
199 longhaul.bits.EnableSoftBSEL = 0;
200 longhaul.bits.EnableSoftVID = 0;
201 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
205 * longhaul_set_cpu_frequency()
206 * @clock_ratio_index : bitpattern of the new multiplier.
208 * Sets a new clock ratio.
211 static void longhaul_setstate(unsigned int clock_ratio_index)
214 struct cpufreq_freqs freqs;
215 static unsigned int old_ratio=-1;
217 unsigned int pic1_mask, pic2_mask;
219 if (old_ratio == clock_ratio_index)
221 old_ratio = clock_ratio_index;
223 mult = clock_ratio[clock_ratio_index];
227 speed = calc_speed(mult);
228 if ((speed > highest_speed) || (speed < lowest_speed))
231 freqs.old = calc_speed(longhaul_get_cpu_mult());
233 freqs.cpu = 0; /* longhaul.c is UP only driver */
235 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
237 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
238 fsb, mult/10, mult%10, print_speed(speed/1000));
241 local_irq_save(flags);
243 pic2_mask = inb(0xA1);
244 pic1_mask = inb(0x21); /* works on C3. save mask. */
245 outb(0xFF,0xA1); /* Overkill */
246 outb(0xFE,0x21); /* TMR0 only */
248 if (longhaul_flags & USE_NORTHBRIDGE) {
249 /* Disable AGP and PCI arbiters */
251 } else if ((pr != NULL) && pr->flags.bm_control) {
252 /* Disable bus master arbitration */
253 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1,
254 ACPI_MTX_DO_NOT_LOCK);
256 switch (longhaul_version) {
259 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
260 * Software controlled multipliers only.
262 * *NB* Until we get voltage scaling working v1 & v2 are the same code.
263 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
265 case TYPE_LONGHAUL_V1:
266 case TYPE_LONGHAUL_V2:
267 do_longhaul1(clock_ratio_index);
271 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
272 * We can scale voltage with this too, but that's currently
273 * disabled until we come up with a decent 'match freq to voltage'
275 * When we add voltage scaling, we will also need to do the
276 * voltage/freq setting in order depending on the direction
277 * of scaling (like we do in powernow-k7.c)
278 * Nehemiah can do FSB scaling too, but this has never been proven
279 * to work in practice.
281 case TYPE_POWERSAVER:
282 if (longhaul_flags & USE_ACPI_C3) {
283 /* Don't allow wakeup */
284 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0,
285 ACPI_MTX_DO_NOT_LOCK);
286 do_powersaver(cx->address, clock_ratio_index);
288 do_powersaver(0, clock_ratio_index);
293 if (longhaul_flags & USE_NORTHBRIDGE) {
294 /* Enable arbiters */
296 } else if ((pr != NULL) && pr->flags.bm_control) {
297 /* Enable bus master arbitration */
298 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0,
299 ACPI_MTX_DO_NOT_LOCK);
301 outb(pic2_mask,0xA1); /* restore mask */
302 outb(pic1_mask,0x21);
304 local_irq_restore(flags);
307 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
311 * Centaur decided to make life a little more tricky.
312 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
313 * Samuel2 and above have to try and guess what the FSB is.
314 * We do this by assuming we booted at maximum multiplier, and interpolate
315 * between that value multiplied by possible FSBs and cpu_mhz which
316 * was calculated at boot time. Really ugly, but no other way to do this.
321 static int _guess(int guess, int mult)
325 target = ((mult/10)*guess);
328 target += ROUNDING/2;
334 static int guess_fsb(int mult)
336 int speed = (cpu_khz/1000);
338 int speeds[] = { 66, 100, 133, 200 };
343 for (i=0; i<4; i++) {
344 if (_guess(speeds[i], mult) == speed)
351 static int __init longhaul_get_ranges(void)
353 unsigned long invalue;
354 unsigned int ezra_t_multipliers[32]= {
355 90, 30, 40, 100, 55, 35, 45, 95,
356 50, 70, 80, 60, 120, 75, 85, 65,
357 -1, 110, 120, -1, 135, 115, 125, 105,
358 130, 150, 160, 140, -1, 155, -1, 145 };
359 unsigned int j, k = 0;
360 union msr_longhaul longhaul;
361 unsigned long lo, hi;
362 unsigned int eblcr_fsb_table_v1[] = { 66, 133, 100, -1 };
363 unsigned int eblcr_fsb_table_v2[] = { 133, 100, -1, 66 };
366 switch (longhaul_version) {
367 case TYPE_LONGHAUL_V1:
368 case TYPE_LONGHAUL_V2:
369 /* Ugh, Longhaul v1 didn't have the min/max MSRs.
370 Assume min=3.0x & max = whatever we booted at. */
372 maxmult = mult = longhaul_get_cpu_mult();
375 case TYPE_POWERSAVER:
377 if (cpu_model==CPU_EZRA_T) {
379 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
380 invalue = longhaul.bits.MaxMHzBR;
381 if (longhaul.bits.MaxMHzBR4)
383 maxmult = mult = ezra_t_multipliers[invalue];
388 if (cpu_model==CPU_NEHEMIAH) {
389 rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
392 * TODO: This code works, but raises a lot of questions.
393 * - Some Nehemiah's seem to have broken Min/MaxMHzBR's.
394 * We get around this by using a hardcoded multiplier of 4.0x
395 * for the minimimum speed, and the speed we booted up at for the max.
396 * This is done in longhaul_get_cpu_mult() by reading the EBLCR register.
397 * - According to some VIA documentation EBLCR is only
398 * in pre-Nehemiah C3s. How this still works is a mystery.
399 * We're possibly using something undocumented and unsupported,
400 * But it works, so we don't grumble.
403 maxmult = mult = longhaul_get_cpu_mult();
407 fsb = guess_fsb(mult);
409 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
410 minmult/10, minmult%10, maxmult/10, maxmult%10);
413 printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
417 highest_speed = calc_speed(maxmult);
418 lowest_speed = calc_speed(minmult);
419 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
420 print_speed(lowest_speed/1000),
421 print_speed(highest_speed/1000));
423 if (lowest_speed == highest_speed) {
424 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
427 if (lowest_speed > highest_speed) {
428 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
429 lowest_speed, highest_speed);
433 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
437 for (j=0; j < numscales; j++) {
439 ratio = clock_ratio[j];
442 if (ratio > maxmult || ratio < minmult)
444 longhaul_table[k].frequency = calc_speed(ratio);
445 longhaul_table[k].index = j;
449 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
451 kfree (longhaul_table);
459 static void __init longhaul_setup_voltagescaling(void)
461 union msr_longhaul longhaul;
462 struct mV_pos minvid, maxvid;
463 unsigned int j, speed, pos, kHz_step, numvscales;
465 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
466 if (!(longhaul.bits.RevisionID & 1)) {
467 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
471 if (!longhaul.bits.VRMRev) {
472 printk (KERN_INFO PFX "VRM 8.5\n");
473 vrm_mV_table = &vrm85_mV[0];
474 mV_vrm_table = &mV_vrm85[0];
476 printk (KERN_INFO PFX "Mobile VRM\n");
477 vrm_mV_table = &mobilevrm_mV[0];
478 mV_vrm_table = &mV_mobilevrm[0];
481 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
482 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
483 numvscales = maxvid.pos - minvid.pos + 1;
484 kHz_step = (highest_speed - lowest_speed) / numvscales;
486 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
487 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
488 "Voltage scaling disabled.\n",
489 minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
493 if (minvid.mV == maxvid.mV) {
494 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
495 "both %d.%03d. Voltage scaling disabled\n",
496 maxvid.mV/1000, maxvid.mV%1000);
500 printk(KERN_INFO PFX "Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n",
501 maxvid.mV/1000, maxvid.mV%1000,
502 minvid.mV/1000, minvid.mV%1000,
506 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
507 speed = longhaul_table[j].frequency;
508 pos = (speed - lowest_speed) / kHz_step + minvid.pos;
509 f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
513 can_scale_voltage = 1;
517 static int longhaul_verify(struct cpufreq_policy *policy)
519 return cpufreq_frequency_table_verify(policy, longhaul_table);
523 static int longhaul_target(struct cpufreq_policy *policy,
524 unsigned int target_freq, unsigned int relation)
526 unsigned int table_index = 0;
527 unsigned int new_clock_ratio = 0;
529 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
532 new_clock_ratio = longhaul_table[table_index].index & 0xFF;
534 longhaul_setstate(new_clock_ratio);
540 static unsigned int longhaul_get(unsigned int cpu)
544 return calc_speed(longhaul_get_cpu_mult());
547 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
549 void *context, void **return_value)
551 struct acpi_device *d;
553 if ( acpi_bus_get_device(obj_handle, &d) ) {
556 *return_value = (void *)acpi_driver_data(d);
560 /* VIA don't support PM2 reg, but have something similar */
561 static int enable_arbiter_disable(void)
567 /* Find PLE133 host bridge */
569 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, NULL);
570 /* Find CLE266 host bridge */
573 dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_862X_0, NULL);
574 /* Find CN400 V-Link host bridge */
576 dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
580 /* Enable access to port 0x22 */
581 pci_read_config_byte(dev, reg, &pci_cmd);
582 if ( !(pci_cmd & 1<<7) ) {
584 pci_write_config_byte(dev, reg, pci_cmd);
591 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
593 struct cpuinfo_x86 *c = cpu_data;
597 /* Check what we have on this motherboard */
598 switch (c->x86_model) {
600 cpu_model = CPU_SAMUEL;
601 cpuname = "C3 'Samuel' [C5A]";
602 longhaul_version = TYPE_LONGHAUL_V1;
603 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
604 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
608 longhaul_version = TYPE_LONGHAUL_V1;
609 switch (c->x86_mask) {
611 cpu_model = CPU_SAMUEL2;
612 cpuname = "C3 'Samuel 2' [C5B]";
613 /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
614 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
615 memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
618 if (c->x86_mask < 8) {
619 cpu_model = CPU_SAMUEL2;
620 cpuname = "C3 'Samuel 2' [C5B]";
622 cpu_model = CPU_EZRA;
623 cpuname = "C3 'Ezra' [C5C]";
625 memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
626 memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
632 cpu_model = CPU_EZRA_T;
633 cpuname = "C3 'Ezra-T' [C5M]";
634 longhaul_version = TYPE_POWERSAVER;
636 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
637 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
641 cpu_model = CPU_NEHEMIAH;
642 longhaul_version = TYPE_POWERSAVER;
644 switch (c->x86_mask) {
646 cpuname = "C3 'Nehemiah A' [C5N]";
647 memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio));
648 memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr));
651 cpuname = "C3 'Nehemiah B' [C5N]";
652 memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio));
653 memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr));
656 cpuname = "C3 'Nehemiah C' [C5N]";
657 memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio));
658 memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr));
668 printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
669 switch (longhaul_version) {
670 case TYPE_LONGHAUL_V1:
671 case TYPE_LONGHAUL_V2:
672 printk ("Longhaul v%d supported.\n", longhaul_version);
674 case TYPE_POWERSAVER:
675 printk ("Powersaver supported.\n");
679 /* Find ACPI data for processor */
680 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
681 &longhaul_walk_callback, NULL, (void *)&pr);
683 /* Check ACPI support for C3 state */
684 if ((pr != NULL) && (longhaul_version == TYPE_POWERSAVER)) {
685 cx = &pr->power.states[ACPI_STATE_C3];
686 if (cx->address > 0 &&
687 (cx->latency <= 1000 || ignore_latency != 0) ) {
688 longhaul_flags |= USE_ACPI_C3;
689 goto print_support_type;
692 /* Check if northbridge is friendly */
693 if (enable_arbiter_disable()) {
694 longhaul_flags |= USE_NORTHBRIDGE;
695 goto print_support_type;
698 /* No ACPI C3 or we can't use it */
699 /* Check ACPI support for bus master arbiter disable */
700 if ((pr == NULL) || !(pr->flags.bm_control)) {
702 "No ACPI support. Unsupported northbridge.\n");
707 if (!(longhaul_flags & USE_NORTHBRIDGE)) {
708 printk (KERN_INFO PFX "Using ACPI support.\n");
710 printk (KERN_INFO PFX "Using northbridge support.\n");
713 ret = longhaul_get_ranges();
717 if ((longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) &&
718 (scale_voltage != 0))
719 longhaul_setup_voltagescaling();
721 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
722 policy->cpuinfo.transition_latency = 200000; /* nsec */
723 policy->cur = calc_speed(longhaul_get_cpu_mult());
725 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
729 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
734 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
736 cpufreq_frequency_table_put_attr(policy->cpu);
740 static struct freq_attr* longhaul_attr[] = {
741 &cpufreq_freq_attr_scaling_available_freqs,
745 static struct cpufreq_driver longhaul_driver = {
746 .verify = longhaul_verify,
747 .target = longhaul_target,
749 .init = longhaul_cpu_init,
750 .exit = __devexit_p(longhaul_cpu_exit),
752 .owner = THIS_MODULE,
753 .attr = longhaul_attr,
757 static int __init longhaul_init(void)
759 struct cpuinfo_x86 *c = cpu_data;
761 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
765 if (num_online_cpus() > 1) {
766 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
770 #ifdef CONFIG_X86_IO_APIC
772 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
776 switch (c->x86_model) {
778 return cpufreq_register_driver(&longhaul_driver);
780 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
789 static void __exit longhaul_exit(void)
793 for (i=0; i < numscales; i++) {
794 if (clock_ratio[i] == maxmult) {
795 longhaul_setstate(i);
800 cpufreq_unregister_driver(&longhaul_driver);
801 kfree(longhaul_table);
804 module_param (scale_voltage, int, 0644);
805 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
806 module_param(ignore_latency, int, 0644);
807 MODULE_PARM_DESC(ignore_latency, "Skip ACPI C3 latency test");
809 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
810 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
811 MODULE_LICENSE ("GPL");
813 late_initcall(longhaul_init);
814 module_exit(longhaul_exit);