2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
5 * Since the original Pentium M, most new Intel CPUs support Enhanced
8 * Despite the "SpeedStep" in the name, this is almost entirely unlike
9 * traditional SpeedStep.
11 * Modelled on speedstep.c
13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/cpufreq.h>
20 #include <linux/config.h>
21 #include <linux/sched.h> /* current */
22 #include <linux/delay.h>
23 #include <linux/compiler.h>
25 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
26 #include <linux/acpi.h>
27 #include <acpi/processor.h>
31 #include <asm/processor.h>
32 #include <asm/cpufeature.h>
34 #define PFX "speedstep-centrino: "
35 #define MAINTAINER "cpufreq@lists.linux.org.uk"
37 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
42 __u8 x86; /* CPU family */
43 __u8 x86_model; /* model */
44 __u8 x86_mask; /* stepping */
56 static const struct cpu_id cpu_ids[] = {
57 [CPU_BANIAS] = { 6, 9, 5 },
58 [CPU_DOTHAN_A1] = { 6, 13, 1 },
59 [CPU_DOTHAN_A2] = { 6, 13, 2 },
60 [CPU_DOTHAN_B0] = { 6, 13, 6 },
61 [CPU_MP4HT_D0] = {15, 3, 4 },
62 [CPU_MP4HT_E0] = {15, 4, 1 },
64 #define N_IDS ARRAY_SIZE(cpu_ids)
68 const struct cpu_id *cpu_id;
69 const char *model_name;
70 unsigned max_freq; /* max clock in kHz */
72 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
74 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
76 /* Operating points for current CPU */
77 static struct cpu_model *centrino_model[NR_CPUS];
78 static const struct cpu_id *centrino_cpu[NR_CPUS];
80 static struct cpufreq_driver centrino_driver;
82 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
84 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
85 frequency/voltage operating point; frequency in MHz, volts in mV.
86 This is stored as "index" in the structure. */
89 .frequency = (mhz) * 1000, \
90 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
94 * These voltage tables were derived from the Intel Pentium M
95 * datasheet, document 25261202.pdf, Table 5. I have verified they
96 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
100 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
101 static struct cpufreq_frequency_table banias_900[] =
106 { .frequency = CPUFREQ_TABLE_END }
109 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
110 static struct cpufreq_frequency_table banias_1000[] =
116 { .frequency = CPUFREQ_TABLE_END }
119 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
120 static struct cpufreq_frequency_table banias_1100[] =
127 { .frequency = CPUFREQ_TABLE_END }
131 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
132 static struct cpufreq_frequency_table banias_1200[] =
140 { .frequency = CPUFREQ_TABLE_END }
143 /* Intel Pentium M processor 1.30GHz (Banias) */
144 static struct cpufreq_frequency_table banias_1300[] =
151 { .frequency = CPUFREQ_TABLE_END }
154 /* Intel Pentium M processor 1.40GHz (Banias) */
155 static struct cpufreq_frequency_table banias_1400[] =
162 { .frequency = CPUFREQ_TABLE_END }
165 /* Intel Pentium M processor 1.50GHz (Banias) */
166 static struct cpufreq_frequency_table banias_1500[] =
174 { .frequency = CPUFREQ_TABLE_END }
177 /* Intel Pentium M processor 1.60GHz (Banias) */
178 static struct cpufreq_frequency_table banias_1600[] =
186 { .frequency = CPUFREQ_TABLE_END }
189 /* Intel Pentium M processor 1.70GHz (Banias) */
190 static struct cpufreq_frequency_table banias_1700[] =
198 { .frequency = CPUFREQ_TABLE_END }
202 #define _BANIAS(cpuid, max, name) \
204 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
205 .max_freq = (max)*1000, \
206 .op_points = banias_##max, \
208 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
210 /* CPU models, their operating frequency range, and freq/voltage
212 static struct cpu_model models[] =
214 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
224 /* NULL model_name is a wildcard */
225 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
226 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
227 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
228 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
229 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
236 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
238 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
239 struct cpu_model *model;
241 for(model = models; model->cpu_id != NULL; model++)
242 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
243 (model->model_name == NULL ||
244 strcmp(cpu->x86_model_id, model->model_name) == 0))
247 if (model->cpu_id == NULL) {
248 /* No match at all */
249 dprintk("no support for CPU model \"%s\": "
250 "send /proc/cpuinfo to " MAINTAINER "\n",
255 if (model->op_points == NULL) {
256 /* Matched a non-match */
257 dprintk("no table support for CPU model \"%s\"\n",
259 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
260 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
265 centrino_model[policy->cpu] = model;
267 dprintk("found \"%s\": max frequency: %dkHz\n",
268 model->model_name, model->max_freq);
274 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
275 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
277 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
279 if ((c->x86 == x->x86) &&
280 (c->x86_model == x->x86_model) &&
281 (c->x86_mask == x->x86_mask))
286 /* To be called only after centrino_model is initialized */
287 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
292 * Extract clock in kHz from PERF_CTL value
293 * for centrino, as some DSDTs are buggy.
294 * Ideally, this can be done using the acpi_data structure.
296 if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
297 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
298 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
299 msr = (msr >> 8) & 0xff;
303 if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
307 for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
308 if (msr == centrino_model[cpu]->op_points[i].index)
309 return centrino_model[cpu]->op_points[i].frequency;
312 return centrino_model[cpu]->op_points[i-1].frequency;
317 /* Return the current CPU frequency in kHz */
318 static unsigned int get_cur_freq(unsigned int cpu)
322 cpumask_t saved_mask;
324 saved_mask = current->cpus_allowed;
325 set_cpus_allowed(current, cpumask_of_cpu(cpu));
326 if (smp_processor_id() != cpu)
329 rdmsr(MSR_IA32_PERF_STATUS, l, h);
330 clock_freq = extract_clock(l, cpu, 0);
332 if (unlikely(clock_freq == 0)) {
334 * On some CPUs, we can see transient MSR values (which are
335 * not present in _PSS), while CPU is doing some automatic
336 * P-state transition (like TM2). Get the last freq set
339 rdmsr(MSR_IA32_PERF_CTL, l, h);
340 clock_freq = extract_clock(l, cpu, 1);
343 set_cpus_allowed(current, saved_mask);
348 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
350 static struct acpi_processor_performance *acpi_perf_data[NR_CPUS];
353 * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States
356 * Before doing the actual init, we need to do _PSD related setup whenever
357 * supported by the BIOS. These are handled by this early_init routine.
359 static int centrino_cpu_early_init_acpi(void)
362 struct acpi_processor_performance *data;
364 for_each_possible_cpu(i) {
365 data = kzalloc(sizeof(struct acpi_processor_performance),
368 for_each_possible_cpu(j) {
369 kfree(acpi_perf_data[j]);
370 acpi_perf_data[j] = NULL;
374 acpi_perf_data[i] = data;
377 acpi_processor_preregister_performance(acpi_perf_data);
382 * centrino_cpu_init_acpi - register with ACPI P-States library
384 * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
385 * in order to determine correct frequency and voltage pairings by reading
386 * the _PSS of the ACPI DSDT or SSDT tables.
388 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
390 unsigned long cur_freq;
392 unsigned int cpu = policy->cpu;
393 struct acpi_processor_performance *p;
395 p = acpi_perf_data[cpu];
397 /* register with ACPI core */
398 if (acpi_processor_register_performance(p, cpu)) {
399 dprintk(PFX "obtaining ACPI data failed\n");
402 policy->cpus = p->shared_cpu_map;
403 policy->shared_type = p->shared_type;
405 /* verify the acpi_data */
406 if (p->state_count <= 1) {
407 dprintk("No P-States\n");
412 if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
413 (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
414 dprintk("Invalid control/status registers (%x - %x)\n",
415 p->control_register.space_id, p->status_register.space_id);
420 for (i=0; i<p->state_count; i++) {
421 if (p->states[i].control != p->states[i].status) {
422 dprintk("Different control (%llu) and status values (%llu)\n",
423 p->states[i].control, p->states[i].status);
428 if (!p->states[i].core_frequency) {
429 dprintk("Zero core frequency for state %u\n", i);
434 if (p->states[i].core_frequency > p->states[0].core_frequency) {
435 dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
436 p->states[i].core_frequency, p->states[0].core_frequency);
437 p->states[i].core_frequency = 0;
442 centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
443 if (!centrino_model[cpu]) {
448 centrino_model[cpu]->model_name=NULL;
449 centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000;
450 centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
451 (p->state_count + 1), GFP_KERNEL);
452 if (!centrino_model[cpu]->op_points) {
457 for (i=0; i<p->state_count; i++) {
458 centrino_model[cpu]->op_points[i].index = p->states[i].control;
459 centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
460 dprintk("adding state %i with frequency %u and control value %04x\n",
461 i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
463 centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END;
465 cur_freq = get_cur_freq(cpu);
467 for (i=0; i<p->state_count; i++) {
468 if (!p->states[i].core_frequency) {
469 dprintk("skipping state %u\n", i);
470 centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
474 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
475 (centrino_model[cpu]->op_points[i].frequency)) {
476 dprintk("Invalid encoded frequency (%u vs. %u)\n",
477 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
478 centrino_model[cpu]->op_points[i].frequency);
483 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
487 /* notify BIOS that we exist */
488 acpi_processor_notify_smm(THIS_MODULE);
493 kfree(centrino_model[cpu]->op_points);
495 kfree(centrino_model[cpu]);
497 acpi_processor_unregister_performance(p, cpu);
498 dprintk(PFX "invalid ACPI data\n");
502 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
503 static inline int centrino_cpu_early_init_acpi(void) { return 0; }
506 static int centrino_cpu_init(struct cpufreq_policy *policy)
508 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
514 /* Only Intel makes Enhanced Speedstep-capable CPUs */
515 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
518 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
519 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
521 if (centrino_cpu_init_acpi(policy)) {
522 if (policy->cpu != 0)
525 for (i = 0; i < N_IDS; i++)
526 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
530 centrino_cpu[policy->cpu] = &cpu_ids[i];
532 if (!centrino_cpu[policy->cpu]) {
533 dprintk("found unsupported CPU with "
534 "Enhanced SpeedStep: send /proc/cpuinfo to "
539 if (centrino_cpu_init_table(policy)) {
544 /* Check to see if Enhanced SpeedStep is enabled, and try to
546 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
548 if (!(l & (1<<16))) {
550 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
551 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
553 /* check to see if it stuck */
554 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
555 if (!(l & (1<<16))) {
556 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
561 freq = get_cur_freq(policy->cpu);
563 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
564 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
567 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
569 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
573 cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
578 static int centrino_cpu_exit(struct cpufreq_policy *policy)
580 unsigned int cpu = policy->cpu;
582 if (!centrino_model[cpu])
585 cpufreq_frequency_table_put_attr(cpu);
587 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
588 if (!centrino_model[cpu]->model_name) {
589 static struct acpi_processor_performance *p;
591 if (acpi_perf_data[cpu]) {
592 p = acpi_perf_data[cpu];
593 dprintk("unregistering and freeing ACPI data\n");
594 acpi_processor_unregister_performance(p, cpu);
595 kfree(centrino_model[cpu]->op_points);
596 kfree(centrino_model[cpu]);
601 centrino_model[cpu] = NULL;
607 * centrino_verify - verifies a new CPUFreq policy
608 * @policy: new policy
610 * Limit must be within this model's frequency range at least one
613 static int centrino_verify (struct cpufreq_policy *policy)
615 return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
619 * centrino_setpolicy - set a new CPUFreq policy
620 * @policy: new policy
621 * @target_freq: the target frequency
622 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
624 * Sets a new CPUFreq policy.
626 static int centrino_target (struct cpufreq_policy *policy,
627 unsigned int target_freq,
628 unsigned int relation)
630 unsigned int newstate = 0;
631 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
632 struct cpufreq_freqs freqs;
633 cpumask_t online_policy_cpus;
634 cpumask_t saved_mask;
636 cpumask_t covered_cpus;
638 unsigned int j, k, first_cpu, tmp;
640 if (unlikely(centrino_model[cpu] == NULL))
643 if (unlikely(cpufreq_frequency_table_target(policy,
644 centrino_model[cpu]->op_points,
651 #ifdef CONFIG_HOTPLUG_CPU
652 /* cpufreq holds the hotplug lock, so we are safe from here on */
653 cpus_and(online_policy_cpus, cpu_online_map, policy->cpus);
655 online_policy_cpus = policy->cpus;
658 saved_mask = current->cpus_allowed;
660 cpus_clear(covered_cpus);
661 for_each_cpu_mask(j, online_policy_cpus) {
663 * Support for SMP systems.
664 * Make sure we are running on CPU that wants to change freq
666 cpus_clear(set_mask);
667 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
668 cpus_or(set_mask, set_mask, online_policy_cpus);
670 cpu_set(j, set_mask);
672 set_cpus_allowed(current, set_mask);
673 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) {
674 dprintk("couldn't limit to CPUs in this domain\n");
677 /* We haven't started the transition yet. */
683 msr = centrino_model[cpu]->op_points[newstate].index;
686 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
687 if (msr == (oldmsr & 0xffff)) {
688 dprintk("no change needed - msr was and needs "
689 "to be %x\n", oldmsr);
694 freqs.old = extract_clock(oldmsr, cpu, 0);
695 freqs.new = extract_clock(msr, cpu, 0);
697 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
698 target_freq, freqs.old, freqs.new, msr);
700 for_each_cpu_mask(k, online_policy_cpus) {
702 cpufreq_notify_transition(&freqs,
707 /* all but 16 LSB are reserved, treat them with care */
713 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
714 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
717 cpu_set(j, covered_cpus);
720 for_each_cpu_mask(k, online_policy_cpus) {
722 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
725 if (unlikely(retval)) {
727 * We have failed halfway through the frequency change.
728 * We have sent callbacks to policy->cpus and
729 * MSRs have already been written on coverd_cpus.
733 if (!cpus_empty(covered_cpus)) {
734 for_each_cpu_mask(j, covered_cpus) {
735 set_cpus_allowed(current, cpumask_of_cpu(j));
736 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
741 freqs.new = freqs.old;
743 for_each_cpu_mask(j, online_policy_cpus) {
745 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
746 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
751 set_cpus_allowed(current, saved_mask);
755 static struct freq_attr* centrino_attr[] = {
756 &cpufreq_freq_attr_scaling_available_freqs,
760 static struct cpufreq_driver centrino_driver = {
761 .name = "centrino", /* should be speedstep-centrino,
762 but there's a 16 char limit */
763 .init = centrino_cpu_init,
764 .exit = centrino_cpu_exit,
765 .verify = centrino_verify,
766 .target = centrino_target,
768 .attr = centrino_attr,
769 .owner = THIS_MODULE,
774 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
776 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
777 * unsupported devices, -ENOENT if there's no voltage table for this
778 * particular CPU model, -EINVAL on problems during initiatization,
779 * and zero on success.
781 * This is quite picky. Not only does the CPU have to advertise the
782 * "est" flag in the cpuid capability flags, we look for a specific
783 * CPU model and stepping, and we need to have the exact model name in
784 * our voltage tables. That is, be paranoid about not releasing
785 * someone's valuable magic smoke.
787 static int __init centrino_init(void)
789 struct cpuinfo_x86 *cpu = cpu_data;
791 if (!cpu_has(cpu, X86_FEATURE_EST))
794 centrino_cpu_early_init_acpi();
796 return cpufreq_register_driver(¢rino_driver);
799 static void __exit centrino_exit(void)
801 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
805 cpufreq_unregister_driver(¢rino_driver);
807 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
808 for_each_possible_cpu(j) {
809 kfree(acpi_perf_data[j]);
810 acpi_perf_data[j] = NULL;
815 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
816 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
817 MODULE_LICENSE ("GPL");
819 late_initcall(centrino_init);
820 module_exit(centrino_exit);