arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/compiler.h>
  32 #include <linux/acpi.h>
  33 #include <linux/module.h>
  34 #include <linux/sysdev.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41
  42 #include <mach_apic.h>
  43
  44 #include "io_ports.h"
  45
  46 int (*ioapic_renumber_irq)(int ioapic, int irq);
  47 atomic_t irq_mis_count;
  48
  49 /* Where if anywhere is the i8259 connect in external int mode */
  50 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  51
  52 static DEFINE_SPINLOCK(ioapic_lock);
  53
  54 int timer_over_8254 __initdata = 1;
  55
  56 /*
  57  *      Is the SiS APIC rmw bug present ?
  58  *      -1 = don't know, 0 = no, 1 = yes
  59  */
  60 int sis_apic_bug = -1;
  61
  62 /*
  63  * # of IRQ routing registers
  64  */
  65 int nr_ioapic_registers[MAX_IO_APICS];
  66
  67 int disable_timer_pin_1 __initdata;
  68
  69 /*
  70  * Rough estimation of how many shared IRQs there are, can
  71  * be changed anytime.
  72  */
  73 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  74 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  75
  76 /*
  77  * This is performance-critical, we want to do it O(1)
  78  *
  79  * the indexing order of this array favors 1:1 mappings
  80  * between pins and IRQs.
  81  */
  82
  83 static struct irq_pin_list {
  84         int apic, pin, next;
  85 } irq_2_pin[PIN_MAP_SIZE];
  86
  87 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  88 #ifdef CONFIG_PCI_MSI
  89 #define vector_to_irq(vector)   \
  90         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  91 #else
  92 #define vector_to_irq(vector)   (vector)
  93 #endif
  94
  95 /*
  96  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  97  * shared ISA-space IRQs, so we have to support them. We are super
  98  * fast in the common case, and fast for shared ISA-space IRQs.
  99  */
 100 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 101 {
 102         static int first_free_entry = NR_IRQS;
 103         struct irq_pin_list *entry = irq_2_pin + irq;
 104
 105         while (entry->next)
 106                 entry = irq_2_pin + entry->next;
 107
 108         if (entry->pin != -1) {
 109                 entry->next = first_free_entry;
 110                 entry = irq_2_pin + entry->next;
 111                 if (++first_free_entry >= PIN_MAP_SIZE)
 112                         panic("io_apic.c: whoops");
 113         }
 114         entry->apic = apic;
 115         entry->pin = pin;
 116 }
 117
 118 /*
 119  * Reroute an IRQ to a different pin.
 120  */
 121 static void __init replace_pin_at_irq(unsigned int irq,
 122                                       int oldapic, int oldpin,
 123                                       int newapic, int newpin)
 124 {
 125         struct irq_pin_list *entry = irq_2_pin + irq;
 126
 127         while (1) {
 128                 if (entry->apic == oldapic && entry->pin == oldpin) {
 129                         entry->apic = newapic;
 130                         entry->pin = newpin;
 131                 }
 132                 if (!entry->next)
 133                         break;
 134                 entry = irq_2_pin + entry->next;
 135         }
 136 }
 137
 138 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 139 {
 140         struct irq_pin_list *entry = irq_2_pin + irq;
 141         unsigned int pin, reg;
 142
 143         for (;;) {
 144                 pin = entry->pin;
 145                 if (pin == -1)
 146                         break;
 147                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 148                 reg &= ~disable;
 149                 reg |= enable;
 150                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 151                 if (!entry->next)
 152                         break;
 153                 entry = irq_2_pin + entry->next;
 154         }
 155 }
 156
 157 /* mask = 1 */
 158 static void __mask_IO_APIC_irq (unsigned int irq)
 159 {
 160         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 161 }
 162
 163 /* mask = 0 */
 164 static void __unmask_IO_APIC_irq (unsigned int irq)
 165 {
 166         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 167 }
 168
 169 /* mask = 1, trigger = 0 */
 170 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 171 {
 172         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 173 }
 174
 175 /* mask = 0, trigger = 1 */
 176 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 177 {
 178         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 179 }
 180
 181 static void mask_IO_APIC_irq (unsigned int irq)
 182 {
 183         unsigned long flags;
 184
 185         spin_lock_irqsave(&ioapic_lock, flags);
 186         __mask_IO_APIC_irq(irq);
 187         spin_unlock_irqrestore(&ioapic_lock, flags);
 188 }
 189
 190 static void unmask_IO_APIC_irq (unsigned int irq)
 191 {
 192         unsigned long flags;
 193
 194         spin_lock_irqsave(&ioapic_lock, flags);
 195         __unmask_IO_APIC_irq(irq);
 196         spin_unlock_irqrestore(&ioapic_lock, flags);
 197 }
 198
 199 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 200 {
 201         struct IO_APIC_route_entry entry;
 202         unsigned long flags;
 203
 204         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 205         spin_lock_irqsave(&ioapic_lock, flags);
 206         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 207         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 208         spin_unlock_irqrestore(&ioapic_lock, flags);
 209         if (entry.delivery_mode == dest_SMI)
 210                 return;
 211
 212         /*
 213          * Disable it in the IO-APIC irq-routing table:
 214          */
 215         memset(&entry, 0, sizeof(entry));
 216         entry.mask = 1;
 217         spin_lock_irqsave(&ioapic_lock, flags);
 218         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 219         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 220         spin_unlock_irqrestore(&ioapic_lock, flags);
 221 }
 222
 223 static void clear_IO_APIC (void)
 224 {
 225         int apic, pin;
 226
 227         for (apic = 0; apic < nr_ioapics; apic++)
 228                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 229                         clear_IO_APIC_pin(apic, pin);
 230 }
 231
 232 #ifdef CONFIG_SMP
 233 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 234 {
 235         unsigned long flags;
 236         int pin;
 237         struct irq_pin_list *entry = irq_2_pin + irq;
 238         unsigned int apicid_value;
 239         cpumask_t tmp;
 240
 241         cpus_and(tmp, cpumask, cpu_online_map);
 242         if (cpus_empty(tmp))
 243                 tmp = TARGET_CPUS;
 244
 245         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 246
 247         apicid_value = cpu_mask_to_apicid(cpumask);
 248         /* Prepare to do the io_apic_write */
 249         apicid_value = apicid_value << 24;
 250         spin_lock_irqsave(&ioapic_lock, flags);
 251         for (;;) {
 252                 pin = entry->pin;
 253                 if (pin == -1)
 254                         break;
 255                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 256                 if (!entry->next)
 257                         break;
 258                 entry = irq_2_pin + entry->next;
 259         }
 260         set_irq_info(irq, cpumask);
 261         spin_unlock_irqrestore(&ioapic_lock, flags);
 262 }
 263
 264 #if defined(CONFIG_IRQBALANCE)
 265 # include <asm/processor.h>     /* kernel_thread() */
 266 # include <linux/kernel_stat.h> /* kstat */
 267 # include <linux/slab.h>                /* kmalloc() */
 268 # include <linux/timer.h>       /* time_after() */
 269
 270 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 271 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 272 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 273 # else
 274 #  define TDprintk(x...)
 275 #  define Dprintk(x...)
 276 # endif
 277
 278 #define IRQBALANCE_CHECK_ARCH -999
 279 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 280 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 281 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 282 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 283
 284 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 285 static int physical_balance __read_mostly;
 286 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 287
 288 static struct irq_cpu_info {
 289         unsigned long * last_irq;
 290         unsigned long * irq_delta;
 291         unsigned long irq;
 292 } irq_cpu_data[NR_CPUS];
 293
 294 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 295 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 296 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 297
 298 #define IDLE_ENOUGH(cpu,now) \
 299         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 300
 301 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 302
 303 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 304
 305 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 306         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 307 };
 308
 309 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 310 {
 311         balance_irq_affinity[irq] = mask;
 312 }
 313
 314 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 315                         unsigned long now, int direction)
 316 {
 317         int search_idle = 1;
 318         int cpu = curr_cpu;
 319
 320         goto inside;
 321
 322         do {
 323                 if (unlikely(cpu == curr_cpu))
 324                         search_idle = 0;
 325 inside:
 326                 if (direction == 1) {
 327                         cpu++;
 328                         if (cpu >= NR_CPUS)
 329                                 cpu = 0;
 330                 } else {
 331                         cpu--;
 332                         if (cpu == -1)
 333                                 cpu = NR_CPUS-1;
 334                 }
 335         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 336                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 337
 338         return cpu;
 339 }
 340
 341 static inline void balance_irq(int cpu, int irq)
 342 {
 343         unsigned long now = jiffies;
 344         cpumask_t allowed_mask;
 345         unsigned int new_cpu;
 346
 347         if (irqbalance_disabled)
 348                 return;
 349
 350         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 351         new_cpu = move(cpu, allowed_mask, now, 1);
 352         if (cpu != new_cpu) {
 353                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 354         }
 355 }
 356
 357 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 358 {
 359         int i, j;
 360         Dprintk("Rotating IRQs among CPUs.\n");
 361         for_each_online_cpu(i) {
 362                 for (j = 0; j < NR_IRQS; j++) {
 363                         if (!irq_desc[j].action)
 364                                 continue;
 365                         /* Is it a significant load ?  */
 366                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 367                                                 useful_load_threshold)
 368                                 continue;
 369                         balance_irq(i, j);
 370                 }
 371         }
 372         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 373                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 374         return;
 375 }
 376
 377 static void do_irq_balance(void)
 378 {
 379         int i, j;
 380         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 381         unsigned long move_this_load = 0;
 382         int max_loaded = 0, min_loaded = 0;
 383         int load;
 384         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 385         int selected_irq;
 386         int tmp_loaded, first_attempt = 1;
 387         unsigned long tmp_cpu_irq;
 388         unsigned long imbalance = 0;
 389         cpumask_t allowed_mask, target_cpu_mask, tmp;
 390
 391         for_each_possible_cpu(i) {
 392                 int package_index;
 393                 CPU_IRQ(i) = 0;
 394                 if (!cpu_online(i))
 395                         continue;
 396                 package_index = CPU_TO_PACKAGEINDEX(i);
 397                 for (j = 0; j < NR_IRQS; j++) {
 398                         unsigned long value_now, delta;
 399                         /* Is this an active IRQ? */
 400                         if (!irq_desc[j].action)
 401                                 continue;
 402                         if ( package_index == i )
 403                                 IRQ_DELTA(package_index,j) = 0;
 404                         /* Determine the total count per processor per IRQ */
 405                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 406
 407                         /* Determine the activity per processor per IRQ */
 408                         delta = value_now - LAST_CPU_IRQ(i,j);
 409
 410                         /* Update last_cpu_irq[][] for the next time */
 411                         LAST_CPU_IRQ(i,j) = value_now;
 412
 413                         /* Ignore IRQs whose rate is less than the clock */
 414                         if (delta < useful_load_threshold)
 415                                 continue;
 416                         /* update the load for the processor or package total */
 417                         IRQ_DELTA(package_index,j) += delta;
 418
 419                         /* Keep track of the higher numbered sibling as well */
 420                         if (i != package_index)
 421                                 CPU_IRQ(i) += delta;
 422                         /*
 423                          * We have sibling A and sibling B in the package
 424                          *
 425                          * cpu_irq[A] = load for cpu A + load for cpu B
 426                          * cpu_irq[B] = load for cpu B
 427                          */
 428                         CPU_IRQ(package_index) += delta;
 429                 }
 430         }
 431         /* Find the least loaded processor package */
 432         for_each_online_cpu(i) {
 433                 if (i != CPU_TO_PACKAGEINDEX(i))
 434                         continue;
 435                 if (min_cpu_irq > CPU_IRQ(i)) {
 436                         min_cpu_irq = CPU_IRQ(i);
 437                         min_loaded = i;
 438                 }
 439         }
 440         max_cpu_irq = ULONG_MAX;
 441
 442 tryanothercpu:
 443         /* Look for heaviest loaded processor.
 444          * We may come back to get the next heaviest loaded processor.
 445          * Skip processors with trivial loads.
 446          */
 447         tmp_cpu_irq = 0;
 448         tmp_loaded = -1;
 449         for_each_online_cpu(i) {
 450                 if (i != CPU_TO_PACKAGEINDEX(i))
 451                         continue;
 452                 if (max_cpu_irq <= CPU_IRQ(i))
 453                         continue;
 454                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 455                         tmp_cpu_irq = CPU_IRQ(i);
 456                         tmp_loaded = i;
 457                 }
 458         }
 459
 460         if (tmp_loaded == -1) {
 461          /* In the case of small number of heavy interrupt sources,
 462           * loading some of the cpus too much. We use Ingo's original
 463           * approach to rotate them around.
 464           */
 465                 if (!first_attempt && imbalance >= useful_load_threshold) {
 466                         rotate_irqs_among_cpus(useful_load_threshold);
 467                         return;
 468                 }
 469                 goto not_worth_the_effort;
 470         }
 471
 472         first_attempt = 0;              /* heaviest search */
 473         max_cpu_irq = tmp_cpu_irq;      /* load */
 474         max_loaded = tmp_loaded;        /* processor */
 475         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 476
 477         Dprintk("max_loaded cpu = %d\n", max_loaded);
 478         Dprintk("min_loaded cpu = %d\n", min_loaded);
 479         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 480         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 481         Dprintk("load imbalance = %lu\n", imbalance);
 482
 483         /* if imbalance is less than approx 10% of max load, then
 484          * observe diminishing returns action. - quit
 485          */
 486         if (imbalance < (max_cpu_irq >> 3)) {
 487                 Dprintk("Imbalance too trivial\n");
 488                 goto not_worth_the_effort;
 489         }
 490
 491 tryanotherirq:
 492         /* if we select an IRQ to move that can't go where we want, then
 493          * see if there is another one to try.
 494          */
 495         move_this_load = 0;
 496         selected_irq = -1;
 497         for (j = 0; j < NR_IRQS; j++) {
 498                 /* Is this an active IRQ? */
 499                 if (!irq_desc[j].action)
 500                         continue;
 501                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 502                         continue;
 503                 /* Try to find the IRQ that is closest to the imbalance
 504                  * without going over.
 505                  */
 506                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 507                         move_this_load = IRQ_DELTA(max_loaded,j);
 508                         selected_irq = j;
 509                 }
 510         }
 511         if (selected_irq == -1) {
 512                 goto tryanothercpu;
 513         }
 514
 515         imbalance = move_this_load;
 516
 517         /* For physical_balance case, we accumlated both load
 518          * values in the one of the siblings cpu_irq[],
 519          * to use the same code for physical and logical processors
 520          * as much as possible.
 521          *
 522          * NOTE: the cpu_irq[] array holds the sum of the load for
 523          * sibling A and sibling B in the slot for the lowest numbered
 524          * sibling (A), _AND_ the load for sibling B in the slot for
 525          * the higher numbered sibling.
 526          *
 527          * We seek the least loaded sibling by making the comparison
 528          * (A+B)/2 vs B
 529          */
 530         load = CPU_IRQ(min_loaded) >> 1;
 531         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 532                 if (load > CPU_IRQ(j)) {
 533                         /* This won't change cpu_sibling_map[min_loaded] */
 534                         load = CPU_IRQ(j);
 535                         min_loaded = j;
 536                 }
 537         }
 538
 539         cpus_and(allowed_mask,
 540                 cpu_online_map,
 541                 balance_irq_affinity[selected_irq]);
 542         target_cpu_mask = cpumask_of_cpu(min_loaded);
 543         cpus_and(tmp, target_cpu_mask, allowed_mask);
 544
 545         if (!cpus_empty(tmp)) {
 546
 547                 Dprintk("irq = %d moved to cpu = %d\n",
 548                                 selected_irq, min_loaded);
 549                 /* mark for change destination */
 550                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 551
 552                 /* Since we made a change, come back sooner to
 553                  * check for more variation.
 554                  */
 555                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 556                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 557                 return;
 558         }
 559         goto tryanotherirq;
 560
 561 not_worth_the_effort:
 562         /*
 563          * if we did not find an IRQ to move, then adjust the time interval
 564          * upward
 565          */
 566         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 567                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 568         Dprintk("IRQ worth rotating not found\n");
 569         return;
 570 }
 571
 572 static int balanced_irq(void *unused)
 573 {
 574         int i;
 575         unsigned long prev_balance_time = jiffies;
 576         long time_remaining = balanced_irq_interval;
 577
 578         daemonize("kirqd");
 579
 580         /* push everything to CPU 0 to give us a starting point.  */
 581         for (i = 0 ; i < NR_IRQS ; i++) {
 582                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
 583                 set_pending_irq(i, cpumask_of_cpu(0));
 584         }
 585
 586         for ( ; ; ) {
 587                 time_remaining = schedule_timeout_interruptible(time_remaining);
 588                 try_to_freeze();
 589                 if (time_after(jiffies,
 590                                 prev_balance_time+balanced_irq_interval)) {
 591                         preempt_disable();
 592                         do_irq_balance();
 593                         prev_balance_time = jiffies;
 594                         time_remaining = balanced_irq_interval;
 595                         preempt_enable();
 596                 }
 597         }
 598         return 0;
 599 }
 600
 601 static int __init balanced_irq_init(void)
 602 {
 603         int i;
 604         struct cpuinfo_x86 *c;
 605         cpumask_t tmp;
 606
 607         cpus_shift_right(tmp, cpu_online_map, 2);
 608         c = &boot_cpu_data;
 609         /* When not overwritten by the command line ask subarchitecture. */
 610         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 611                 irqbalance_disabled = NO_BALANCE_IRQ;
 612         if (irqbalance_disabled)
 613                 return 0;
 614
 615          /* disable irqbalance completely if there is only one processor online */
 616         if (num_online_cpus() < 2) {
 617                 irqbalance_disabled = 1;
 618                 return 0;
 619         }
 620         /*
 621          * Enable physical balance only if more than 1 physical processor
 622          * is present
 623          */
 624         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 625                 physical_balance = 1;
 626
 627         for_each_online_cpu(i) {
 628                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 629                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 630                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 631                         printk(KERN_ERR "balanced_irq_init: out of memory");
 632                         goto failed;
 633                 }
 634                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 635                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 636         }
 637
 638         printk(KERN_INFO "Starting balanced_irq\n");
 639         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 640                 return 0;
 641         else
 642                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 643 failed:
 644         for_each_possible_cpu(i) {
 645                 kfree(irq_cpu_data[i].irq_delta);
 646                 irq_cpu_data[i].irq_delta = NULL;
 647                 kfree(irq_cpu_data[i].last_irq);
 648                 irq_cpu_data[i].last_irq = NULL;
 649         }
 650         return 0;
 651 }
 652
 653 int __init irqbalance_disable(char *str)
 654 {
 655         irqbalance_disabled = 1;
 656         return 1;
 657 }
 658
 659 __setup("noirqbalance", irqbalance_disable);
 660
 661 late_initcall(balanced_irq_init);
 662 #endif /* CONFIG_IRQBALANCE */
 663 #endif /* CONFIG_SMP */
 664
 665 #ifndef CONFIG_SMP
 666 void fastcall send_IPI_self(int vector)
 667 {
 668         unsigned int cfg;
 669
 670         /*
 671          * Wait for idle.
 672          */
 673         apic_wait_icr_idle();
 674         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 675         /*
 676          * Send the IPI. The write to APIC_ICR fires this off.
 677          */
 678         apic_write_around(APIC_ICR, cfg);
 679 }
 680 #endif /* !CONFIG_SMP */
 681
 682
 683 /*
 684  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 685  * specific CPU-side IRQs.
 686  */
 687
 688 #define MAX_PIRQS 8
 689 static int pirq_entries [MAX_PIRQS];
 690 static int pirqs_enabled;
 691 int skip_ioapic_setup;
 692
 693 static int __init ioapic_setup(char *str)
 694 {
 695         skip_ioapic_setup = 1;
 696         return 1;
 697 }
 698
 699 __setup("noapic", ioapic_setup);
 700
 701 static int __init ioapic_pirq_setup(char *str)
 702 {
 703         int i, max;
 704         int ints[MAX_PIRQS+1];
 705
 706         get_options(str, ARRAY_SIZE(ints), ints);
 707
 708         for (i = 0; i < MAX_PIRQS; i++)
 709                 pirq_entries[i] = -1;
 710
 711         pirqs_enabled = 1;
 712         apic_printk(APIC_VERBOSE, KERN_INFO
 713                         "PIRQ redirection, working around broken MP-BIOS.\n");
 714         max = MAX_PIRQS;
 715         if (ints[0] < MAX_PIRQS)
 716                 max = ints[0];
 717
 718         for (i = 0; i < max; i++) {
 719                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 720                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 721                 /*
 722                  * PIRQs are mapped upside down, usually.
 723                  */
 724                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 725         }
 726         return 1;
 727 }
 728
 729 __setup("pirq=", ioapic_pirq_setup);
 730
 731 /*
 732  * Find the IRQ entry number of a certain pin.
 733  */
 734 static int find_irq_entry(int apic, int pin, int type)
 735 {
 736         int i;
 737
 738         for (i = 0; i < mp_irq_entries; i++)
 739                 if (mp_irqs[i].mpc_irqtype == type &&
 740                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 741                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 742                     mp_irqs[i].mpc_dstirq == pin)
 743                         return i;
 744
 745         return -1;
 746 }
 747
 748 /*
 749  * Find the pin to which IRQ[irq] (ISA) is connected
 750  */
 751 static int __init find_isa_irq_pin(int irq, int type)
 752 {
 753         int i;
 754
 755         for (i = 0; i < mp_irq_entries; i++) {
 756                 int lbus = mp_irqs[i].mpc_srcbus;
 757
 758                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 759                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 760                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 761                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 762                     ) &&
 763                     (mp_irqs[i].mpc_irqtype == type) &&
 764                     (mp_irqs[i].mpc_srcbusirq == irq))
 765
 766                         return mp_irqs[i].mpc_dstirq;
 767         }
 768         return -1;
 769 }
 770
 771 static int __init find_isa_irq_apic(int irq, int type)
 772 {
 773         int i;
 774
 775         for (i = 0; i < mp_irq_entries; i++) {
 776                 int lbus = mp_irqs[i].mpc_srcbus;
 777
 778                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 779                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 780                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 781                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 782                     ) &&
 783                     (mp_irqs[i].mpc_irqtype == type) &&
 784                     (mp_irqs[i].mpc_srcbusirq == irq))
 785                         break;
 786         }
 787         if (i < mp_irq_entries) {
 788                 int apic;
 789                 for(apic = 0; apic < nr_ioapics; apic++) {
 790                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 791                                 return apic;
 792                 }
 793         }
 794
 795         return -1;
 796 }
 797
 798 /*
 799  * Find a specific PCI IRQ entry.
 800  * Not an __init, possibly needed by modules
 801  */
 802 static int pin_2_irq(int idx, int apic, int pin);
 803
 804 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 805 {
 806         int apic, i, best_guess = -1;
 807
 808         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 809                 "slot:%d, pin:%d.\n", bus, slot, pin);
 810         if (mp_bus_id_to_pci_bus[bus] == -1) {
 811                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 812                 return -1;
 813         }
 814         for (i = 0; i < mp_irq_entries; i++) {
 815                 int lbus = mp_irqs[i].mpc_srcbus;
 816
 817                 for (apic = 0; apic < nr_ioapics; apic++)
 818                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 819                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 820                                 break;
 821
 822                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 823                     !mp_irqs[i].mpc_irqtype &&
 824                     (bus == lbus) &&
 825                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 826                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 827
 828                         if (!(apic || IO_APIC_IRQ(irq)))
 829                                 continue;
 830
 831                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 832                                 return irq;
 833                         /*
 834                          * Use the first all-but-pin matching entry as a
 835                          * best-guess fuzzy result for broken mptables.
 836                          */
 837                         if (best_guess < 0)
 838                                 best_guess = irq;
 839                 }
 840         }
 841         return best_guess;
 842 }
 843 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 844
 845 /*
 846  * This function currently is only a helper for the i386 smp boot process where
 847  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 848  * so mask in all cases should simply be TARGET_CPUS
 849  */
 850 #ifdef CONFIG_SMP
 851 void __init setup_ioapic_dest(void)
 852 {
 853         int pin, ioapic, irq, irq_entry;
 854
 855         if (skip_ioapic_setup == 1)
 856                 return;
 857
 858         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 859                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 860                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 861                         if (irq_entry == -1)
 862                                 continue;
 863                         irq = pin_2_irq(irq_entry, ioapic, pin);
 864                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 865                 }
 866
 867         }
 868 }
 869 #endif
 870
 871 /*
 872  * EISA Edge/Level control register, ELCR
 873  */
 874 static int EISA_ELCR(unsigned int irq)
 875 {
 876         if (irq < 16) {
 877                 unsigned int port = 0x4d0 + (irq >> 3);
 878                 return (inb(port) >> (irq & 7)) & 1;
 879         }
 880         apic_printk(APIC_VERBOSE, KERN_INFO
 881                         "Broken MPtable reports ISA irq %d\n", irq);
 882         return 0;
 883 }
 884
 885 /* EISA interrupts are always polarity zero and can be edge or level
 886  * trigger depending on the ELCR value.  If an interrupt is listed as
 887  * EISA conforming in the MP table, that means its trigger type must
 888  * be read in from the ELCR */
 889
 890 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 891 #define default_EISA_polarity(idx)      (0)
 892
 893 /* ISA interrupts are always polarity zero edge triggered,
 894  * when listed as conforming in the MP table. */
 895
 896 #define default_ISA_trigger(idx)        (0)
 897 #define default_ISA_polarity(idx)       (0)
 898
 899 /* PCI interrupts are always polarity one level triggered,
 900  * when listed as conforming in the MP table. */
 901
 902 #define default_PCI_trigger(idx)        (1)
 903 #define default_PCI_polarity(idx)       (1)
 904
 905 /* MCA interrupts are always polarity zero level triggered,
 906  * when listed as conforming in the MP table. */
 907
 908 #define default_MCA_trigger(idx)        (1)
 909 #define default_MCA_polarity(idx)       (0)
 910
 911 /* NEC98 interrupts are always polarity zero edge triggered,
 912  * when listed as conforming in the MP table. */
 913
 914 #define default_NEC98_trigger(idx)     (0)
 915 #define default_NEC98_polarity(idx)    (0)
 916
 917 static int __init MPBIOS_polarity(int idx)
 918 {
 919         int bus = mp_irqs[idx].mpc_srcbus;
 920         int polarity;
 921
 922         /*
 923          * Determine IRQ line polarity (high active or low active):
 924          */
 925         switch (mp_irqs[idx].mpc_irqflag & 3)
 926         {
 927                 case 0: /* conforms, ie. bus-type dependent polarity */
 928                 {
 929                         switch (mp_bus_id_to_type[bus])
 930                         {
 931                                 case MP_BUS_ISA: /* ISA pin */
 932                                 {
 933                                         polarity = default_ISA_polarity(idx);
 934                                         break;
 935                                 }
 936                                 case MP_BUS_EISA: /* EISA pin */
 937                                 {
 938                                         polarity = default_EISA_polarity(idx);
 939                                         break;
 940                                 }
 941                                 case MP_BUS_PCI: /* PCI pin */
 942                                 {
 943                                         polarity = default_PCI_polarity(idx);
 944                                         break;
 945                                 }
 946                                 case MP_BUS_MCA: /* MCA pin */
 947                                 {
 948                                         polarity = default_MCA_polarity(idx);
 949                                         break;
 950                                 }
 951                                 case MP_BUS_NEC98: /* NEC 98 pin */
 952                                 {
 953                                         polarity = default_NEC98_polarity(idx);
 954                                         break;
 955                                 }
 956                                 default:
 957                                 {
 958                                         printk(KERN_WARNING "broken BIOS!!\n");
 959                                         polarity = 1;
 960                                         break;
 961                                 }
 962                         }
 963                         break;
 964                 }
 965                 case 1: /* high active */
 966                 {
 967                         polarity = 0;
 968                         break;
 969                 }
 970                 case 2: /* reserved */
 971                 {
 972                         printk(KERN_WARNING "broken BIOS!!\n");
 973                         polarity = 1;
 974                         break;
 975                 }
 976                 case 3: /* low active */
 977                 {
 978                         polarity = 1;
 979                         break;
 980                 }
 981                 default: /* invalid */
 982                 {
 983                         printk(KERN_WARNING "broken BIOS!!\n");
 984                         polarity = 1;
 985                         break;
 986                 }
 987         }
 988         return polarity;
 989 }
 990
 991 static int MPBIOS_trigger(int idx)
 992 {
 993         int bus = mp_irqs[idx].mpc_srcbus;
 994         int trigger;
 995
 996         /*
 997          * Determine IRQ trigger mode (edge or level sensitive):
 998          */
 999         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1000         {
1001                 case 0: /* conforms, ie. bus-type dependent */
1002                 {
1003                         switch (mp_bus_id_to_type[bus])
1004                         {
1005                                 case MP_BUS_ISA: /* ISA pin */
1006                                 {
1007                                         trigger = default_ISA_trigger(idx);
1008                                         break;
1009                                 }
1010                                 case MP_BUS_EISA: /* EISA pin */
1011                                 {
1012                                         trigger = default_EISA_trigger(idx);
1013                                         break;
1014                                 }
1015                                 case MP_BUS_PCI: /* PCI pin */
1016                                 {
1017                                         trigger = default_PCI_trigger(idx);
1018                                         break;
1019                                 }
1020                                 case MP_BUS_MCA: /* MCA pin */
1021                                 {
1022                                         trigger = default_MCA_trigger(idx);
1023                                         break;
1024                                 }
1025                                 case MP_BUS_NEC98: /* NEC 98 pin */
1026                                 {
1027                                         trigger = default_NEC98_trigger(idx);
1028                                         break;
1029                                 }
1030                                 default:
1031                                 {
1032                                         printk(KERN_WARNING "broken BIOS!!\n");
1033                                         trigger = 1;
1034                                         break;
1035                                 }
1036                         }
1037                         break;
1038                 }
1039                 case 1: /* edge */
1040                 {
1041                         trigger = 0;
1042                         break;
1043                 }
1044                 case 2: /* reserved */
1045                 {
1046                         printk(KERN_WARNING "broken BIOS!!\n");
1047                         trigger = 1;
1048                         break;
1049                 }
1050                 case 3: /* level */
1051                 {
1052                         trigger = 1;
1053                         break;
1054                 }
1055                 default: /* invalid */
1056                 {
1057                         printk(KERN_WARNING "broken BIOS!!\n");
1058                         trigger = 0;
1059                         break;
1060                 }
1061         }
1062         return trigger;
1063 }
1064
1065 static inline int irq_polarity(int idx)
1066 {
1067         return MPBIOS_polarity(idx);
1068 }
1069
1070 static inline int irq_trigger(int idx)
1071 {
1072         return MPBIOS_trigger(idx);
1073 }
1074
1075 static int pin_2_irq(int idx, int apic, int pin)
1076 {
1077         int irq, i;
1078         int bus = mp_irqs[idx].mpc_srcbus;
1079
1080         /*
1081          * Debugging check, we are in big trouble if this message pops up!
1082          */
1083         if (mp_irqs[idx].mpc_dstirq != pin)
1084                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1085
1086         switch (mp_bus_id_to_type[bus])
1087         {
1088                 case MP_BUS_ISA: /* ISA pin */
1089                 case MP_BUS_EISA:
1090                 case MP_BUS_MCA:
1091                 case MP_BUS_NEC98:
1092                 {
1093                         irq = mp_irqs[idx].mpc_srcbusirq;
1094                         break;
1095                 }
1096                 case MP_BUS_PCI: /* PCI pin */
1097                 {
1098                         /*
1099                          * PCI IRQs are mapped in order
1100                          */
1101                         i = irq = 0;
1102                         while (i < apic)
1103                                 irq += nr_ioapic_registers[i++];
1104                         irq += pin;
1105
1106                         /*
1107                          * For MPS mode, so far only needed by ES7000 platform
1108                          */
1109                         if (ioapic_renumber_irq)
1110                                 irq = ioapic_renumber_irq(apic, irq);
1111
1112                         break;
1113                 }
1114                 default:
1115                 {
1116                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1117                         irq = 0;
1118                         break;
1119                 }
1120         }
1121
1122         /*
1123          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1124          */
1125         if ((pin >= 16) && (pin <= 23)) {
1126                 if (pirq_entries[pin-16] != -1) {
1127                         if (!pirq_entries[pin-16]) {
1128                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1129                                                 "disabling PIRQ%d\n", pin-16);
1130                         } else {
1131                                 irq = pirq_entries[pin-16];
1132                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1133                                                 "using PIRQ%d -> IRQ %d\n",
1134                                                 pin-16, irq);
1135                         }
1136                 }
1137         }
1138         return irq;
1139 }
1140
1141 static inline int IO_APIC_irq_trigger(int irq)
1142 {
1143         int apic, idx, pin;
1144
1145         for (apic = 0; apic < nr_ioapics; apic++) {
1146                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1147                         idx = find_irq_entry(apic,pin,mp_INT);
1148                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1149                                 return irq_trigger(idx);
1150                 }
1151         }
1152         /*
1153          * nonexistent IRQs are edge default
1154          */
1155         return 0;
1156 }
1157
1158 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1159 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1160
1161 int assign_irq_vector(int irq)
1162 {
1163         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1164
1165         BUG_ON(irq >= NR_IRQ_VECTORS);
1166         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1167                 return IO_APIC_VECTOR(irq);
1168 next:
1169         current_vector += 8;
1170         if (current_vector == SYSCALL_VECTOR)
1171                 goto next;
1172
1173         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1174                 offset++;
1175                 if (!(offset%8))
1176                         return -ENOSPC;
1177                 current_vector = FIRST_DEVICE_VECTOR + offset;
1178         }
1179
1180         vector_irq[current_vector] = irq;
1181         if (irq != AUTO_ASSIGN)
1182                 IO_APIC_VECTOR(irq) = current_vector;
1183
1184         return current_vector;
1185 }
1186
1187 static struct hw_interrupt_type ioapic_level_type;
1188 static struct hw_interrupt_type ioapic_edge_type;
1189
1190 #define IOAPIC_AUTO     -1
1191 #define IOAPIC_EDGE     0
1192 #define IOAPIC_LEVEL    1
1193
1194 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1195 {
1196         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1197                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1198                                 trigger == IOAPIC_LEVEL)
1199                         irq_desc[vector].handler = &ioapic_level_type;
1200                 else
1201                         irq_desc[vector].handler = &ioapic_edge_type;
1202                 set_intr_gate(vector, interrupt[vector]);
1203         } else  {
1204                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1205                                 trigger == IOAPIC_LEVEL)
1206                         irq_desc[irq].handler = &ioapic_level_type;
1207                 else
1208                         irq_desc[irq].handler = &ioapic_edge_type;
1209                 set_intr_gate(vector, interrupt[irq]);
1210         }
1211 }
1212
1213 static void __init setup_IO_APIC_irqs(void)
1214 {
1215         struct IO_APIC_route_entry entry;
1216         int apic, pin, idx, irq, first_notcon = 1, vector;
1217         unsigned long flags;
1218
1219         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1220
1221         for (apic = 0; apic < nr_ioapics; apic++) {
1222         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1223
1224                 /*
1225                  * add it to the IO-APIC irq-routing table:
1226                  */
1227                 memset(&entry,0,sizeof(entry));
1228
1229                 entry.delivery_mode = INT_DELIVERY_MODE;
1230                 entry.dest_mode = INT_DEST_MODE;
1231                 entry.mask = 0;                         /* enable IRQ */
1232                 entry.dest.logical.logical_dest =
1233                                         cpu_mask_to_apicid(TARGET_CPUS);
1234
1235                 idx = find_irq_entry(apic,pin,mp_INT);
1236                 if (idx == -1) {
1237                         if (first_notcon) {
1238                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1239                                                 " IO-APIC (apicid-pin) %d-%d",
1240                                                 mp_ioapics[apic].mpc_apicid,
1241                                                 pin);
1242                                 first_notcon = 0;
1243                         } else
1244                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1245                                         mp_ioapics[apic].mpc_apicid, pin);
1246                         continue;
1247                 }
1248
1249                 entry.trigger = irq_trigger(idx);
1250                 entry.polarity = irq_polarity(idx);
1251
1252                 if (irq_trigger(idx)) {
1253                         entry.trigger = 1;
1254                         entry.mask = 1;
1255                 }
1256
1257                 irq = pin_2_irq(idx, apic, pin);
1258                 /*
1259                  * skip adding the timer int on secondary nodes, which causes
1260                  * a small but painful rift in the time-space continuum
1261                  */
1262                 if (multi_timer_check(apic, irq))
1263                         continue;
1264                 else
1265                         add_pin_to_irq(irq, apic, pin);
1266
1267                 if (!apic && !IO_APIC_IRQ(irq))
1268                         continue;
1269
1270                 if (IO_APIC_IRQ(irq)) {
1271                         vector = assign_irq_vector(irq);
1272                         entry.vector = vector;
1273                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1274
1275                         if (!apic && (irq < 16))
1276                                 disable_8259A_irq(irq);
1277                 }
1278                 spin_lock_irqsave(&ioapic_lock, flags);
1279                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1280                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1281                 set_native_irq_info(irq, TARGET_CPUS);
1282                 spin_unlock_irqrestore(&ioapic_lock, flags);
1283         }
1284         }
1285
1286         if (!first_notcon)
1287                 apic_printk(APIC_VERBOSE, " not connected.\n");
1288 }
1289
1290 /*
1291  * Set up the 8259A-master output pin:
1292  */
1293 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1294 {
1295         struct IO_APIC_route_entry entry;
1296         unsigned long flags;
1297
1298         memset(&entry,0,sizeof(entry));
1299
1300         disable_8259A_irq(0);
1301
1302         /* mask LVT0 */
1303         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1304
1305         /*
1306          * We use logical delivery to get the timer IRQ
1307          * to the first CPU.
1308          */
1309         entry.dest_mode = INT_DEST_MODE;
1310         entry.mask = 0;                                 /* unmask IRQ now */
1311         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1312         entry.delivery_mode = INT_DELIVERY_MODE;
1313         entry.polarity = 0;
1314         entry.trigger = 0;
1315         entry.vector = vector;
1316
1317         /*
1318          * The timer IRQ doesn't have to know that behind the
1319          * scene we have a 8259A-master in AEOI mode ...
1320          */
1321         irq_desc[0].handler = &ioapic_edge_type;
1322
1323         /*
1324          * Add it to the IO-APIC irq-routing table:
1325          */
1326         spin_lock_irqsave(&ioapic_lock, flags);
1327         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1328         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1329         spin_unlock_irqrestore(&ioapic_lock, flags);
1330
1331         enable_8259A_irq(0);
1332 }
1333
1334 static inline void UNEXPECTED_IO_APIC(void)
1335 {
1336 }
1337
1338 void __init print_IO_APIC(void)
1339 {
1340         int apic, i;
1341         union IO_APIC_reg_00 reg_00;
1342         union IO_APIC_reg_01 reg_01;
1343         union IO_APIC_reg_02 reg_02;
1344         union IO_APIC_reg_03 reg_03;
1345         unsigned long flags;
1346
1347         if (apic_verbosity == APIC_QUIET)
1348                 return;
1349
1350         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1351         for (i = 0; i < nr_ioapics; i++)
1352                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1353                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1354
1355         /*
1356          * We are a bit conservative about what we expect.  We have to
1357          * know about every hardware change ASAP.
1358          */
1359         printk(KERN_INFO "testing the IO APIC.......................\n");
1360
1361         for (apic = 0; apic < nr_ioapics; apic++) {
1362
1363         spin_lock_irqsave(&ioapic_lock, flags);
1364         reg_00.raw = io_apic_read(apic, 0);
1365         reg_01.raw = io_apic_read(apic, 1);
1366         if (reg_01.bits.version >= 0x10)
1367                 reg_02.raw = io_apic_read(apic, 2);
1368         if (reg_01.bits.version >= 0x20)
1369                 reg_03.raw = io_apic_read(apic, 3);
1370         spin_unlock_irqrestore(&ioapic_lock, flags);
1371
1372         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1373         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1374         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1375         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1376         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1377         if (reg_00.bits.ID >= get_physical_broadcast())
1378                 UNEXPECTED_IO_APIC();
1379         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1380                 UNEXPECTED_IO_APIC();
1381
1382         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1383         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1384         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1385                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1386                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1387                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1388                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1389                 (reg_01.bits.entries != 0x2E) &&
1390                 (reg_01.bits.entries != 0x3F)
1391         )
1392                 UNEXPECTED_IO_APIC();
1393
1394         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1395         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1396         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1397                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1398                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1399                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1400                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1401         )
1402                 UNEXPECTED_IO_APIC();
1403         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1404                 UNEXPECTED_IO_APIC();
1405
1406         /*
1407          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1408          * but the value of reg_02 is read as the previous read register
1409          * value, so ignore it if reg_02 == reg_01.
1410          */
1411         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1412                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1413                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1414                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1415                         UNEXPECTED_IO_APIC();
1416         }
1417
1418         /*
1419          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1420          * or reg_03, but the value of reg_0[23] is read as the previous read
1421          * register value, so ignore it if reg_03 == reg_0[12].
1422          */
1423         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1424             reg_03.raw != reg_01.raw) {
1425                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1426                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1427                 if (reg_03.bits.__reserved_1)
1428                         UNEXPECTED_IO_APIC();
1429         }
1430
1431         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1432
1433         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1434                           " Stat Dest Deli Vect:   \n");
1435
1436         for (i = 0; i <= reg_01.bits.entries; i++) {
1437                 struct IO_APIC_route_entry entry;
1438
1439                 spin_lock_irqsave(&ioapic_lock, flags);
1440                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1441                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1442                 spin_unlock_irqrestore(&ioapic_lock, flags);
1443
1444                 printk(KERN_DEBUG " %02x %03X %02X  ",
1445                         i,
1446                         entry.dest.logical.logical_dest,
1447                         entry.dest.physical.physical_dest
1448                 );
1449
1450                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1451                         entry.mask,
1452                         entry.trigger,
1453                         entry.irr,
1454                         entry.polarity,
1455                         entry.delivery_status,
1456                         entry.dest_mode,
1457                         entry.delivery_mode,
1458                         entry.vector
1459                 );
1460         }
1461         }
1462         if (use_pci_vector())
1463                 printk(KERN_INFO "Using vector-based indexing\n");
1464         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1465         for (i = 0; i < NR_IRQS; i++) {
1466                 struct irq_pin_list *entry = irq_2_pin + i;
1467                 if (entry->pin < 0)
1468                         continue;
1469                 if (use_pci_vector() && !platform_legacy_irq(i))
1470                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1471                 else
1472                         printk(KERN_DEBUG "IRQ%d ", i);
1473                 for (;;) {
1474                         printk("-> %d:%d", entry->apic, entry->pin);
1475                         if (!entry->next)
1476                                 break;
1477                         entry = irq_2_pin + entry->next;
1478                 }
1479                 printk("\n");
1480         }
1481
1482         printk(KERN_INFO ".................................... done.\n");
1483
1484         return;
1485 }
1486
1487 #if 0
1488
1489 static void print_APIC_bitfield (int base)
1490 {
1491         unsigned int v;
1492         int i, j;
1493
1494         if (apic_verbosity == APIC_QUIET)
1495                 return;
1496
1497         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1498         for (i = 0; i < 8; i++) {
1499                 v = apic_read(base + i*0x10);
1500                 for (j = 0; j < 32; j++) {
1501                         if (v & (1<<j))
1502                                 printk("1");
1503                         else
1504                                 printk("0");
1505                 }
1506                 printk("\n");
1507         }
1508 }
1509
1510 void /*__init*/ print_local_APIC(void * dummy)
1511 {
1512         unsigned int v, ver, maxlvt;
1513
1514         if (apic_verbosity == APIC_QUIET)
1515                 return;
1516
1517         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1518                 smp_processor_id(), hard_smp_processor_id());
1519         v = apic_read(APIC_ID);
1520         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1521         v = apic_read(APIC_LVR);
1522         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1523         ver = GET_APIC_VERSION(v);
1524         maxlvt = get_maxlvt();
1525
1526         v = apic_read(APIC_TASKPRI);
1527         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1528
1529         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1530                 v = apic_read(APIC_ARBPRI);
1531                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1532                         v & APIC_ARBPRI_MASK);
1533                 v = apic_read(APIC_PROCPRI);
1534                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1535         }
1536
1537         v = apic_read(APIC_EOI);
1538         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1539         v = apic_read(APIC_RRR);
1540         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1541         v = apic_read(APIC_LDR);
1542         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1543         v = apic_read(APIC_DFR);
1544         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1545         v = apic_read(APIC_SPIV);
1546         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1547
1548         printk(KERN_DEBUG "... APIC ISR field:\n");
1549         print_APIC_bitfield(APIC_ISR);
1550         printk(KERN_DEBUG "... APIC TMR field:\n");
1551         print_APIC_bitfield(APIC_TMR);
1552         printk(KERN_DEBUG "... APIC IRR field:\n");
1553         print_APIC_bitfield(APIC_IRR);
1554
1555         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1556                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1557                         apic_write(APIC_ESR, 0);
1558                 v = apic_read(APIC_ESR);
1559                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1560         }
1561
1562         v = apic_read(APIC_ICR);
1563         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1564         v = apic_read(APIC_ICR2);
1565         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1566
1567         v = apic_read(APIC_LVTT);
1568         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1569
1570         if (maxlvt > 3) {                       /* PC is LVT#4. */
1571                 v = apic_read(APIC_LVTPC);
1572                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1573         }
1574         v = apic_read(APIC_LVT0);
1575         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1576         v = apic_read(APIC_LVT1);
1577         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1578
1579         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1580                 v = apic_read(APIC_LVTERR);
1581                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1582         }
1583
1584         v = apic_read(APIC_TMICT);
1585         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1586         v = apic_read(APIC_TMCCT);
1587         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1588         v = apic_read(APIC_TDCR);
1589         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1590         printk("\n");
1591 }
1592
1593 void print_all_local_APICs (void)
1594 {
1595         on_each_cpu(print_local_APIC, NULL, 1, 1);
1596 }
1597
1598 void /*__init*/ print_PIC(void)
1599 {
1600         unsigned int v;
1601         unsigned long flags;
1602
1603         if (apic_verbosity == APIC_QUIET)
1604                 return;
1605
1606         printk(KERN_DEBUG "\nprinting PIC contents\n");
1607
1608         spin_lock_irqsave(&i8259A_lock, flags);
1609
1610         v = inb(0xa1) << 8 | inb(0x21);
1611         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1612
1613         v = inb(0xa0) << 8 | inb(0x20);
1614         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1615
1616         outb(0x0b,0xa0);
1617         outb(0x0b,0x20);
1618         v = inb(0xa0) << 8 | inb(0x20);
1619         outb(0x0a,0xa0);
1620         outb(0x0a,0x20);
1621
1622         spin_unlock_irqrestore(&i8259A_lock, flags);
1623
1624         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1625
1626         v = inb(0x4d1) << 8 | inb(0x4d0);
1627         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1628 }
1629
1630 #endif  /*  0  */
1631
1632 static void __init enable_IO_APIC(void)
1633 {
1634         union IO_APIC_reg_01 reg_01;
1635         int i8259_apic, i8259_pin;
1636         int i, apic;
1637         unsigned long flags;
1638
1639         for (i = 0; i < PIN_MAP_SIZE; i++) {
1640                 irq_2_pin[i].pin = -1;
1641                 irq_2_pin[i].next = 0;
1642         }
1643         if (!pirqs_enabled)
1644                 for (i = 0; i < MAX_PIRQS; i++)
1645                         pirq_entries[i] = -1;
1646
1647         /*
1648          * The number of IO-APIC IRQ registers (== #pins):
1649          */
1650         for (apic = 0; apic < nr_ioapics; apic++) {
1651                 spin_lock_irqsave(&ioapic_lock, flags);
1652                 reg_01.raw = io_apic_read(apic, 1);
1653                 spin_unlock_irqrestore(&ioapic_lock, flags);
1654                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1655         }
1656         for(apic = 0; apic < nr_ioapics; apic++) {
1657                 int pin;
1658                 /* See if any of the pins is in ExtINT mode */
1659                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1660                         struct IO_APIC_route_entry entry;
1661                         spin_lock_irqsave(&ioapic_lock, flags);
1662                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1663                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1664                         spin_unlock_irqrestore(&ioapic_lock, flags);
1665
1666
1667                         /* If the interrupt line is enabled and in ExtInt mode
1668                          * I have found the pin where the i8259 is connected.
1669                          */
1670                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1671                                 ioapic_i8259.apic = apic;
1672                                 ioapic_i8259.pin  = pin;
1673                                 goto found_i8259;
1674                         }
1675                 }
1676         }
1677  found_i8259:
1678         /* Look to see what if the MP table has reported the ExtINT */
1679         /* If we could not find the appropriate pin by looking at the ioapic
1680          * the i8259 probably is not connected the ioapic but give the
1681          * mptable a chance anyway.
1682          */
1683         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1684         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1685         /* Trust the MP table if nothing is setup in the hardware */
1686         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1687                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1688                 ioapic_i8259.pin  = i8259_pin;
1689                 ioapic_i8259.apic = i8259_apic;
1690         }
1691         /* Complain if the MP table and the hardware disagree */
1692         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1693                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1694         {
1695                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1696         }
1697
1698         /*
1699          * Do not trust the IO-APIC being empty at bootup
1700          */
1701         clear_IO_APIC();
1702 }
1703
1704 /*
1705  * Not an __init, needed by the reboot code
1706  */
1707 void disable_IO_APIC(void)
1708 {
1709         /*
1710          * Clear the IO-APIC before rebooting:
1711          */
1712         clear_IO_APIC();
1713
1714         /*
1715          * If the i8259 is routed through an IOAPIC
1716          * Put that IOAPIC in virtual wire mode
1717          * so legacy interrupts can be delivered.
1718          */
1719         if (ioapic_i8259.pin != -1) {
1720                 struct IO_APIC_route_entry entry;
1721                 unsigned long flags;
1722
1723                 memset(&entry, 0, sizeof(entry));
1724                 entry.mask            = 0; /* Enabled */
1725                 entry.trigger         = 0; /* Edge */
1726                 entry.irr             = 0;
1727                 entry.polarity        = 0; /* High */
1728                 entry.delivery_status = 0;
1729                 entry.dest_mode       = 0; /* Physical */
1730                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1731                 entry.vector          = 0;
1732                 entry.dest.physical.physical_dest =
1733                                         GET_APIC_ID(apic_read(APIC_ID));
1734
1735                 /*
1736                  * Add it to the IO-APIC irq-routing table:
1737                  */
1738                 spin_lock_irqsave(&ioapic_lock, flags);
1739                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1740                         *(((int *)&entry)+1));
1741                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1742                         *(((int *)&entry)+0));
1743                 spin_unlock_irqrestore(&ioapic_lock, flags);
1744         }
1745         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1746 }
1747
1748 /*
1749  * function to set the IO-APIC physical IDs based on the
1750  * values stored in the MPC table.
1751  *
1752  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1753  */
1754
1755 #ifndef CONFIG_X86_NUMAQ
1756 static void __init setup_ioapic_ids_from_mpc(void)
1757 {
1758         union IO_APIC_reg_00 reg_00;
1759         physid_mask_t phys_id_present_map;
1760         int apic;
1761         int i;
1762         unsigned char old_id;
1763         unsigned long flags;
1764
1765         /*
1766          * Don't check I/O APIC IDs for xAPIC systems.  They have
1767          * no meaning without the serial APIC bus.
1768          */
1769         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1770                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1771                 return;
1772         /*
1773          * This is broken; anything with a real cpu count has to
1774          * circumvent this idiocy regardless.
1775          */
1776         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1777
1778         /*
1779          * Set the IOAPIC ID to the value stored in the MPC table.
1780          */
1781         for (apic = 0; apic < nr_ioapics; apic++) {
1782
1783                 /* Read the register 0 value */
1784                 spin_lock_irqsave(&ioapic_lock, flags);
1785                 reg_00.raw = io_apic_read(apic, 0);
1786                 spin_unlock_irqrestore(&ioapic_lock, flags);
1787
1788                 old_id = mp_ioapics[apic].mpc_apicid;
1789
1790                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1791                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1792                                 apic, mp_ioapics[apic].mpc_apicid);
1793                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1794                                 reg_00.bits.ID);
1795                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1796                 }
1797
1798                 /*
1799                  * Sanity check, is the ID really free? Every APIC in a
1800                  * system must have a unique ID or we get lots of nice
1801                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1802                  */
1803                 if (check_apicid_used(phys_id_present_map,
1804                                         mp_ioapics[apic].mpc_apicid)) {
1805                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1806                                 apic, mp_ioapics[apic].mpc_apicid);
1807                         for (i = 0; i < get_physical_broadcast(); i++)
1808                                 if (!physid_isset(i, phys_id_present_map))
1809                                         break;
1810                         if (i >= get_physical_broadcast())
1811                                 panic("Max APIC ID exceeded!\n");
1812                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1813                                 i);
1814                         physid_set(i, phys_id_present_map);
1815                         mp_ioapics[apic].mpc_apicid = i;
1816                 } else {
1817                         physid_mask_t tmp;
1818                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1819                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1820                                         "phys_id_present_map\n",
1821                                         mp_ioapics[apic].mpc_apicid);
1822                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1823                 }
1824
1825
1826                 /*
1827                  * We need to adjust the IRQ routing table
1828                  * if the ID changed.
1829                  */
1830                 if (old_id != mp_ioapics[apic].mpc_apicid)
1831                         for (i = 0; i < mp_irq_entries; i++)
1832                                 if (mp_irqs[i].mpc_dstapic == old_id)
1833                                         mp_irqs[i].mpc_dstapic
1834                                                 = mp_ioapics[apic].mpc_apicid;
1835
1836                 /*
1837                  * Read the right value from the MPC table and
1838                  * write it into the ID register.
1839                  */
1840                 apic_printk(APIC_VERBOSE, KERN_INFO
1841                         "...changing IO-APIC physical APIC ID to %d ...",
1842                         mp_ioapics[apic].mpc_apicid);
1843
1844                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1845                 spin_lock_irqsave(&ioapic_lock, flags);
1846                 io_apic_write(apic, 0, reg_00.raw);
1847                 spin_unlock_irqrestore(&ioapic_lock, flags);
1848
1849                 /*
1850                  * Sanity check
1851                  */
1852                 spin_lock_irqsave(&ioapic_lock, flags);
1853                 reg_00.raw = io_apic_read(apic, 0);
1854                 spin_unlock_irqrestore(&ioapic_lock, flags);
1855                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1856                         printk("could not set ID!\n");
1857                 else
1858                         apic_printk(APIC_VERBOSE, " ok.\n");
1859         }
1860 }
1861 #else
1862 static void __init setup_ioapic_ids_from_mpc(void) { }
1863 #endif
1864
1865 /*
1866  * There is a nasty bug in some older SMP boards, their mptable lies
1867  * about the timer IRQ. We do the following to work around the situation:
1868  *
1869  *      - timer IRQ defaults to IO-APIC IRQ
1870  *      - if this function detects that timer IRQs are defunct, then we fall
1871  *        back to ISA timer IRQs
1872  */
1873 static int __init timer_irq_works(void)
1874 {
1875         unsigned long t1 = jiffies;
1876
1877         local_irq_enable();
1878         /* Let ten ticks pass... */
1879         mdelay((10 * 1000) / HZ);
1880
1881         /*
1882          * Expect a few ticks at least, to be sure some possible
1883          * glue logic does not lock up after one or two first
1884          * ticks in a non-ExtINT mode.  Also the local APIC
1885          * might have cached one ExtINT interrupt.  Finally, at
1886          * least one tick may be lost due to delays.
1887          */
1888         if (jiffies - t1 > 4)
1889                 return 1;
1890
1891         return 0;
1892 }
1893
1894 /*
1895  * In the SMP+IOAPIC case it might happen that there are an unspecified
1896  * number of pending IRQ events unhandled. These cases are very rare,
1897  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1898  * better to do it this way as thus we do not have to be aware of
1899  * 'pending' interrupts in the IRQ path, except at this point.
1900  */
1901 /*
1902  * Edge triggered needs to resend any interrupt
1903  * that was delayed but this is now handled in the device
1904  * independent code.
1905  */
1906
1907 /*
1908  * Starting up a edge-triggered IO-APIC interrupt is
1909  * nasty - we need to make sure that we get the edge.
1910  * If it is already asserted for some reason, we need
1911  * return 1 to indicate that is was pending.
1912  *
1913  * This is not complete - we should be able to fake
1914  * an edge even if it isn't on the 8259A...
1915  */
1916 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1917 {
1918         int was_pending = 0;
1919         unsigned long flags;
1920
1921         spin_lock_irqsave(&ioapic_lock, flags);
1922         if (irq < 16) {
1923                 disable_8259A_irq(irq);
1924                 if (i8259A_irq_pending(irq))
1925                         was_pending = 1;
1926         }
1927         __unmask_IO_APIC_irq(irq);
1928         spin_unlock_irqrestore(&ioapic_lock, flags);
1929
1930         return was_pending;
1931 }
1932
1933 /*
1934  * Once we have recorded IRQ_PENDING already, we can mask the
1935  * interrupt for real. This prevents IRQ storms from unhandled
1936  * devices.
1937  */
1938 static void ack_edge_ioapic_irq(unsigned int irq)
1939 {
1940         move_irq(irq);
1941         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1942                                         == (IRQ_PENDING | IRQ_DISABLED))
1943                 mask_IO_APIC_irq(irq);
1944         ack_APIC_irq();
1945 }
1946
1947 /*
1948  * Level triggered interrupts can just be masked,
1949  * and shutting down and starting up the interrupt
1950  * is the same as enabling and disabling them -- except
1951  * with a startup need to return a "was pending" value.
1952  *
1953  * Level triggered interrupts are special because we
1954  * do not touch any IO-APIC register while handling
1955  * them. We ack the APIC in the end-IRQ handler, not
1956  * in the start-IRQ-handler. Protection against reentrance
1957  * from the same interrupt is still provided, both by the
1958  * generic IRQ layer and by the fact that an unacked local
1959  * APIC does not accept IRQs.
1960  */
1961 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1962 {
1963         unmask_IO_APIC_irq(irq);
1964
1965         return 0; /* don't check for pending */
1966 }
1967
1968 static void end_level_ioapic_irq (unsigned int irq)
1969 {
1970         unsigned long v;
1971         int i;
1972
1973         move_irq(irq);
1974 /*
1975  * It appears there is an erratum which affects at least version 0x11
1976  * of I/O APIC (that's the 82093AA and cores integrated into various
1977  * chipsets).  Under certain conditions a level-triggered interrupt is
1978  * erroneously delivered as edge-triggered one but the respective IRR
1979  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1980  * message but it will never arrive and further interrupts are blocked
1981  * from the source.  The exact reason is so far unknown, but the
1982  * phenomenon was observed when two consecutive interrupt requests
1983  * from a given source get delivered to the same CPU and the source is
1984  * temporarily disabled in between.
1985  *
1986  * A workaround is to simulate an EOI message manually.  We achieve it
1987  * by setting the trigger mode to edge and then to level when the edge
1988  * trigger mode gets detected in the TMR of a local APIC for a
1989  * level-triggered interrupt.  We mask the source for the time of the
1990  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1991  * The idea is from Manfred Spraul.  --macro
1992  */
1993         i = IO_APIC_VECTOR(irq);
1994
1995         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1996
1997         ack_APIC_irq();
1998
1999         if (!(v & (1 << (i & 0x1f)))) {
2000                 atomic_inc(&irq_mis_count);
2001                 spin_lock(&ioapic_lock);
2002                 __mask_and_edge_IO_APIC_irq(irq);
2003                 __unmask_and_level_IO_APIC_irq(irq);
2004                 spin_unlock(&ioapic_lock);
2005         }
2006 }
2007
2008 #ifdef CONFIG_PCI_MSI
2009 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2010 {
2011         int irq = vector_to_irq(vector);
2012
2013         return startup_edge_ioapic_irq(irq);
2014 }
2015
2016 static void ack_edge_ioapic_vector(unsigned int vector)
2017 {
2018         int irq = vector_to_irq(vector);
2019
2020         move_native_irq(vector);
2021         ack_edge_ioapic_irq(irq);
2022 }
2023
2024 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2025 {
2026         int irq = vector_to_irq(vector);
2027
2028         return startup_level_ioapic_irq (irq);
2029 }
2030
2031 static void end_level_ioapic_vector (unsigned int vector)
2032 {
2033         int irq = vector_to_irq(vector);
2034
2035         move_native_irq(vector);
2036         end_level_ioapic_irq(irq);
2037 }
2038
2039 static void mask_IO_APIC_vector (unsigned int vector)
2040 {
2041         int irq = vector_to_irq(vector);
2042
2043         mask_IO_APIC_irq(irq);
2044 }
2045
2046 static void unmask_IO_APIC_vector (unsigned int vector)
2047 {
2048         int irq = vector_to_irq(vector);
2049
2050         unmask_IO_APIC_irq(irq);
2051 }
2052
2053 #ifdef CONFIG_SMP
2054 static void set_ioapic_affinity_vector (unsigned int vector,
2055                                         cpumask_t cpu_mask)
2056 {
2057         int irq = vector_to_irq(vector);
2058
2059         set_native_irq_info(vector, cpu_mask);
2060         set_ioapic_affinity_irq(irq, cpu_mask);
2061 }
2062 #endif
2063 #endif
2064
2065 /*
2066  * Level and edge triggered IO-APIC interrupts need different handling,
2067  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2068  * handled with the level-triggered descriptor, but that one has slightly
2069  * more overhead. Level-triggered interrupts cannot be handled with the
2070  * edge-triggered handler, without risking IRQ storms and other ugly
2071  * races.
2072  */
2073 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2074         .typename       = "IO-APIC-edge",
2075         .startup        = startup_edge_ioapic,
2076         .shutdown       = shutdown_edge_ioapic,
2077         .enable         = enable_edge_ioapic,
2078         .disable        = disable_edge_ioapic,
2079         .ack            = ack_edge_ioapic,
2080         .end            = end_edge_ioapic,
2081 #ifdef CONFIG_SMP
2082         .set_affinity   = set_ioapic_affinity,
2083 #endif
2084 };
2085
2086 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2087         .typename       = "IO-APIC-level",
2088         .startup        = startup_level_ioapic,
2089         .shutdown       = shutdown_level_ioapic,
2090         .enable         = enable_level_ioapic,
2091         .disable        = disable_level_ioapic,
2092         .ack            = mask_and_ack_level_ioapic,
2093         .end            = end_level_ioapic,
2094 #ifdef CONFIG_SMP
2095         .set_affinity   = set_ioapic_affinity,
2096 #endif
2097 };
2098
2099 static inline void init_IO_APIC_traps(void)
2100 {
2101         int irq;
2102
2103         /*
2104          * NOTE! The local APIC isn't very good at handling
2105          * multiple interrupts at the same interrupt level.
2106          * As the interrupt level is determined by taking the
2107          * vector number and shifting that right by 4, we
2108          * want to spread these out a bit so that they don't
2109          * all fall in the same interrupt level.
2110          *
2111          * Also, we've got to be careful not to trash gate
2112          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2113          */
2114         for (irq = 0; irq < NR_IRQS ; irq++) {
2115                 int tmp = irq;
2116                 if (use_pci_vector()) {
2117                         if (!platform_legacy_irq(tmp))
2118                                 if ((tmp = vector_to_irq(tmp)) == -1)
2119                                         continue;
2120                 }
2121                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2122                         /*
2123                          * Hmm.. We don't have an entry for this,
2124                          * so default to an old-fashioned 8259
2125                          * interrupt if we can..
2126                          */
2127                         if (irq < 16)
2128                                 make_8259A_irq(irq);
2129                         else
2130                                 /* Strange. Oh, well.. */
2131                                 irq_desc[irq].handler = &no_irq_type;
2132                 }
2133         }
2134 }
2135
2136 static void enable_lapic_irq (unsigned int irq)
2137 {
2138         unsigned long v;
2139
2140         v = apic_read(APIC_LVT0);
2141         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2142 }
2143
2144 static void disable_lapic_irq (unsigned int irq)
2145 {
2146         unsigned long v;
2147
2148         v = apic_read(APIC_LVT0);
2149         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2150 }
2151
2152 static void ack_lapic_irq (unsigned int irq)
2153 {
2154         ack_APIC_irq();
2155 }
2156
2157 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2158
2159 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2160         .typename       = "local-APIC-edge",
2161         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2162         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2163         .enable         = enable_lapic_irq,
2164         .disable        = disable_lapic_irq,
2165         .ack            = ack_lapic_irq,
2166         .end            = end_lapic_irq
2167 };
2168
2169 static void setup_nmi (void)
2170 {
2171         /*
2172          * Dirty trick to enable the NMI watchdog ...
2173          * We put the 8259A master into AEOI mode and
2174          * unmask on all local APICs LVT0 as NMI.
2175          *
2176          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2177          * is from Maciej W. Rozycki - so we do not have to EOI from
2178          * the NMI handler or the timer interrupt.
2179          */
2180         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2181
2182         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2183
2184         apic_printk(APIC_VERBOSE, " done.\n");
2185 }
2186
2187 /*
2188  * This looks a bit hackish but it's about the only one way of sending
2189  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2190  * not support the ExtINT mode, unfortunately.  We need to send these
2191  * cycles as some i82489DX-based boards have glue logic that keeps the
2192  * 8259A interrupt line asserted until INTA.  --macro
2193  */
2194 static inline void unlock_ExtINT_logic(void)
2195 {
2196         int apic, pin, i;
2197         struct IO_APIC_route_entry entry0, entry1;
2198         unsigned char save_control, save_freq_select;
2199         unsigned long flags;
2200
2201         pin  = find_isa_irq_pin(8, mp_INT);
2202         apic = find_isa_irq_apic(8, mp_INT);
2203         if (pin == -1)
2204                 return;
2205
2206         spin_lock_irqsave(&ioapic_lock, flags);
2207         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2208         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2209         spin_unlock_irqrestore(&ioapic_lock, flags);
2210         clear_IO_APIC_pin(apic, pin);
2211
2212         memset(&entry1, 0, sizeof(entry1));
2213
2214         entry1.dest_mode = 0;                   /* physical delivery */
2215         entry1.mask = 0;                        /* unmask IRQ now */
2216         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2217         entry1.delivery_mode = dest_ExtINT;
2218         entry1.polarity = entry0.polarity;
2219         entry1.trigger = 0;
2220         entry1.vector = 0;
2221
2222         spin_lock_irqsave(&ioapic_lock, flags);
2223         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2224         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2225         spin_unlock_irqrestore(&ioapic_lock, flags);
2226
2227         save_control = CMOS_READ(RTC_CONTROL);
2228         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2229         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2230                    RTC_FREQ_SELECT);
2231         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2232
2233         i = 100;
2234         while (i-- > 0) {
2235                 mdelay(10);
2236                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2237                         i -= 10;
2238         }
2239
2240         CMOS_WRITE(save_control, RTC_CONTROL);
2241         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2242         clear_IO_APIC_pin(apic, pin);
2243
2244         spin_lock_irqsave(&ioapic_lock, flags);
2245         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2246         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2247         spin_unlock_irqrestore(&ioapic_lock, flags);
2248 }
2249
2250 int timer_uses_ioapic_pin_0;
2251
2252 /*
2253  * This code may look a bit paranoid, but it's supposed to cooperate with
2254  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2255  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2256  * fanatically on his truly buggy board.
2257  */
2258 static inline void check_timer(void)
2259 {
2260         int apic1, pin1, apic2, pin2;
2261         int vector;
2262
2263         /*
2264          * get/set the timer IRQ vector:
2265          */
2266         disable_8259A_irq(0);
2267         vector = assign_irq_vector(0);
2268         set_intr_gate(vector, interrupt[0]);
2269
2270         /*
2271          * Subtle, code in do_timer_interrupt() expects an AEOI
2272          * mode for the 8259A whenever interrupts are routed
2273          * through I/O APICs.  Also IRQ0 has to be enabled in
2274          * the 8259A which implies the virtual wire has to be
2275          * disabled in the local APIC.
2276          */
2277         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2278         init_8259A(1);
2279         timer_ack = 1;
2280         if (timer_over_8254 > 0)
2281                 enable_8259A_irq(0);
2282
2283         pin1  = find_isa_irq_pin(0, mp_INT);
2284         apic1 = find_isa_irq_apic(0, mp_INT);
2285         pin2  = ioapic_i8259.pin;
2286         apic2 = ioapic_i8259.apic;
2287
2288         if (pin1 == 0)
2289                 timer_uses_ioapic_pin_0 = 1;
2290
2291         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2292                 vector, apic1, pin1, apic2, pin2);
2293
2294         if (pin1 != -1) {
2295                 /*
2296                  * Ok, does IRQ0 through the IOAPIC work?
2297                  */
2298                 unmask_IO_APIC_irq(0);
2299                 if (timer_irq_works()) {
2300                         if (nmi_watchdog == NMI_IO_APIC) {
2301                                 disable_8259A_irq(0);
2302                                 setup_nmi();
2303                                 enable_8259A_irq(0);
2304                         }
2305                         if (disable_timer_pin_1 > 0)
2306                                 clear_IO_APIC_pin(0, pin1);
2307                         return;
2308                 }
2309                 clear_IO_APIC_pin(apic1, pin1);
2310                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2311                                 "IO-APIC\n");
2312         }
2313
2314         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2315         if (pin2 != -1) {
2316                 printk("\n..... (found pin %d) ...", pin2);
2317                 /*
2318                  * legacy devices should be connected to IO APIC #0
2319                  */
2320                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2321                 if (timer_irq_works()) {
2322                         printk("works.\n");
2323                         if (pin1 != -1)
2324                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2325                         else
2326                                 add_pin_to_irq(0, apic2, pin2);
2327                         if (nmi_watchdog == NMI_IO_APIC) {
2328                                 setup_nmi();
2329                         }
2330                         return;
2331                 }
2332                 /*
2333                  * Cleanup, just in case ...
2334                  */
2335                 clear_IO_APIC_pin(apic2, pin2);
2336         }
2337         printk(" failed.\n");
2338
2339         if (nmi_watchdog == NMI_IO_APIC) {
2340                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2341                 nmi_watchdog = 0;
2342         }
2343
2344         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2345
2346         disable_8259A_irq(0);
2347         irq_desc[0].handler = &lapic_irq_type;
2348         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2349         enable_8259A_irq(0);
2350
2351         if (timer_irq_works()) {
2352                 printk(" works.\n");
2353                 return;
2354         }
2355         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2356         printk(" failed.\n");
2357
2358         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2359
2360         timer_ack = 0;
2361         init_8259A(0);
2362         make_8259A_irq(0);
2363         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2364
2365         unlock_ExtINT_logic();
2366
2367         if (timer_irq_works()) {
2368                 printk(" works.\n");
2369                 return;
2370         }
2371         printk(" failed :(.\n");
2372         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2373                 "report.  Then try booting with the 'noapic' option");
2374 }
2375
2376 /*
2377  *
2378  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2379  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2380  *   Linux doesn't really care, as it's not actually used
2381  *   for any interrupt handling anyway.
2382  */
2383 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2384
2385 void __init setup_IO_APIC(void)
2386 {
2387         enable_IO_APIC();
2388
2389         if (acpi_ioapic)
2390                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2391         else
2392                 io_apic_irqs = ~PIC_IRQS;
2393
2394         printk("ENABLING IO-APIC IRQs\n");
2395
2396         /*
2397          * Set up IO-APIC IRQ routing.
2398          */
2399         if (!acpi_ioapic)
2400                 setup_ioapic_ids_from_mpc();
2401         sync_Arb_IDs();
2402         setup_IO_APIC_irqs();
2403         init_IO_APIC_traps();
2404         check_timer();
2405         if (!acpi_ioapic)
2406                 print_IO_APIC();
2407 }
2408
2409 static int __init setup_disable_8254_timer(char *s)
2410 {
2411         timer_over_8254 = -1;
2412         return 1;
2413 }
2414 static int __init setup_enable_8254_timer(char *s)
2415 {
2416         timer_over_8254 = 2;
2417         return 1;
2418 }
2419
2420 __setup("disable_8254_timer", setup_disable_8254_timer);
2421 __setup("enable_8254_timer", setup_enable_8254_timer);
2422
2423 /*
2424  *      Called after all the initialization is done. If we didnt find any
2425  *      APIC bugs then we can allow the modify fast path
2426  */
2427
2428 static int __init io_apic_bug_finalize(void)
2429 {
2430         if(sis_apic_bug == -1)
2431                 sis_apic_bug = 0;
2432         return 0;
2433 }
2434
2435 late_initcall(io_apic_bug_finalize);
2436
2437 struct sysfs_ioapic_data {
2438         struct sys_device dev;
2439         struct IO_APIC_route_entry entry[0];
2440 };
2441 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2442
2443 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2444 {
2445         struct IO_APIC_route_entry *entry;
2446         struct sysfs_ioapic_data *data;
2447         unsigned long flags;
2448         int i;
2449
2450         data = container_of(dev, struct sysfs_ioapic_data, dev);
2451         entry = data->entry;
2452         spin_lock_irqsave(&ioapic_lock, flags);
2453         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2454                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2455                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2456         }
2457         spin_unlock_irqrestore(&ioapic_lock, flags);
2458
2459         return 0;
2460 }
2461
2462 static int ioapic_resume(struct sys_device *dev)
2463 {
2464         struct IO_APIC_route_entry *entry;
2465         struct sysfs_ioapic_data *data;
2466         unsigned long flags;
2467         union IO_APIC_reg_00 reg_00;
2468         int i;
2469
2470         data = container_of(dev, struct sysfs_ioapic_data, dev);
2471         entry = data->entry;
2472
2473         spin_lock_irqsave(&ioapic_lock, flags);
2474         reg_00.raw = io_apic_read(dev->id, 0);
2475         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2476                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2477                 io_apic_write(dev->id, 0, reg_00.raw);
2478         }
2479         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2480                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2481                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2482         }
2483         spin_unlock_irqrestore(&ioapic_lock, flags);
2484
2485         return 0;
2486 }
2487
2488 static struct sysdev_class ioapic_sysdev_class = {
2489         set_kset_name("ioapic"),
2490         .suspend = ioapic_suspend,
2491         .resume = ioapic_resume,
2492 };
2493
2494 static int __init ioapic_init_sysfs(void)
2495 {
2496         struct sys_device * dev;
2497         int i, size, error = 0;
2498
2499         error = sysdev_class_register(&ioapic_sysdev_class);
2500         if (error)
2501                 return error;
2502
2503         for (i = 0; i < nr_ioapics; i++ ) {
2504                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2505                         * sizeof(struct IO_APIC_route_entry);
2506                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2507                 if (!mp_ioapic_data[i]) {
2508                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2509                         continue;
2510                 }
2511                 memset(mp_ioapic_data[i], 0, size);
2512                 dev = &mp_ioapic_data[i]->dev;
2513                 dev->id = i;
2514                 dev->cls = &ioapic_sysdev_class;
2515                 error = sysdev_register(dev);
2516                 if (error) {
2517                         kfree(mp_ioapic_data[i]);
2518                         mp_ioapic_data[i] = NULL;
2519                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2520                         continue;
2521                 }
2522         }
2523
2524         return 0;
2525 }
2526
2527 device_initcall(ioapic_init_sysfs);
2528
2529 /* --------------------------------------------------------------------------
2530                           ACPI-based IOAPIC Configuration
2531    -------------------------------------------------------------------------- */
2532
2533 #ifdef CONFIG_ACPI
2534
2535 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2536 {
2537         union IO_APIC_reg_00 reg_00;
2538         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2539         physid_mask_t tmp;
2540         unsigned long flags;
2541         int i = 0;
2542
2543         /*
2544          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2545          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2546          * supports up to 16 on one shared APIC bus.
2547          *
2548          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2549          *      advantage of new APIC bus architecture.
2550          */
2551
2552         if (physids_empty(apic_id_map))
2553                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2554
2555         spin_lock_irqsave(&ioapic_lock, flags);
2556         reg_00.raw = io_apic_read(ioapic, 0);
2557         spin_unlock_irqrestore(&ioapic_lock, flags);
2558
2559         if (apic_id >= get_physical_broadcast()) {
2560                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2561                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2562                 apic_id = reg_00.bits.ID;
2563         }
2564
2565         /*
2566          * Every APIC in a system must have a unique ID or we get lots of nice
2567          * 'stuck on smp_invalidate_needed IPI wait' messages.
2568          */
2569         if (check_apicid_used(apic_id_map, apic_id)) {
2570
2571                 for (i = 0; i < get_physical_broadcast(); i++) {
2572                         if (!check_apicid_used(apic_id_map, i))
2573                                 break;
2574                 }
2575
2576                 if (i == get_physical_broadcast())
2577                         panic("Max apic_id exceeded!\n");
2578
2579                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2580                         "trying %d\n", ioapic, apic_id, i);
2581
2582                 apic_id = i;
2583         }
2584
2585         tmp = apicid_to_cpu_present(apic_id);
2586         physids_or(apic_id_map, apic_id_map, tmp);
2587
2588         if (reg_00.bits.ID != apic_id) {
2589                 reg_00.bits.ID = apic_id;
2590
2591                 spin_lock_irqsave(&ioapic_lock, flags);
2592                 io_apic_write(ioapic, 0, reg_00.raw);
2593                 reg_00.raw = io_apic_read(ioapic, 0);
2594                 spin_unlock_irqrestore(&ioapic_lock, flags);
2595
2596                 /* Sanity check */
2597                 if (reg_00.bits.ID != apic_id) {
2598                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2599                         return -1;
2600                 }
2601         }
2602
2603         apic_printk(APIC_VERBOSE, KERN_INFO
2604                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2605
2606         return apic_id;
2607 }
2608
2609
2610 int __init io_apic_get_version (int ioapic)
2611 {
2612         union IO_APIC_reg_01    reg_01;
2613         unsigned long flags;
2614
2615         spin_lock_irqsave(&ioapic_lock, flags);
2616         reg_01.raw = io_apic_read(ioapic, 1);
2617         spin_unlock_irqrestore(&ioapic_lock, flags);
2618
2619         return reg_01.bits.version;
2620 }
2621
2622
2623 int __init io_apic_get_redir_entries (int ioapic)
2624 {
2625         union IO_APIC_reg_01    reg_01;
2626         unsigned long flags;
2627
2628         spin_lock_irqsave(&ioapic_lock, flags);
2629         reg_01.raw = io_apic_read(ioapic, 1);
2630         spin_unlock_irqrestore(&ioapic_lock, flags);
2631
2632         return reg_01.bits.entries;
2633 }
2634
2635
2636 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2637 {
2638         struct IO_APIC_route_entry entry;
2639         unsigned long flags;
2640
2641         if (!IO_APIC_IRQ(irq)) {
2642                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2643                         ioapic);
2644                 return -EINVAL;
2645         }
2646
2647         /*
2648          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2649          * Note that we mask (disable) IRQs now -- these get enabled when the
2650          * corresponding device driver registers for this IRQ.
2651          */
2652
2653         memset(&entry,0,sizeof(entry));
2654
2655         entry.delivery_mode = INT_DELIVERY_MODE;
2656         entry.dest_mode = INT_DEST_MODE;
2657         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2658         entry.trigger = edge_level;
2659         entry.polarity = active_high_low;
2660         entry.mask  = 1;
2661
2662         /*
2663          * IRQs < 16 are already in the irq_2_pin[] map
2664          */
2665         if (irq >= 16)
2666                 add_pin_to_irq(irq, ioapic, pin);
2667
2668         entry.vector = assign_irq_vector(irq);
2669
2670         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2671                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2672                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2673                 edge_level, active_high_low);
2674
2675         ioapic_register_intr(irq, entry.vector, edge_level);
2676
2677         if (!ioapic && (irq < 16))
2678                 disable_8259A_irq(irq);
2679
2680         spin_lock_irqsave(&ioapic_lock, flags);
2681         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2682         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2683         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2684         spin_unlock_irqrestore(&ioapic_lock, flags);
2685
2686         return 0;
2687 }
2688
2689 #endif /* CONFIG_ACPI */