arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/nmi.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/percpu.h>
  23 #include <linux/dmi.h>
  24 #include <linux/kprobes.h>
  25 #include <linux/cpumask.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/smp.h>
  29 #include <asm/nmi.h>
  30 #include <asm/kdebug.h>
  31 #include <asm/intel_arch_perfmon.h>
  32
  33 #include "mach_traps.h"
  34
  35 int unknown_nmi_panic;
  36 int nmi_watchdog_enabled;
  37
  38 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  39  * evtsel_nmi_owner tracks the ownership of the event selection
  40  * - different performance counters/ event selection may be reserved for
  41  *   different subsystems this reservation system just tries to coordinate
  42  *   things a little
  43  */
  44
  45 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  46  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  47  */
  48 #define NMI_MAX_COUNTER_BITS 66
  49 #define NMI_MAX_COUNTER_LONGS BITS_TO_LONGS(NMI_MAX_COUNTER_BITS)
  50
  51 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner[NMI_MAX_COUNTER_LONGS]);
  52 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner[NMI_MAX_COUNTER_LONGS]);
  53
  54 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  55 /* nmi_active:
  56  * >0: the lapic NMI watchdog is active, but can be disabled
  57  * <0: the lapic NMI watchdog has not been set up, and cannot
  58  *     be enabled
  59  *  0: the lapic NMI watchdog is disabled, but can be enabled
  60  */
  61 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  62
  63 unsigned int nmi_watchdog = NMI_DEFAULT;
  64 static unsigned int nmi_hz = HZ;
  65
  66 struct nmi_watchdog_ctlblk {
  67         int enabled;
  68         u64 check_bit;
  69         unsigned int cccr_msr;
  70         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  71         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  72 };
  73 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  74
  75 /* local prototypes */
  76 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  77
  78 /* converts an msr to an appropriate reservation bit */
  79 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  80 {
  81         /* returns the bit offset of the performance counter register */
  82         switch (boot_cpu_data.x86_vendor) {
  83         case X86_VENDOR_AMD:
  84                 return (msr - MSR_K7_PERFCTR0);
  85         case X86_VENDOR_INTEL:
  86                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  87                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  88
  89                 switch (boot_cpu_data.x86) {
  90                 case 6:
  91                         return (msr - MSR_P6_PERFCTR0);
  92                 case 15:
  93                         return (msr - MSR_P4_BPU_PERFCTR0);
  94                 }
  95         }
  96         return 0;
  97 }
  98
  99 /* converts an msr to an appropriate reservation bit */
 100 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
 101 {
 102         /* returns the bit offset of the event selection register */
 103         switch (boot_cpu_data.x86_vendor) {
 104         case X86_VENDOR_AMD:
 105                 return (msr - MSR_K7_EVNTSEL0);
 106         case X86_VENDOR_INTEL:
 107                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 108                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 109
 110                 switch (boot_cpu_data.x86) {
 111                 case 6:
 112                         return (msr - MSR_P6_EVNTSEL0);
 113                 case 15:
 114                         return (msr - MSR_P4_BSU_ESCR0);
 115                 }
 116         }
 117         return 0;
 118 }
 119
 120 /* checks for a bit availability (hack for oprofile) */
 121 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 122 {
 123         int cpu;
 124         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 125         for_each_possible_cpu (cpu) {
 126                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)[0]))
 127                         return 0;
 128         }
 129         return 1;
 130 }
 131
 132 /* checks the an msr for availability */
 133 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 134 {
 135         unsigned int counter;
 136         int cpu;
 137
 138         counter = nmi_perfctr_msr_to_bit(msr);
 139         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 140
 141         for_each_possible_cpu (cpu) {
 142                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)[0]))
 143                         return 0;
 144         }
 145         return 1;
 146 }
 147
 148 static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
 149 {
 150         unsigned int counter;
 151         if (cpu < 0)
 152                 cpu = smp_processor_id();
 153
 154         counter = nmi_perfctr_msr_to_bit(msr);
 155         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 156
 157         if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)[0]))
 158                 return 1;
 159         return 0;
 160 }
 161
 162 static void __release_perfctr_nmi(int cpu, unsigned int msr)
 163 {
 164         unsigned int counter;
 165         if (cpu < 0)
 166                 cpu = smp_processor_id();
 167
 168         counter = nmi_perfctr_msr_to_bit(msr);
 169         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 170
 171         clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)[0]);
 172 }
 173
 174 int reserve_perfctr_nmi(unsigned int msr)
 175 {
 176         int cpu, i;
 177         for_each_possible_cpu (cpu) {
 178                 if (!__reserve_perfctr_nmi(cpu, msr)) {
 179                         for_each_possible_cpu (i) {
 180                                 if (i >= cpu)
 181                                         break;
 182                                 __release_perfctr_nmi(i, msr);
 183                         }
 184                         return 0;
 185                 }
 186         }
 187         return 1;
 188 }
 189
 190 void release_perfctr_nmi(unsigned int msr)
 191 {
 192         int cpu;
 193         for_each_possible_cpu (cpu) {
 194                 __release_perfctr_nmi(cpu, msr);
 195         }
 196 }
 197
 198 int __reserve_evntsel_nmi(int cpu, unsigned int msr)
 199 {
 200         unsigned int counter;
 201         if (cpu < 0)
 202                 cpu = smp_processor_id();
 203
 204         counter = nmi_evntsel_msr_to_bit(msr);
 205         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 206
 207         if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
 208                 return 1;
 209         return 0;
 210 }
 211
 212 static void __release_evntsel_nmi(int cpu, unsigned int msr)
 213 {
 214         unsigned int counter;
 215         if (cpu < 0)
 216                 cpu = smp_processor_id();
 217
 218         counter = nmi_evntsel_msr_to_bit(msr);
 219         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 220
 221         clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
 222 }
 223
 224 int reserve_evntsel_nmi(unsigned int msr)
 225 {
 226         int cpu, i;
 227         for_each_possible_cpu (cpu) {
 228                 if (!__reserve_evntsel_nmi(cpu, msr)) {
 229                         for_each_possible_cpu (i) {
 230                                 if (i >= cpu)
 231                                         break;
 232                                 __release_evntsel_nmi(i, msr);
 233                         }
 234                         return 0;
 235                 }
 236         }
 237         return 1;
 238 }
 239
 240 void release_evntsel_nmi(unsigned int msr)
 241 {
 242         int cpu;
 243         for_each_possible_cpu (cpu) {
 244                 __release_evntsel_nmi(cpu, msr);
 245         }
 246 }
 247
 248 static __cpuinit inline int nmi_known_cpu(void)
 249 {
 250         switch (boot_cpu_data.x86_vendor) {
 251         case X86_VENDOR_AMD:
 252                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6)
 253                         || (boot_cpu_data.x86 == 16));
 254         case X86_VENDOR_INTEL:
 255                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 256                         return 1;
 257                 else
 258                         return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 259         }
 260         return 0;
 261 }
 262
 263 static int endflag __initdata = 0;
 264
 265 #ifdef CONFIG_SMP
 266 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 267  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 268  * CPUs during the test make them busy.
 269  */
 270 static __init void nmi_cpu_busy(void *data)
 271 {
 272         local_irq_enable_in_hardirq();
 273         /* Intentionally don't use cpu_relax here. This is
 274            to make sure that the performance counter really ticks,
 275            even if there is a simulator or similar that catches the
 276            pause instruction. On a real HT machine this is fine because
 277            all other CPUs are busy with "useless" delay loops and don't
 278            care if they get somewhat less cycles. */
 279         while (endflag == 0)
 280                 mb();
 281 }
 282 #endif
 283
 284 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 285 {
 286         u64 counter_val;
 287         unsigned int retval = hz;
 288
 289         /*
 290          * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
 291          * are writable, with higher bits sign extending from bit 31.
 292          * So, we can only program the counter with 31 bit values and
 293          * 32nd bit should be 1, for 33.. to be 1.
 294          * Find the appropriate nmi_hz
 295          */
 296         counter_val = (u64)cpu_khz * 1000;
 297         do_div(counter_val, retval);
 298         if (counter_val > 0x7fffffffULL) {
 299                 u64 count = (u64)cpu_khz * 1000;
 300                 do_div(count, 0x7fffffffUL);
 301                 retval = count + 1;
 302         }
 303         return retval;
 304 }
 305
 306 static int __init check_nmi_watchdog(void)
 307 {
 308         unsigned int *prev_nmi_count;
 309         int cpu;
 310
 311         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 312                 return 0;
 313
 314         if (!atomic_read(&nmi_active))
 315                 return 0;
 316
 317         prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 318         if (!prev_nmi_count)
 319                 return -1;
 320
 321         printk(KERN_INFO "Testing NMI watchdog ... ");
 322
 323         if (nmi_watchdog == NMI_LOCAL_APIC)
 324                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 325
 326         for_each_possible_cpu(cpu)
 327                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 328         local_irq_enable();
 329         mdelay((20*1000)/nmi_hz); // wait 20 ticks
 330
 331         for_each_possible_cpu(cpu) {
 332 #ifdef CONFIG_SMP
 333                 /* Check cpu_callin_map here because that is set
 334                    after the timer is started. */
 335                 if (!cpu_isset(cpu, cpu_callin_map))
 336                         continue;
 337 #endif
 338                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 339                         continue;
 340                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 341                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 342                                 cpu,
 343                                 prev_nmi_count[cpu],
 344                                 nmi_count(cpu));
 345                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 346                         atomic_dec(&nmi_active);
 347                 }
 348         }
 349         if (!atomic_read(&nmi_active)) {
 350                 kfree(prev_nmi_count);
 351                 atomic_set(&nmi_active, -1);
 352                 return -1;
 353         }
 354         endflag = 1;
 355         printk("OK.\n");
 356
 357         /* now that we know it works we can reduce NMI frequency to
 358            something more reasonable; makes a difference in some configs */
 359         if (nmi_watchdog == NMI_LOCAL_APIC) {
 360                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 361
 362                 nmi_hz = 1;
 363
 364                 if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
 365                     wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
 366                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 367                 }
 368         }
 369
 370         kfree(prev_nmi_count);
 371         return 0;
 372 }
 373 /* This needs to happen later in boot so counters are working */
 374 late_initcall(check_nmi_watchdog);
 375
 376 static int __init setup_nmi_watchdog(char *str)
 377 {
 378         int nmi;
 379
 380         get_option(&str, &nmi);
 381
 382         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 383                 return 0;
 384
 385         nmi_watchdog = nmi;
 386         return 1;
 387 }
 388
 389 __setup("nmi_watchdog=", setup_nmi_watchdog);
 390
 391 static void disable_lapic_nmi_watchdog(void)
 392 {
 393         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 394
 395         if (atomic_read(&nmi_active) <= 0)
 396                 return;
 397
 398         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 399
 400         BUG_ON(atomic_read(&nmi_active) != 0);
 401 }
 402
 403 static void enable_lapic_nmi_watchdog(void)
 404 {
 405         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 406
 407         /* are we already enabled */
 408         if (atomic_read(&nmi_active) != 0)
 409                 return;
 410
 411         /* are we lapic aware */
 412         if (nmi_known_cpu() <= 0)
 413                 return;
 414
 415         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 416         touch_nmi_watchdog();
 417 }
 418
 419 void disable_timer_nmi_watchdog(void)
 420 {
 421         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 422
 423         if (atomic_read(&nmi_active) <= 0)
 424                 return;
 425
 426         disable_irq(0);
 427         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 428
 429         BUG_ON(atomic_read(&nmi_active) != 0);
 430 }
 431
 432 void enable_timer_nmi_watchdog(void)
 433 {
 434         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 435
 436         if (atomic_read(&nmi_active) == 0) {
 437                 touch_nmi_watchdog();
 438                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 439                 enable_irq(0);
 440         }
 441 }
 442
 443 static void __acpi_nmi_disable(void *__unused)
 444 {
 445         apic_write_around(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 446 }
 447
 448 /*
 449  * Disable timer based NMIs on all CPUs:
 450  */
 451 void acpi_nmi_disable(void)
 452 {
 453         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 454                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 455 }
 456
 457 static void __acpi_nmi_enable(void *__unused)
 458 {
 459         apic_write_around(APIC_LVT0, APIC_DM_NMI);
 460 }
 461
 462 /*
 463  * Enable timer based NMIs on all CPUs:
 464  */
 465 void acpi_nmi_enable(void)
 466 {
 467         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 468                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 469 }
 470
 471 #ifdef CONFIG_PM
 472
 473 static int nmi_pm_active; /* nmi_active before suspend */
 474
 475 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 476 {
 477         /* only CPU0 goes here, other CPUs should be offline */
 478         nmi_pm_active = atomic_read(&nmi_active);
 479         stop_apic_nmi_watchdog(NULL);
 480         BUG_ON(atomic_read(&nmi_active) != 0);
 481         return 0;
 482 }
 483
 484 static int lapic_nmi_resume(struct sys_device *dev)
 485 {
 486         /* only CPU0 goes here, other CPUs should be offline */
 487         if (nmi_pm_active > 0) {
 488                 setup_apic_nmi_watchdog(NULL);
 489                 touch_nmi_watchdog();
 490         }
 491         return 0;
 492 }
 493
 494
 495 static struct sysdev_class nmi_sysclass = {
 496         set_kset_name("lapic_nmi"),
 497         .resume         = lapic_nmi_resume,
 498         .suspend        = lapic_nmi_suspend,
 499 };
 500
 501 static struct sys_device device_lapic_nmi = {
 502         .id     = 0,
 503         .cls    = &nmi_sysclass,
 504 };
 505
 506 static int __init init_lapic_nmi_sysfs(void)
 507 {
 508         int error;
 509
 510         /* should really be a BUG_ON but b/c this is an
 511          * init call, it just doesn't work.  -dcz
 512          */
 513         if (nmi_watchdog != NMI_LOCAL_APIC)
 514                 return 0;
 515
 516         if ( atomic_read(&nmi_active) < 0 )
 517                 return 0;
 518
 519         error = sysdev_class_register(&nmi_sysclass);
 520         if (!error)
 521                 error = sysdev_register(&device_lapic_nmi);
 522         return error;
 523 }
 524 /* must come after the local APIC's device_initcall() */
 525 late_initcall(init_lapic_nmi_sysfs);
 526
 527 #endif  /* CONFIG_PM */
 528
 529 /*
 530  * Activate the NMI watchdog via the local APIC.
 531  * Original code written by Keith Owens.
 532  */
 533
 534 static void write_watchdog_counter(unsigned int perfctr_msr, const char *descr)
 535 {
 536         u64 count = (u64)cpu_khz * 1000;
 537
 538         do_div(count, nmi_hz);
 539         if(descr)
 540                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 541         wrmsrl(perfctr_msr, 0 - count);
 542 }
 543
 544 static void write_watchdog_counter32(unsigned int perfctr_msr,
 545                 const char *descr)
 546 {
 547         u64 count = (u64)cpu_khz * 1000;
 548
 549         do_div(count, nmi_hz);
 550         if(descr)
 551                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 552         wrmsr(perfctr_msr, (u32)(-count), 0);
 553 }
 554
 555 /* Note that these events don't tick when the CPU idles. This means
 556    the frequency varies with CPU load. */
 557
 558 #define K7_EVNTSEL_ENABLE       (1 << 22)
 559 #define K7_EVNTSEL_INT          (1 << 20)
 560 #define K7_EVNTSEL_OS           (1 << 17)
 561 #define K7_EVNTSEL_USR          (1 << 16)
 562 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 563 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 564
 565 static int setup_k7_watchdog(void)
 566 {
 567         unsigned int perfctr_msr, evntsel_msr;
 568         unsigned int evntsel;
 569         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 570
 571         perfctr_msr = MSR_K7_PERFCTR0;
 572         evntsel_msr = MSR_K7_EVNTSEL0;
 573         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 574                 goto fail;
 575
 576         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 577                 goto fail1;
 578
 579         wrmsrl(perfctr_msr, 0UL);
 580
 581         evntsel = K7_EVNTSEL_INT
 582                 | K7_EVNTSEL_OS
 583                 | K7_EVNTSEL_USR
 584                 | K7_NMI_EVENT;
 585
 586         /* setup the timer */
 587         wrmsr(evntsel_msr, evntsel, 0);
 588         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0");
 589         apic_write(APIC_LVTPC, APIC_DM_NMI);
 590         evntsel |= K7_EVNTSEL_ENABLE;
 591         wrmsr(evntsel_msr, evntsel, 0);
 592
 593         wd->perfctr_msr = perfctr_msr;
 594         wd->evntsel_msr = evntsel_msr;
 595         wd->cccr_msr = 0;  //unused
 596         wd->check_bit = 1ULL<<63;
 597         return 1;
 598 fail1:
 599         __release_perfctr_nmi(-1, perfctr_msr);
 600 fail:
 601         return 0;
 602 }
 603
 604 static void stop_k7_watchdog(void)
 605 {
 606         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 607
 608         wrmsr(wd->evntsel_msr, 0, 0);
 609
 610         __release_evntsel_nmi(-1, wd->evntsel_msr);
 611         __release_perfctr_nmi(-1, wd->perfctr_msr);
 612 }
 613
 614 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 615 #define P6_EVNTSEL_INT          (1 << 20)
 616 #define P6_EVNTSEL_OS           (1 << 17)
 617 #define P6_EVNTSEL_USR          (1 << 16)
 618 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
 619 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
 620
 621 static int setup_p6_watchdog(void)
 622 {
 623         unsigned int perfctr_msr, evntsel_msr;
 624         unsigned int evntsel;
 625         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 626
 627         perfctr_msr = MSR_P6_PERFCTR0;
 628         evntsel_msr = MSR_P6_EVNTSEL0;
 629         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 630                 goto fail;
 631
 632         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 633                 goto fail1;
 634
 635         wrmsrl(perfctr_msr, 0UL);
 636
 637         evntsel = P6_EVNTSEL_INT
 638                 | P6_EVNTSEL_OS
 639                 | P6_EVNTSEL_USR
 640                 | P6_NMI_EVENT;
 641
 642         /* setup the timer */
 643         wrmsr(evntsel_msr, evntsel, 0);
 644         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 645         write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0");
 646         apic_write(APIC_LVTPC, APIC_DM_NMI);
 647         evntsel |= P6_EVNTSEL0_ENABLE;
 648         wrmsr(evntsel_msr, evntsel, 0);
 649
 650         wd->perfctr_msr = perfctr_msr;
 651         wd->evntsel_msr = evntsel_msr;
 652         wd->cccr_msr = 0;  //unused
 653         wd->check_bit = 1ULL<<39;
 654         return 1;
 655 fail1:
 656         __release_perfctr_nmi(-1, perfctr_msr);
 657 fail:
 658         return 0;
 659 }
 660
 661 static void stop_p6_watchdog(void)
 662 {
 663         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 664
 665         wrmsr(wd->evntsel_msr, 0, 0);
 666
 667         __release_evntsel_nmi(-1, wd->evntsel_msr);
 668         __release_perfctr_nmi(-1, wd->perfctr_msr);
 669 }
 670
 671 /* Note that these events don't tick when the CPU idles. This means
 672    the frequency varies with CPU load. */
 673
 674 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 675 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 676 #define P4_ESCR_OS              (1<<3)
 677 #define P4_ESCR_USR             (1<<2)
 678 #define P4_CCCR_OVF_PMI0        (1<<26)
 679 #define P4_CCCR_OVF_PMI1        (1<<27)
 680 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 681 #define P4_CCCR_COMPLEMENT      (1<<19)
 682 #define P4_CCCR_COMPARE         (1<<18)
 683 #define P4_CCCR_REQUIRED        (3<<16)
 684 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 685 #define P4_CCCR_ENABLE          (1<<12)
 686 #define P4_CCCR_OVF             (1<<31)
 687 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 688    CRU_ESCR0 (with any non-null event selector) through a complemented
 689    max threshold. [IA32-Vol3, Section 14.9.9] */
 690
 691 static int setup_p4_watchdog(void)
 692 {
 693         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 694         unsigned int evntsel, cccr_val;
 695         unsigned int misc_enable, dummy;
 696         unsigned int ht_num;
 697         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 698
 699         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 700         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 701                 return 0;
 702
 703 #ifdef CONFIG_SMP
 704         /* detect which hyperthread we are on */
 705         if (smp_num_siblings == 2) {
 706                 unsigned int ebx, apicid;
 707
 708                 ebx = cpuid_ebx(1);
 709                 apicid = (ebx >> 24) & 0xff;
 710                 ht_num = apicid & 1;
 711         } else
 712 #endif
 713                 ht_num = 0;
 714
 715         /* performance counters are shared resources
 716          * assign each hyperthread its own set
 717          * (re-use the ESCR0 register, seems safe
 718          * and keeps the cccr_val the same)
 719          */
 720         if (!ht_num) {
 721                 /* logical cpu 0 */
 722                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 723                 evntsel_msr = MSR_P4_CRU_ESCR0;
 724                 cccr_msr = MSR_P4_IQ_CCCR0;
 725                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 726         } else {
 727                 /* logical cpu 1 */
 728                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 729                 evntsel_msr = MSR_P4_CRU_ESCR0;
 730                 cccr_msr = MSR_P4_IQ_CCCR1;
 731                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 732         }
 733
 734         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 735                 goto fail;
 736
 737         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 738                 goto fail1;
 739
 740         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 741                 | P4_ESCR_OS
 742                 | P4_ESCR_USR;
 743
 744         cccr_val |= P4_CCCR_THRESHOLD(15)
 745                  | P4_CCCR_COMPLEMENT
 746                  | P4_CCCR_COMPARE
 747                  | P4_CCCR_REQUIRED;
 748
 749         wrmsr(evntsel_msr, evntsel, 0);
 750         wrmsr(cccr_msr, cccr_val, 0);
 751         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0");
 752         apic_write(APIC_LVTPC, APIC_DM_NMI);
 753         cccr_val |= P4_CCCR_ENABLE;
 754         wrmsr(cccr_msr, cccr_val, 0);
 755         wd->perfctr_msr = perfctr_msr;
 756         wd->evntsel_msr = evntsel_msr;
 757         wd->cccr_msr = cccr_msr;
 758         wd->check_bit = 1ULL<<39;
 759         return 1;
 760 fail1:
 761         __release_perfctr_nmi(-1, perfctr_msr);
 762 fail:
 763         return 0;
 764 }
 765
 766 static void stop_p4_watchdog(void)
 767 {
 768         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 769
 770         wrmsr(wd->cccr_msr, 0, 0);
 771         wrmsr(wd->evntsel_msr, 0, 0);
 772
 773         __release_evntsel_nmi(-1, wd->evntsel_msr);
 774         __release_perfctr_nmi(-1, wd->perfctr_msr);
 775 }
 776
 777 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 778 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 779
 780 static int setup_intel_arch_watchdog(void)
 781 {
 782         unsigned int ebx;
 783         union cpuid10_eax eax;
 784         unsigned int unused;
 785         unsigned int perfctr_msr, evntsel_msr;
 786         unsigned int evntsel;
 787         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 788
 789         /*
 790          * Check whether the Architectural PerfMon supports
 791          * Unhalted Core Cycles Event or not.
 792          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 793          */
 794         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 795         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 796             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 797                 goto fail;
 798
 799         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR1;
 800         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL1;
 801
 802         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 803                 goto fail;
 804
 805         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 806                 goto fail1;
 807
 808         wrmsrl(perfctr_msr, 0UL);
 809
 810         evntsel = ARCH_PERFMON_EVENTSEL_INT
 811                 | ARCH_PERFMON_EVENTSEL_OS
 812                 | ARCH_PERFMON_EVENTSEL_USR
 813                 | ARCH_PERFMON_NMI_EVENT_SEL
 814                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 815
 816         /* setup the timer */
 817         wrmsr(evntsel_msr, evntsel, 0);
 818         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 819         write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0");
 820         apic_write(APIC_LVTPC, APIC_DM_NMI);
 821         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 822         wrmsr(evntsel_msr, evntsel, 0);
 823
 824         wd->perfctr_msr = perfctr_msr;
 825         wd->evntsel_msr = evntsel_msr;
 826         wd->cccr_msr = 0;  //unused
 827         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 828         return 1;
 829 fail1:
 830         __release_perfctr_nmi(-1, perfctr_msr);
 831 fail:
 832         return 0;
 833 }
 834
 835 static void stop_intel_arch_watchdog(void)
 836 {
 837         unsigned int ebx;
 838         union cpuid10_eax eax;
 839         unsigned int unused;
 840         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 841
 842         /*
 843          * Check whether the Architectural PerfMon supports
 844          * Unhalted Core Cycles Event or not.
 845          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 846          */
 847         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 848         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 849             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 850                 return;
 851
 852         wrmsr(wd->evntsel_msr, 0, 0);
 853         __release_evntsel_nmi(-1, wd->evntsel_msr);
 854         __release_perfctr_nmi(-1, wd->perfctr_msr);
 855 }
 856
 857 void setup_apic_nmi_watchdog (void *unused)
 858 {
 859         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 860
 861         /* only support LOCAL and IO APICs for now */
 862         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 863             (nmi_watchdog != NMI_IO_APIC))
 864                 return;
 865
 866         if (wd->enabled == 1)
 867                 return;
 868
 869         /* cheap hack to support suspend/resume */
 870         /* if cpu0 is not active neither should the other cpus */
 871         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 872                 return;
 873
 874         if (nmi_watchdog == NMI_LOCAL_APIC) {
 875                 switch (boot_cpu_data.x86_vendor) {
 876                 case X86_VENDOR_AMD:
 877                         if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15 &&
 878                                 boot_cpu_data.x86 != 16)
 879                                 return;
 880                         if (!setup_k7_watchdog())
 881                                 return;
 882                         break;
 883                 case X86_VENDOR_INTEL:
 884                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 885                                 if (!setup_intel_arch_watchdog())
 886                                         return;
 887                                 break;
 888                         }
 889                         switch (boot_cpu_data.x86) {
 890                         case 6:
 891                                 if (boot_cpu_data.x86_model > 0xd)
 892                                         return;
 893
 894                                 if (!setup_p6_watchdog())
 895                                         return;
 896                                 break;
 897                         case 15:
 898                                 if (boot_cpu_data.x86_model > 0x4)
 899                                         return;
 900
 901                                 if (!setup_p4_watchdog())
 902                                         return;
 903                                 break;
 904                         default:
 905                                 return;
 906                         }
 907                         break;
 908                 default:
 909                         return;
 910                 }
 911         }
 912         wd->enabled = 1;
 913         atomic_inc(&nmi_active);
 914 }
 915
 916 void stop_apic_nmi_watchdog(void *unused)
 917 {
 918         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 919
 920         /* only support LOCAL and IO APICs for now */
 921         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 922             (nmi_watchdog != NMI_IO_APIC))
 923                 return;
 924
 925         if (wd->enabled == 0)
 926                 return;
 927
 928         if (nmi_watchdog == NMI_LOCAL_APIC) {
 929                 switch (boot_cpu_data.x86_vendor) {
 930                 case X86_VENDOR_AMD:
 931                         stop_k7_watchdog();
 932                         break;
 933                 case X86_VENDOR_INTEL:
 934                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 935                                 stop_intel_arch_watchdog();
 936                                 break;
 937                         }
 938                         switch (boot_cpu_data.x86) {
 939                         case 6:
 940                                 if (boot_cpu_data.x86_model > 0xd)
 941                                         break;
 942                                 stop_p6_watchdog();
 943                                 break;
 944                         case 15:
 945                                 if (boot_cpu_data.x86_model > 0x4)
 946                                         break;
 947                                 stop_p4_watchdog();
 948                                 break;
 949                         }
 950                         break;
 951                 default:
 952                         return;
 953                 }
 954         }
 955         wd->enabled = 0;
 956         atomic_dec(&nmi_active);
 957 }
 958
 959 /*
 960  * the best way to detect whether a CPU has a 'hard lockup' problem
 961  * is to check it's local APIC timer IRQ counts. If they are not
 962  * changing then that CPU has some problem.
 963  *
 964  * as these watchdog NMI IRQs are generated on every CPU, we only
 965  * have to check the current processor.
 966  *
 967  * since NMIs don't listen to _any_ locks, we have to be extremely
 968  * careful not to rely on unsafe variables. The printk might lock
 969  * up though, so we have to break up any console locks first ...
 970  * [when there will be more tty-related locks, break them up
 971  *  here too!]
 972  */
 973
 974 static unsigned int
 975         last_irq_sums [NR_CPUS],
 976         alert_counter [NR_CPUS];
 977
 978 void touch_nmi_watchdog (void)
 979 {
 980         if (nmi_watchdog > 0) {
 981                 unsigned cpu;
 982
 983                 /*
 984                  * Just reset the alert counters, (other CPUs might be
 985                  * spinning on locks we hold):
 986                  */
 987                 for_each_present_cpu (cpu)
 988                         alert_counter[cpu] = 0;
 989         }
 990
 991         /*
 992          * Tickle the softlockup detector too:
 993          */
 994         touch_softlockup_watchdog();
 995 }
 996 EXPORT_SYMBOL(touch_nmi_watchdog);
 997
 998 extern void die_nmi(struct pt_regs *, const char *msg);
 999
1000 __kprobes int nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
1001 {
1002
1003         /*
1004          * Since current_thread_info()-> is always on the stack, and we
1005          * always switch the stack NMI-atomically, it's safe to use
1006          * smp_processor_id().
1007          */
1008         unsigned int sum;
1009         int touched = 0;
1010         int cpu = smp_processor_id();
1011         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
1012         u64 dummy;
1013         int rc=0;
1014
1015         /* check for other users first */
1016         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
1017                         == NOTIFY_STOP) {
1018                 rc = 1;
1019                 touched = 1;
1020         }
1021
1022         if (cpu_isset(cpu, backtrace_mask)) {
1023                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
1024
1025                 spin_lock(&lock);
1026                 printk("NMI backtrace for cpu %d\n", cpu);
1027                 dump_stack();
1028                 spin_unlock(&lock);
1029                 cpu_clear(cpu, backtrace_mask);
1030         }
1031
1032         /*
1033          * Take the local apic timer and PIT/HPET into account. We don't
1034          * know which one is active, when we have highres/dyntick on
1035          */
1036         sum = per_cpu(irq_stat, cpu).apic_timer_irqs + kstat_irqs(0);
1037
1038         /* if the none of the timers isn't firing, this cpu isn't doing much */
1039         if (!touched && last_irq_sums[cpu] == sum) {
1040                 /*
1041                  * Ayiee, looks like this CPU is stuck ...
1042                  * wait a few IRQs (5 seconds) before doing the oops ...
1043                  */
1044                 alert_counter[cpu]++;
1045                 if (alert_counter[cpu] == 5*nmi_hz)
1046                         /*
1047                          * die_nmi will return ONLY if NOTIFY_STOP happens..
1048                          */
1049                         die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
1050         } else {
1051                 last_irq_sums[cpu] = sum;
1052                 alert_counter[cpu] = 0;
1053         }
1054         /* see if the nmi watchdog went off */
1055         if (wd->enabled) {
1056                 if (nmi_watchdog == NMI_LOCAL_APIC) {
1057                         rdmsrl(wd->perfctr_msr, dummy);
1058                         if (dummy & wd->check_bit){
1059                                 /* this wasn't a watchdog timer interrupt */
1060                                 goto done;
1061                         }
1062
1063                         /* only Intel P4 uses the cccr msr */
1064                         if (wd->cccr_msr != 0) {
1065                                 /*
1066                                  * P4 quirks:
1067                                  * - An overflown perfctr will assert its interrupt
1068                                  *   until the OVF flag in its CCCR is cleared.
1069                                  * - LVTPC is masked on interrupt and must be
1070                                  *   unmasked by the LVTPC handler.
1071                                  */
1072                                 rdmsrl(wd->cccr_msr, dummy);
1073                                 dummy &= ~P4_CCCR_OVF;
1074                                 wrmsrl(wd->cccr_msr, dummy);
1075                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1076                                 /* start the cycle over again */
1077                                 write_watchdog_counter(wd->perfctr_msr, NULL);
1078                         }
1079                         else if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
1080                                  wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
1081                                 /* P6 based Pentium M need to re-unmask
1082                                  * the apic vector but it doesn't hurt
1083                                  * other P6 variant.
1084                                  * ArchPerfom/Core Duo also needs this */
1085                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1086                                 /* P6/ARCH_PERFMON has 32 bit counter write */
1087                                 write_watchdog_counter32(wd->perfctr_msr, NULL);
1088                         } else {
1089                                 /* start the cycle over again */
1090                                 write_watchdog_counter(wd->perfctr_msr, NULL);
1091                         }
1092                         rc = 1;
1093                 } else if (nmi_watchdog == NMI_IO_APIC) {
1094                         /* don't know how to accurately check for this.
1095                          * just assume it was a watchdog timer interrupt
1096                          * This matches the old behaviour.
1097                          */
1098                         rc = 1;
1099                 }
1100         }
1101 done:
1102         return rc;
1103 }
1104
1105 int do_nmi_callback(struct pt_regs * regs, int cpu)
1106 {
1107 #ifdef CONFIG_SYSCTL
1108         if (unknown_nmi_panic)
1109                 return unknown_nmi_panic_callback(regs, cpu);
1110 #endif
1111         return 0;
1112 }
1113
1114 #ifdef CONFIG_SYSCTL
1115
1116 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
1117 {
1118         unsigned char reason = get_nmi_reason();
1119         char buf[64];
1120
1121         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
1122         die_nmi(regs, buf);
1123         return 0;
1124 }
1125
1126 /*
1127  * proc handler for /proc/sys/kernel/nmi
1128  */
1129 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
1130                         void __user *buffer, size_t *length, loff_t *ppos)
1131 {
1132         int old_state;
1133
1134         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
1135         old_state = nmi_watchdog_enabled;
1136         proc_dointvec(table, write, file, buffer, length, ppos);
1137         if (!!old_state == !!nmi_watchdog_enabled)
1138                 return 0;
1139
1140         if (atomic_read(&nmi_active) < 0) {
1141                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
1142                 return -EIO;
1143         }
1144
1145         if (nmi_watchdog == NMI_DEFAULT) {
1146                 if (nmi_known_cpu() > 0)
1147                         nmi_watchdog = NMI_LOCAL_APIC;
1148                 else
1149                         nmi_watchdog = NMI_IO_APIC;
1150         }
1151
1152         if (nmi_watchdog == NMI_LOCAL_APIC) {
1153                 if (nmi_watchdog_enabled)
1154                         enable_lapic_nmi_watchdog();
1155                 else
1156                         disable_lapic_nmi_watchdog();
1157         } else {
1158                 printk( KERN_WARNING
1159                         "NMI watchdog doesn't know what hardware to touch\n");
1160                 return -EIO;
1161         }
1162         return 0;
1163 }
1164
1165 #endif
1166
1167 void __trigger_all_cpu_backtrace(void)
1168 {
1169         int i;
1170
1171         backtrace_mask = cpu_online_map;
1172         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
1173         for (i = 0; i < 10 * 1000; i++) {
1174                 if (cpus_empty(backtrace_mask))
1175                         break;
1176                 mdelay(1);
1177         }
1178 }
1179
1180 EXPORT_SYMBOL(nmi_active);
1181 EXPORT_SYMBOL(nmi_watchdog);
1182 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1183 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1184 EXPORT_SYMBOL(reserve_perfctr_nmi);
1185 EXPORT_SYMBOL(release_perfctr_nmi);
1186 EXPORT_SYMBOL(reserve_evntsel_nmi);
1187 EXPORT_SYMBOL(release_evntsel_nmi);
1188 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1189 EXPORT_SYMBOL(enable_timer_nmi_watchdog);