1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/module.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/smp_lock.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/bootmem.h>
23 #include <linux/completion.h>
25 #include <asm/voyager.h>
28 #include <asm/pgalloc.h>
29 #include <asm/tlbflush.h>
30 #include <asm/arch_hooks.h>
32 /* TLB state -- visible externally, indexed physically */
33 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
35 /* CPU IRQ affinity -- set to all ones initially */
36 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
41 EXPORT_SYMBOL(cpu_data);
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id;
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors = 0;
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors = 0;
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors = 0;
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus = 1;
63 /* Have we found an SMP box - used by time.c to do the profiling
64 interrupt for timeslicing; do not set to 1 until the per CPU timer
65 interrupt is active */
66 int smp_found_config = 0;
68 /* Used for the invalidate map that's also checked in the spinlock */
69 static volatile unsigned long smp_invalidate_needed;
71 /* Bitmask of currently online CPUs - used by setup.c for
72 /proc/cpuinfo, visible externally but still physical */
73 cpumask_t cpu_online_map = CPU_MASK_NONE;
74 EXPORT_SYMBOL(cpu_online_map);
76 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
77 * by scheduler but indexed physically */
78 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
81 /* The internal functions */
82 static void send_CPI(__u32 cpuset, __u8 cpi);
83 static void ack_CPI(__u8 cpi);
84 static int ack_QIC_CPI(__u8 cpi);
85 static void ack_special_QIC_CPI(__u8 cpi);
86 static void ack_VIC_CPI(__u8 cpi);
87 static void send_CPI_allbutself(__u8 cpi);
88 static void mask_vic_irq(unsigned int irq);
89 static void unmask_vic_irq(unsigned int irq);
90 static unsigned int startup_vic_irq(unsigned int irq);
91 static void enable_local_vic_irq(unsigned int irq);
92 static void disable_local_vic_irq(unsigned int irq);
93 static void before_handle_vic_irq(unsigned int irq);
94 static void after_handle_vic_irq(unsigned int irq);
95 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
96 static void ack_vic_irq(unsigned int irq);
97 static void vic_enable_cpi(void);
98 static void do_boot_cpu(__u8 cpuid);
99 static void do_quad_bootstrap(void);
101 int hard_smp_processor_id(void);
102 int safe_smp_processor_id(void);
104 /* Inline functions */
106 send_one_QIC_CPI(__u8 cpu, __u8 cpi)
108 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
109 (smp_processor_id() << 16) + cpi;
113 send_QIC_CPI(__u32 cpuset, __u8 cpi)
117 for_each_online_cpu(cpu) {
118 if(cpuset & (1<<cpu)) {
120 if(!cpu_isset(cpu, cpu_online_map))
121 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
123 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
129 wrapper_smp_local_timer_interrupt(void)
132 smp_local_timer_interrupt();
137 send_one_CPI(__u8 cpu, __u8 cpi)
139 if(voyager_quad_processors & (1<<cpu))
140 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
142 send_CPI(1<<cpu, cpi);
146 send_CPI_allbutself(__u8 cpi)
148 __u8 cpu = smp_processor_id();
149 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
156 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
157 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
161 is_cpu_extended(void)
163 __u8 cpu = hard_smp_processor_id();
165 return(voyager_extended_vic_processors & (1<<cpu));
169 is_cpu_vic_boot(void)
171 __u8 cpu = hard_smp_processor_id();
173 return(voyager_extended_vic_processors
174 & voyager_allowed_boot_processors & (1<<cpu));
182 case VIC_CPU_BOOT_CPI:
183 if(is_cpu_quad() && !is_cpu_vic_boot())
190 /* These are slightly strange. Even on the Quad card,
191 * They are vectored as VIC CPIs */
193 ack_special_QIC_CPI(cpi);
198 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
203 /* local variables */
205 /* The VIC IRQ descriptors -- these look almost identical to the
206 * 8259 IRQs except that masks and things must be kept per processor
208 static struct irq_chip vic_chip = {
210 .startup = startup_vic_irq,
211 .mask = mask_vic_irq,
212 .unmask = unmask_vic_irq,
213 .set_affinity = set_vic_irq_affinity,
216 /* used to count up as CPUs are brought on line (starts at 0) */
217 static int cpucount = 0;
219 /* steal a page from the bottom of memory for the trampoline and
220 * squirrel its address away here. This will be in kernel virtual
222 static __u32 trampoline_base;
224 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
225 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
226 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
227 static DEFINE_PER_CPU(int, prof_counter) = 1;
229 /* the map used to check if a CPU has booted */
230 static __u32 cpu_booted_map;
232 /* the synchronize flag used to hold all secondary CPUs spinning in
233 * a tight loop until the boot sequence is ready for them */
234 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
236 /* This is for the new dynamic CPU boot code */
237 cpumask_t cpu_callin_map = CPU_MASK_NONE;
238 cpumask_t cpu_callout_map = CPU_MASK_NONE;
239 EXPORT_SYMBOL(cpu_callout_map);
240 cpumask_t cpu_possible_map = CPU_MASK_NONE;
241 EXPORT_SYMBOL(cpu_possible_map);
243 /* The per processor IRQ masks (these are usually kept in sync) */
244 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
246 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
247 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
249 /* Lock for enable/disable of VIC interrupts */
250 static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
252 /* The boot processor is correctly set up in PC mode when it
253 * comes up, but the secondaries need their master/slave 8259
254 * pairs initializing correctly */
256 /* Interrupt counters (per cpu) and total - used to try to
257 * even up the interrupt handling routines */
258 static long vic_intr_total = 0;
259 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
260 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
262 /* Since we can only use CPI0, we fake all the other CPIs */
263 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
265 /* debugging routine to read the isr of the cpu's pic */
272 isr = inb(0xa0) << 8;
283 /* not a quad, no setup */
286 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
287 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
289 if(is_cpu_extended()) {
290 /* the QIC duplicate of the VIC base register */
291 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
292 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
294 /* FIXME: should set up the QIC timer and memory parity
295 * error vectors here */
302 outb(1, VIC_REDIRECT_REGISTER_1);
303 /* clear the claim registers for dynamic routing */
304 outb(0, VIC_CLAIM_REGISTER_0);
305 outb(0, VIC_CLAIM_REGISTER_1);
307 outb(0, VIC_PRIORITY_REGISTER);
308 /* Set the Primary and Secondary Microchannel vector
309 * bases to be the same as the ordinary interrupts
311 * FIXME: This would be more efficient using separate
313 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
314 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
315 /* Now initiallise the master PIC belonging to this CPU by
316 * sending the four ICWs */
318 /* ICW1: level triggered, ICW4 needed */
321 /* ICW2: vector base */
322 outb(FIRST_EXTERNAL_VECTOR, 0x21);
324 /* ICW3: slave at line 2 */
327 /* ICW4: 8086 mode */
330 /* now the same for the slave PIC */
332 /* ICW1: level trigger, ICW4 needed */
335 /* ICW2: slave vector base */
336 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
341 /* ICW4: 8086 mode */
346 do_quad_bootstrap(void)
348 if(is_cpu_quad() && is_cpu_vic_boot()) {
351 __u8 cpuid = hard_smp_processor_id();
353 local_irq_save(flags);
355 for(i = 0; i<4; i++) {
356 /* FIXME: this would be >>3 &0x7 on the 32 way */
357 if(((cpuid >> 2) & 0x03) == i)
358 /* don't lower our own mask! */
361 /* masquerade as local Quad CPU */
362 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
363 /* enable the startup CPI */
364 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
366 outb(0, QIC_PROCESSOR_ID);
368 local_irq_restore(flags);
373 /* Set up all the basic stuff: read the SMP config and make all the
374 * SMP information reflect only the boot cpu. All others will be
375 * brought on-line later. */
377 find_smp_config(void)
381 boot_cpu_id = hard_smp_processor_id();
383 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
385 /* initialize the CPU structures (moved from smp_boot_cpus) */
386 for(i=0; i<NR_CPUS; i++) {
387 cpu_irq_affinity[i] = ~0;
389 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
391 /* The boot CPU must be extended */
392 voyager_extended_vic_processors = 1<<boot_cpu_id;
393 /* initially, all of the first 8 cpu's can boot */
394 voyager_allowed_boot_processors = 0xff;
395 /* set up everything for just this CPU, we can alter
396 * this as we start the other CPUs later */
397 /* now get the CPU disposition from the extended CMOS */
398 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
399 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
400 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
401 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
402 cpu_possible_map = phys_cpu_present_map;
403 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
404 /* Here we set up the VIC to enable SMP */
405 /* enable the CPIs by writing the base vector to their register */
406 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
407 outb(1, VIC_REDIRECT_REGISTER_1);
408 /* set the claim registers for static routing --- Boot CPU gets
409 * all interrupts untill all other CPUs started */
410 outb(0xff, VIC_CLAIM_REGISTER_0);
411 outb(0xff, VIC_CLAIM_REGISTER_1);
412 /* Set the Primary and Secondary Microchannel vector
413 * bases to be the same as the ordinary interrupts
415 * FIXME: This would be more efficient using separate
417 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
418 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
420 /* Finally tell the firmware that we're driving */
421 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
422 VOYAGER_SUS_IN_CONTROL_PORT);
424 current_thread_info()->cpu = boot_cpu_id;
428 * The bootstrap kernel entry code has set these up. Save them
429 * for a given CPU, id is physical */
431 smp_store_cpu_info(int id)
433 struct cpuinfo_x86 *c=&cpu_data[id];
440 /* set up the trampoline and return the physical address of the code */
442 setup_trampoline(void)
444 /* these two are global symbols in trampoline.S */
445 extern __u8 trampoline_end[];
446 extern __u8 trampoline_data[];
448 memcpy((__u8 *)trampoline_base, trampoline_data,
449 trampoline_end - trampoline_data);
450 return virt_to_phys((__u8 *)trampoline_base);
453 /* Routine initially called when a non-boot CPU is brought online */
455 start_secondary(void *unused)
457 __u8 cpuid = hard_smp_processor_id();
458 /* external functions not defined in the headers */
459 extern void calibrate_delay(void);
463 /* OK, we're in the routine */
464 ack_CPI(VIC_CPU_BOOT_CPI);
466 /* setup the 8259 master slave pair belonging to this CPU ---
467 * we won't actually receive any until the boot CPU
468 * relinquishes it's static routing mask */
473 if(is_cpu_quad() && !is_cpu_vic_boot()) {
474 /* clear the boot CPI */
477 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
478 printk("read dummy %d\n", dummy);
481 /* lower the mask to receive CPIs */
484 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
486 /* enable interrupts */
489 /* get our bogomips */
492 /* save our processor parameters */
493 smp_store_cpu_info(cpuid);
495 /* if we're a quad, we may need to bootstrap other CPUs */
498 /* FIXME: this is rather a poor hack to prevent the CPU
499 * activating softirqs while it's supposed to be waiting for
500 * permission to proceed. Without this, the new per CPU stuff
501 * in the softirqs will fail */
503 cpu_set(cpuid, cpu_callin_map);
505 /* signal that we're done */
508 while (!cpu_isset(cpuid, smp_commenced_mask))
514 cpu_set(cpuid, cpu_online_map);
520 /* Routine to kick start the given CPU and wait for it to report ready
521 * (or timeout in startup). When this routine returns, the requested
522 * CPU is either fully running and configured or known to be dead.
524 * We call this routine sequentially 1 CPU at a time, so no need for
528 do_boot_cpu(__u8 cpu)
530 struct task_struct *idle;
533 int quad_boot = (1<<cpu) & voyager_quad_processors
534 & ~( voyager_extended_vic_processors
535 & voyager_allowed_boot_processors);
537 /* For the 486, we can't use the 4Mb page table trick, so
538 * must map a region of memory */
541 unsigned long *page_table_copies = (unsigned long *)
542 __get_free_page(GFP_KERNEL);
544 pgd_t orig_swapper_pg_dir0;
546 /* This is an area in head.S which was used to set up the
547 * initial kernel stack. We need to alter this to give the
548 * booting CPU a new stack (taken from its idle process) */
553 /* This is the format of the CPI IDT gate (in real mode) which
554 * we're hijacking to boot the CPU */
563 __u32 *hijack_vector;
564 __u32 start_phys_address = setup_trampoline();
566 /* There's a clever trick to this: The linux trampoline is
567 * compiled to begin at absolute location zero, so make the
568 * address zero but have the data segment selector compensate
569 * for the actual address */
570 hijack_source.idt.Offset = start_phys_address & 0x000F;
571 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
574 idle = fork_idle(cpu);
576 panic("failed fork for CPU%d", cpu);
577 idle->thread.eip = (unsigned long) start_secondary;
578 /* init_tasks (in sched.c) is indexed logically */
579 stack_start.esp = (void *) idle->thread.esp;
583 /* Note: Don't modify initial ss override */
584 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
585 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
586 hijack_source.idt.Offset, stack_start.esp));
587 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
588 * (so that the booting CPU can find start_32 */
589 orig_swapper_pg_dir0 = swapper_pg_dir[0];
591 if(page_table_copies == NULL)
592 panic("No free memory for 486 page tables\n");
593 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
594 page_table_copies[i] = (i * PAGE_SIZE)
595 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
597 ((unsigned long *)swapper_pg_dir)[0] =
598 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
599 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
601 ((unsigned long *)swapper_pg_dir)[0] =
602 (virt_to_phys(pg0) & PAGE_MASK)
603 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
607 printk("CPU %d: non extended Quad boot\n", cpu);
608 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
609 *hijack_vector = hijack_source.val;
611 printk("CPU%d: extended VIC boot\n", cpu);
612 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
613 *hijack_vector = hijack_source.val;
614 /* VIC errata, may also receive interrupt at this address */
615 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
616 *hijack_vector = hijack_source.val;
618 /* All non-boot CPUs start with interrupts fully masked. Need
619 * to lower the mask of the CPI we're about to send. We do
620 * this in the VIC by masquerading as the processor we're
621 * about to boot and lowering its interrupt mask */
622 local_irq_save(flags);
624 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
626 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
627 /* here we're altering registers belonging to `cpu' */
629 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
630 /* now go back to our original identity */
631 outb(boot_cpu_id, VIC_PROCESSOR_ID);
633 /* and boot the CPU */
635 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
638 local_irq_restore(flags);
640 /* now wait for it to become ready (or timeout) */
641 for(timeout = 0; timeout < 50000; timeout++) {
646 /* reset the page table */
647 swapper_pg_dir[0] = orig_swapper_pg_dir0;
650 free_page((unsigned long)page_table_copies);
653 if (cpu_booted_map) {
654 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
655 cpu, smp_processor_id()));
657 printk("CPU%d: ", cpu);
658 print_cpu_info(&cpu_data[cpu]);
660 cpu_set(cpu, cpu_callout_map);
661 cpu_set(cpu, cpu_present_map);
664 printk("CPU%d FAILED TO BOOT: ", cpu);
665 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
668 printk("Not responding.\n");
679 /* CAT BUS initialisation must be done after the memory */
680 /* FIXME: The L4 has a catbus too, it just needs to be
681 * accessed in a totally different way */
682 if(voyager_level == 5) {
685 /* now that the cat has probed the Voyager System Bus, sanity
686 * check the cpu map */
687 if( ((voyager_quad_processors | voyager_extended_vic_processors)
688 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
690 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
692 } else if(voyager_level == 4)
693 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
695 /* this sets up the idle task to run on the current cpu */
696 voyager_extended_cpus = 1;
697 /* Remove the global_irq_holder setting, it triggers a BUG() on
698 * schedule at the moment */
699 //global_irq_holder = boot_cpu_id;
701 /* FIXME: Need to do something about this but currently only works
702 * on CPUs with a tsc which none of mine have.
703 smp_tune_scheduling();
705 smp_store_cpu_info(boot_cpu_id);
706 printk("CPU%d: ", boot_cpu_id);
707 print_cpu_info(&cpu_data[boot_cpu_id]);
710 /* booting on a Quad CPU */
711 printk("VOYAGER SMP: Boot CPU is Quad\n");
716 /* enable our own CPIs */
719 cpu_set(boot_cpu_id, cpu_online_map);
720 cpu_set(boot_cpu_id, cpu_callout_map);
722 /* loop over all the extended VIC CPUs and boot them. The
723 * Quad CPUs must be bootstrapped by their extended VIC cpu */
724 for(i = 0; i < NR_CPUS; i++) {
725 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
728 /* This udelay seems to be needed for the Quad boots
729 * don't remove unless you know what you're doing */
732 /* we could compute the total bogomips here, but why bother?,
733 * Code added from smpboot.c */
735 unsigned long bogosum = 0;
736 for (i = 0; i < NR_CPUS; i++)
737 if (cpu_isset(i, cpu_online_map))
738 bogosum += cpu_data[i].loops_per_jiffy;
739 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
742 (bogosum/(5000/HZ))%100);
744 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
745 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
746 /* that's it, switch to symmetric mode */
747 outb(0, VIC_PRIORITY_REGISTER);
748 outb(0, VIC_CLAIM_REGISTER_0);
749 outb(0, VIC_CLAIM_REGISTER_1);
751 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
754 /* Reload the secondary CPUs task structure (this function does not
757 initialize_secondary(void)
761 set_current(hard_get_current());
765 * We don't actually need to load the full TSS,
766 * basically just the stack pointer and the eip.
773 :"r" (current->thread.esp),"r" (current->thread.eip));
776 /* handle a Voyager SYS_INT -- If we don't, the base board will
779 * System interrupts occur because some problem was detected on the
780 * various busses. To find out what you have to probe all the
781 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
783 smp_vic_sys_interrupt(struct pt_regs *regs)
785 ack_CPI(VIC_SYS_INT);
786 printk("Voyager SYSTEM INTERRUPT\n");
789 /* Handle a voyager CMN_INT; These interrupts occur either because of
790 * a system status change or because a single bit memory error
791 * occurred. FIXME: At the moment, ignore all this. */
793 smp_vic_cmn_interrupt(struct pt_regs *regs)
795 static __u8 in_cmn_int = 0;
796 static DEFINE_SPINLOCK(cmn_int_lock);
798 /* common ints are broadcast, so make sure we only do this once */
799 _raw_spin_lock(&cmn_int_lock);
804 _raw_spin_unlock(&cmn_int_lock);
806 VDEBUG(("Voyager COMMON INTERRUPT\n"));
808 if(voyager_level == 5)
809 voyager_cat_do_common_interrupt();
811 _raw_spin_lock(&cmn_int_lock);
814 _raw_spin_unlock(&cmn_int_lock);
815 ack_CPI(VIC_CMN_INT);
819 * Reschedule call back. Nothing to do, all the work is done
820 * automatically when we return from the interrupt. */
822 smp_reschedule_interrupt(void)
827 static struct mm_struct * flush_mm;
828 static unsigned long flush_va;
829 static DEFINE_SPINLOCK(tlbstate_lock);
830 #define FLUSH_ALL 0xffffffff
833 * We cannot call mmdrop() because we are in interrupt context,
834 * instead update mm->cpu_vm_mask.
836 * We need to reload %cr3 since the page tables may be going
837 * away from under us..
840 leave_mm (unsigned long cpu)
842 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
844 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
845 load_cr3(swapper_pg_dir);
850 * Invalidate call-back
853 smp_invalidate_interrupt(void)
855 __u8 cpu = smp_processor_id();
857 if (!test_bit(cpu, &smp_invalidate_needed))
859 /* This will flood messages. Don't uncomment unless you see
860 * Problems with cross cpu invalidation
861 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
862 smp_processor_id()));
865 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
866 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
867 if (flush_va == FLUSH_ALL)
870 __flush_tlb_one(flush_va);
874 smp_mb__before_clear_bit();
875 clear_bit(cpu, &smp_invalidate_needed);
876 smp_mb__after_clear_bit();
879 /* All the new flush operations for 2.4 */
882 /* This routine is called with a physical cpu mask */
884 flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
891 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
893 if (cpumask & (1 << smp_processor_id()))
898 spin_lock(&tlbstate_lock);
902 atomic_set_mask(cpumask, &smp_invalidate_needed);
904 * We have to send the CPI only to
907 send_CPI(cpumask, VIC_INVALIDATE_CPI);
909 while (smp_invalidate_needed) {
912 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
917 /* Uncomment only to debug invalidation problems
918 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
923 spin_unlock(&tlbstate_lock);
927 flush_tlb_current_task(void)
929 struct mm_struct *mm = current->mm;
930 unsigned long cpu_mask;
934 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
937 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
944 flush_tlb_mm (struct mm_struct * mm)
946 unsigned long cpu_mask;
950 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
952 if (current->active_mm == mm) {
956 leave_mm(smp_processor_id());
959 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
964 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
966 struct mm_struct *mm = vma->vm_mm;
967 unsigned long cpu_mask;
971 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
972 if (current->active_mm == mm) {
976 leave_mm(smp_processor_id());
980 flush_tlb_others(cpu_mask, mm, va);
984 EXPORT_SYMBOL(flush_tlb_page);
986 /* enable the requested IRQs */
988 smp_enable_irq_interrupt(void)
991 __u8 cpu = get_cpu();
993 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
994 vic_irq_enable_mask[cpu]));
996 spin_lock(&vic_irq_lock);
997 for(irq = 0; irq < 16; irq++) {
998 if(vic_irq_enable_mask[cpu] & (1<<irq))
999 enable_local_vic_irq(irq);
1001 vic_irq_enable_mask[cpu] = 0;
1002 spin_unlock(&vic_irq_lock);
1004 put_cpu_no_resched();
1008 * CPU halt call-back
1011 smp_stop_cpu_function(void *dummy)
1013 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1014 cpu_clear(smp_processor_id(), cpu_online_map);
1015 local_irq_disable();
1020 static DEFINE_SPINLOCK(call_lock);
1022 struct call_data_struct {
1023 void (*func) (void *info);
1025 volatile unsigned long started;
1026 volatile unsigned long finished;
1030 static struct call_data_struct * call_data;
1032 /* execute a thread on a new CPU. The function to be called must be
1033 * previously set up. This is used to schedule a function for
1034 * execution on all CPU's - set up the function then broadcast a
1035 * function_interrupt CPI to come here on each CPU */
1037 smp_call_function_interrupt(void)
1039 void (*func) (void *info) = call_data->func;
1040 void *info = call_data->info;
1041 /* must take copy of wait because call_data may be replaced
1042 * unless the function is waiting for us to finish */
1043 int wait = call_data->wait;
1044 __u8 cpu = smp_processor_id();
1047 * Notify initiating CPU that I've grabbed the data and am
1048 * about to execute the function
1051 if(!test_and_clear_bit(cpu, &call_data->started)) {
1052 /* If the bit wasn't set, this could be a replay */
1053 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1057 * At this point the info structure may be out of scope unless wait==1
1064 clear_bit(cpu, &call_data->finished);
1068 /* Call this function on all CPUs using the function_interrupt above
1069 <func> The function to run. This must be fast and non-blocking.
1070 <info> An arbitrary pointer to pass to the function.
1071 <retry> If true, keep retrying until ready.
1072 <wait> If true, wait until function has completed on other CPUs.
1073 [RETURNS] 0 on success, else a negative status code. Does not return until
1074 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1077 smp_call_function (void (*func) (void *info), void *info, int retry,
1080 struct call_data_struct data;
1081 __u32 mask = cpus_addr(cpu_online_map)[0];
1083 mask &= ~(1<<smp_processor_id());
1088 /* Can deadlock when called with interrupts disabled */
1089 WARN_ON(irqs_disabled());
1093 data.started = mask;
1096 data.finished = mask;
1098 spin_lock(&call_lock);
1101 /* Send a message to all other CPUs and wait for them to respond */
1102 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1104 /* Wait for response */
1105 while (data.started)
1109 while (data.finished)
1112 spin_unlock(&call_lock);
1116 EXPORT_SYMBOL(smp_call_function);
1118 /* Sorry about the name. In an APIC based system, the APICs
1119 * themselves are programmed to send a timer interrupt. This is used
1120 * by linux to reschedule the processor. Voyager doesn't have this,
1121 * so we use the system clock to interrupt one processor, which in
1122 * turn, broadcasts a timer CPI to all the others --- we receive that
1123 * CPI here. We don't use this actually for counting so losing
1124 * ticks doesn't matter
1126 * FIXME: For those CPU's which actually have a local APIC, we could
1127 * try to use it to trigger this interrupt instead of having to
1128 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1129 * no local APIC, so I can't do this
1131 * This function is currently a placeholder and is unused in the code */
1133 smp_apic_timer_interrupt(struct pt_regs *regs)
1135 struct pt_regs *old_regs = set_irq_regs(regs);
1136 wrapper_smp_local_timer_interrupt();
1137 set_irq_regs(old_regs);
1140 /* All of the QUAD interrupt GATES */
1142 smp_qic_timer_interrupt(struct pt_regs *regs)
1144 ack_QIC_CPI(QIC_TIMER_CPI);
1145 struct pt_regs *old_regs = set_irq_regs(regs);
1146 wrapper_smp_local_timer_interrupt(void);
1147 set_irq_regs(old_regs);
1151 smp_qic_invalidate_interrupt(struct pt_regs *regs)
1153 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1154 smp_invalidate_interrupt();
1158 smp_qic_reschedule_interrupt(struct pt_regs *regs)
1160 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1161 smp_reschedule_interrupt();
1165 smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1167 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1168 smp_enable_irq_interrupt();
1172 smp_qic_call_function_interrupt(struct pt_regs *regs)
1174 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1175 smp_call_function_interrupt();
1179 smp_vic_cpi_interrupt(struct pt_regs *regs)
1181 struct pt_regs *old_regs = set_irq_regs(regs);
1182 __u8 cpu = smp_processor_id();
1185 ack_QIC_CPI(VIC_CPI_LEVEL0);
1187 ack_VIC_CPI(VIC_CPI_LEVEL0);
1189 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1190 wrapper_smp_local_timer_interrupt();
1191 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1192 smp_invalidate_interrupt();
1193 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1194 smp_reschedule_interrupt();
1195 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1196 smp_enable_irq_interrupt();
1197 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1198 smp_call_function_interrupt();
1199 set_irq_regs(old_regs);
1203 do_flush_tlb_all(void* info)
1205 unsigned long cpu = smp_processor_id();
1208 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1213 /* flush the TLB of every active CPU in the system */
1217 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1220 /* used to set up the trampoline for other CPUs when the memory manager
1223 smp_alloc_memory(void)
1225 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1226 if(__pa(trampoline_base) >= 0x93000)
1230 /* send a reschedule CPI to one CPU by physical CPU number*/
1232 smp_send_reschedule(int cpu)
1234 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1239 hard_smp_processor_id(void)
1242 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1243 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1244 return cpumask & 0x1F;
1246 for(i = 0; i < 8; i++) {
1247 if(cpumask & (1<<i))
1250 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1255 safe_smp_processor_id(void)
1257 return hard_smp_processor_id();
1260 /* broadcast a halt to all other CPUs */
1264 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1267 /* this function is triggered in time.c when a clock tick fires
1268 * we need to re-broadcast the tick to all CPUs */
1270 smp_vic_timer_interrupt(struct pt_regs *regs)
1272 struct pt_regs *old_regs = set_irq_regs(regs);
1273 send_CPI_allbutself(VIC_TIMER_CPI);
1274 smp_local_timer_interrupt();
1275 set_irq_regs(old_regs);
1278 /* local (per CPU) timer interrupt. It does both profiling and
1279 * process statistics/rescheduling.
1281 * We do profiling in every local tick, statistics/rescheduling
1282 * happen only every 'profiling multiplier' ticks. The default
1283 * multiplier is 1 and it can be changed by writing the new multiplier
1284 * value into /proc/profile.
1287 smp_local_timer_interrupt(void)
1289 int cpu = smp_processor_id();
1292 profile_tick(CPU_PROFILING);
1293 if (--per_cpu(prof_counter, cpu) <= 0) {
1295 * The multiplier may have changed since the last time we got
1296 * to this point as a result of the user writing to
1297 * /proc/profile. In this case we need to adjust the APIC
1298 * timer accordingly.
1300 * Interrupts are already masked off at this point.
1302 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1303 if (per_cpu(prof_counter, cpu) !=
1304 per_cpu(prof_old_multiplier, cpu)) {
1305 /* FIXME: need to update the vic timer tick here */
1306 per_cpu(prof_old_multiplier, cpu) =
1307 per_cpu(prof_counter, cpu);
1310 update_process_times(user_mode_vm(irq_regs));
1313 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1314 /* only extended VIC processors participate in
1315 * interrupt distribution */
1319 * We take the 'long' return path, and there every subsystem
1320 * grabs the apropriate locks (kernel lock/ irq lock).
1322 * we might want to decouple profiling from the 'long path',
1323 * and do the profiling totally in assembly.
1325 * Currently this isn't too much of an issue (performance wise),
1326 * we can take more than 100K local irqs per second on a 100 MHz P5.
1329 if((++vic_tick[cpu] & 0x7) != 0)
1331 /* get here every 16 ticks (about every 1/6 of a second) */
1333 /* Change our priority to give someone else a chance at getting
1334 * the IRQ. The algorithm goes like this:
1336 * In the VIC, the dynamically routed interrupt is always
1337 * handled by the lowest priority eligible (i.e. receiving
1338 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1339 * lowest processor number gets it.
1341 * The priority of a CPU is controlled by a special per-CPU
1342 * VIC priority register which is 3 bits wide 0 being lowest
1343 * and 7 highest priority..
1345 * Therefore we subtract the average number of interrupts from
1346 * the number we've fielded. If this number is negative, we
1347 * lower the activity count and if it is positive, we raise
1350 * I'm afraid this still leads to odd looking interrupt counts:
1351 * the totals are all roughly equal, but the individual ones
1352 * look rather skewed.
1354 * FIXME: This algorithm is total crap when mixed with SMP
1355 * affinity code since we now try to even up the interrupt
1356 * counts when an affinity binding is keeping them on a
1358 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1359 - vic_intr_total) >> 4;
1366 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1368 #ifdef VOYAGER_DEBUG
1369 if((vic_tick[cpu] & 0xFFF) == 0) {
1370 /* print this message roughly every 25 secs */
1371 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1372 cpu, vic_tick[cpu], weight);
1377 /* setup the profiling timer */
1379 setup_profiling_timer(unsigned int multiplier)
1387 * Set the new multiplier for each CPU. CPUs don't start using the
1388 * new values until the next timer interrupt in which they do process
1391 for (i = 0; i < NR_CPUS; ++i)
1392 per_cpu(prof_multiplier, i) = multiplier;
1397 /* This is a bit of a mess, but forced on us by the genirq changes
1398 * there's no genirq handler that really does what voyager wants
1399 * so hack it up with the simple IRQ handler */
1400 static void fastcall
1401 handle_vic_irq(unsigned int irq, struct irq_desc *desc)
1403 before_handle_vic_irq(irq);
1404 handle_simple_irq(irq, desc);
1405 after_handle_vic_irq(irq);
1409 /* The CPIs are handled in the per cpu 8259s, so they must be
1410 * enabled to be received: FIX: enabling the CPIs in the early
1411 * boot sequence interferes with bug checking; enable them later
1413 #define VIC_SET_GATE(cpi, vector) \
1414 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1415 #define QIC_SET_GATE(cpi, vector) \
1416 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1423 /* initialize the per cpu irq mask to all disabled */
1424 for(i = 0; i < NR_CPUS; i++)
1425 vic_irq_mask[i] = 0xFFFF;
1427 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1429 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1430 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1432 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1433 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1434 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1435 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1436 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1439 /* now put the VIC descriptor into the first 48 IRQs
1441 * This is for later: first 16 correspond to PC IRQs; next 16
1442 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1443 for(i = 0; i < 48; i++)
1444 set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
1447 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1448 * processor to receive CPI */
1450 send_CPI(__u32 cpuset, __u8 cpi)
1453 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1455 if(cpi < VIC_START_FAKE_CPI) {
1456 /* fake CPI are only used for booting, so send to the
1457 * extended quads as well---Quads must be VIC booted */
1458 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1462 send_QIC_CPI(quad_cpuset, cpi);
1463 cpuset &= ~quad_cpuset;
1464 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1467 for_each_online_cpu(cpu) {
1468 if(cpuset & (1<<cpu))
1469 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1472 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1475 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1476 * set the cache line to shared by reading it.
1478 * DON'T make this inline otherwise the cache line read will be
1482 ack_QIC_CPI(__u8 cpi) {
1483 __u8 cpu = hard_smp_processor_id();
1487 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1488 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1492 ack_special_QIC_CPI(__u8 cpi)
1496 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1499 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1502 /* also clear at the VIC, just in case (nop for non-extended proc) */
1506 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1508 ack_VIC_CPI(__u8 cpi)
1510 #ifdef VOYAGER_DEBUG
1511 unsigned long flags;
1513 __u8 cpu = smp_processor_id();
1515 local_irq_save(flags);
1516 isr = vic_read_isr();
1517 if((isr & (1<<(cpi &7))) == 0) {
1518 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1521 /* send specific EOI; the two system interrupts have
1522 * bit 4 set for a separate vector but behave as the
1523 * corresponding 3 bit intr */
1524 outb_p(0x60|(cpi & 7),0x20);
1526 #ifdef VOYAGER_DEBUG
1527 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1528 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1530 local_irq_restore(flags);
1534 /* cribbed with thanks from irq.c */
1535 #define __byte(x,y) (((unsigned char *)&(y))[x])
1536 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1537 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1540 startup_vic_irq(unsigned int irq)
1542 unmask_vic_irq(irq);
1547 /* The enable and disable routines. This is where we run into
1548 * conflicting architectural philosophy. Fundamentally, the voyager
1549 * architecture does not expect to have to disable interrupts globally
1550 * (the IRQ controllers belong to each CPU). The processor masquerade
1551 * which is used to start the system shouldn't be used in a running OS
1552 * since it will cause great confusion if two separate CPUs drive to
1553 * the same IRQ controller (I know, I've tried it).
1555 * The solution is a variant on the NCR lazy SPL design:
1557 * 1) To disable an interrupt, do nothing (other than set the
1558 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1560 * 2) If the interrupt dares to come in, raise the local mask against
1561 * it (this will result in all the CPU masks being raised
1564 * 3) To enable the interrupt, lower the mask on the local CPU and
1565 * broadcast an Interrupt enable CPI which causes all other CPUs to
1566 * adjust their masks accordingly. */
1569 unmask_vic_irq(unsigned int irq)
1571 /* linux doesn't to processor-irq affinity, so enable on
1572 * all CPUs we know about */
1573 int cpu = smp_processor_id(), real_cpu;
1574 __u16 mask = (1<<irq);
1575 __u32 processorList = 0;
1576 unsigned long flags;
1578 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1579 irq, cpu, cpu_irq_affinity[cpu]));
1580 spin_lock_irqsave(&vic_irq_lock, flags);
1581 for_each_online_cpu(real_cpu) {
1582 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1584 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1585 /* irq has no affinity for this CPU, ignore */
1588 if(real_cpu == cpu) {
1589 enable_local_vic_irq(irq);
1591 else if(vic_irq_mask[real_cpu] & mask) {
1592 vic_irq_enable_mask[real_cpu] |= mask;
1593 processorList |= (1<<real_cpu);
1596 spin_unlock_irqrestore(&vic_irq_lock, flags);
1598 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1602 mask_vic_irq(unsigned int irq)
1604 /* lazy disable, do nothing */
1608 enable_local_vic_irq(unsigned int irq)
1610 __u8 cpu = smp_processor_id();
1611 __u16 mask = ~(1 << irq);
1612 __u16 old_mask = vic_irq_mask[cpu];
1614 vic_irq_mask[cpu] &= mask;
1615 if(vic_irq_mask[cpu] == old_mask)
1618 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1622 outb_p(cached_A1(cpu),0xA1);
1626 outb_p(cached_21(cpu),0x21);
1632 disable_local_vic_irq(unsigned int irq)
1634 __u8 cpu = smp_processor_id();
1635 __u16 mask = (1 << irq);
1636 __u16 old_mask = vic_irq_mask[cpu];
1641 vic_irq_mask[cpu] |= mask;
1642 if(old_mask == vic_irq_mask[cpu])
1645 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1649 outb_p(cached_A1(cpu),0xA1);
1653 outb_p(cached_21(cpu),0x21);
1658 /* The VIC is level triggered, so the ack can only be issued after the
1659 * interrupt completes. However, we do Voyager lazy interrupt
1660 * handling here: It is an extremely expensive operation to mask an
1661 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1662 * this interrupt actually comes in, then we mask and ack here to push
1663 * the interrupt off to another CPU */
1665 before_handle_vic_irq(unsigned int irq)
1667 irq_desc_t *desc = irq_desc + irq;
1668 __u8 cpu = smp_processor_id();
1670 _raw_spin_lock(&vic_irq_lock);
1672 vic_intr_count[cpu]++;
1674 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1675 /* The irq is not in our affinity mask, push it off
1676 * onto another CPU */
1677 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1679 disable_local_vic_irq(irq);
1680 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1681 * actually calling the interrupt routine */
1682 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1683 } else if(desc->status & IRQ_DISABLED) {
1684 /* Damn, the interrupt actually arrived, do the lazy
1685 * disable thing. The interrupt routine in irq.c will
1686 * not handle a IRQ_DISABLED interrupt, so nothing more
1687 * need be done here */
1688 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1690 disable_local_vic_irq(irq);
1691 desc->status |= IRQ_REPLAY;
1693 desc->status &= ~IRQ_REPLAY;
1696 _raw_spin_unlock(&vic_irq_lock);
1699 /* Finish the VIC interrupt: basically mask */
1701 after_handle_vic_irq(unsigned int irq)
1703 irq_desc_t *desc = irq_desc + irq;
1705 _raw_spin_lock(&vic_irq_lock);
1707 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1708 #ifdef VOYAGER_DEBUG
1712 desc->status = status;
1713 if ((status & IRQ_DISABLED))
1714 disable_local_vic_irq(irq);
1715 #ifdef VOYAGER_DEBUG
1716 /* DEBUG: before we ack, check what's in progress */
1717 isr = vic_read_isr();
1718 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1720 __u8 cpu = smp_processor_id();
1722 int mask; /* Um... initialize me??? --RR */
1724 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1726 for_each_possible_cpu(real_cpu, mask) {
1728 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1730 isr = vic_read_isr();
1731 if(isr & (1<<irq)) {
1732 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1736 outb(cpu, VIC_PROCESSOR_ID);
1739 #endif /* VOYAGER_DEBUG */
1740 /* as soon as we ack, the interrupt is eligible for
1741 * receipt by another CPU so everything must be in
1744 if(status & IRQ_REPLAY) {
1745 /* replay is set if we disable the interrupt
1746 * in the before_handle_vic_irq() routine, so
1747 * clear the in progress bit here to allow the
1748 * next CPU to handle this correctly */
1749 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1751 #ifdef VOYAGER_DEBUG
1752 isr = vic_read_isr();
1753 if((isr & (1<<irq)) != 0)
1754 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1756 #endif /* VOYAGER_DEBUG */
1758 _raw_spin_unlock(&vic_irq_lock);
1760 /* All code after this point is out of the main path - the IRQ
1761 * may be intercepted by another CPU if reasserted */
1765 /* Linux processor - interrupt affinity manipulations.
1767 * For each processor, we maintain a 32 bit irq affinity mask.
1768 * Initially it is set to all 1's so every processor accepts every
1769 * interrupt. In this call, we change the processor's affinity mask:
1771 * Change from enable to disable:
1773 * If the interrupt ever comes in to the processor, we will disable it
1774 * and ack it to push it off to another CPU, so just accept the mask here.
1776 * Change from disable to enable:
1778 * change the mask and then do an interrupt enable CPI to re-enable on
1779 * the selected processors */
1782 set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1784 /* Only extended processors handle interrupts */
1785 unsigned long real_mask;
1786 unsigned long irq_mask = 1 << irq;
1789 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1791 if(cpus_addr(mask)[0] == 0)
1792 /* can't have no cpu's to accept the interrupt -- extremely
1793 * bad things will happen */
1797 /* can't change the affinity of the timer IRQ. This
1798 * is due to the constraint in the voyager
1799 * architecture that the CPI also comes in on and IRQ
1800 * line and we have chosen IRQ0 for this. If you
1801 * raise the mask on this interrupt, the processor
1802 * will no-longer be able to accept VIC CPIs */
1806 /* You can only have 32 interrupts in a voyager system
1807 * (and 32 only if you have a secondary microchannel
1811 for_each_online_cpu(cpu) {
1812 unsigned long cpu_mask = 1 << cpu;
1814 if(cpu_mask & real_mask) {
1815 /* enable the interrupt for this cpu */
1816 cpu_irq_affinity[cpu] |= irq_mask;
1818 /* disable the interrupt for this cpu */
1819 cpu_irq_affinity[cpu] &= ~irq_mask;
1822 /* this is magic, we now have the correct affinity maps, so
1823 * enable the interrupt. This will send an enable CPI to
1824 * those cpu's who need to enable it in their local masks,
1825 * causing them to correct for the new affinity . If the
1826 * interrupt is currently globally disabled, it will simply be
1827 * disabled again as it comes in (voyager lazy disable). If
1828 * the affinity map is tightened to disable the interrupt on a
1829 * cpu, it will be pushed off when it comes in */
1830 unmask_vic_irq(irq);
1834 ack_vic_irq(unsigned int irq)
1837 outb(0x62,0x20); /* Specific EOI to cascade */
1838 outb(0x60|(irq & 7),0xA0);
1840 outb(0x60 | (irq & 7),0x20);
1844 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1845 * but are not vectored by it. This means that the 8259 mask must be
1846 * lowered to receive them */
1848 vic_enable_cpi(void)
1850 __u8 cpu = smp_processor_id();
1852 /* just take a copy of the current mask (nop for boot cpu) */
1853 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1855 enable_local_vic_irq(VIC_CPI_LEVEL0);
1856 enable_local_vic_irq(VIC_CPI_LEVEL1);
1857 /* for sys int and cmn int */
1858 enable_local_vic_irq(7);
1861 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1862 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1863 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1864 cpu, QIC_CPI_ENABLE));
1867 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1868 cpu, vic_irq_mask[cpu]));
1874 int old_cpu = smp_processor_id(), cpu;
1876 /* dump the interrupt masks of each processor */
1877 for_each_online_cpu(cpu) {
1878 __u16 imr, isr, irr;
1879 unsigned long flags;
1881 local_irq_save(flags);
1882 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1883 imr = (inb(0xa1) << 8) | inb(0x21);
1885 irr = inb(0xa0) << 8;
1889 isr = inb(0xa0) << 8;
1892 outb(old_cpu, VIC_PROCESSOR_ID);
1893 local_irq_restore(flags);
1894 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1895 cpu, vic_irq_mask[cpu], imr, irr, isr);
1897 /* These lines are put in to try to unstick an un ack'd irq */
1900 for(irq=0; irq<16; irq++) {
1901 if(isr & (1<<irq)) {
1902 printk("\tCPU%d: ack irq %d\n",
1904 local_irq_save(flags);
1905 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1908 outb(old_cpu, VIC_PROCESSOR_ID);
1909 local_irq_restore(flags);
1918 smp_voyager_power_off(void *dummy)
1920 if(smp_processor_id() == boot_cpu_id)
1921 voyager_power_off();
1923 smp_stop_cpu_function(NULL);
1927 smp_prepare_cpus(unsigned int max_cpus)
1929 /* FIXME: ignore max_cpus for now */
1933 void __devinit smp_prepare_boot_cpu(void)
1935 cpu_set(smp_processor_id(), cpu_online_map);
1936 cpu_set(smp_processor_id(), cpu_callout_map);
1937 cpu_set(smp_processor_id(), cpu_possible_map);
1938 cpu_set(smp_processor_id(), cpu_present_map);
1942 __cpu_up(unsigned int cpu)
1944 /* This only works at boot for x86. See "rewrite" above. */
1945 if (cpu_isset(cpu, smp_commenced_mask))
1948 /* In case one didn't come up */
1949 if (!cpu_isset(cpu, cpu_callin_map))
1951 /* Unleash the CPU! */
1952 cpu_set(cpu, smp_commenced_mask);
1953 while (!cpu_isset(cpu, cpu_online_map))
1959 smp_cpus_done(unsigned int max_cpus)
1965 smp_setup_processor_id(void)
1967 current_thread_info()->cpu = hard_smp_processor_id();