2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
30 #include <asm/bootinfo.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
33 #include <asm/setup.h>
35 #include <asm/traps.h>
36 #include <asm/machdep.h>
37 #include <asm/q40_master.h>
39 extern irqreturn_t q40_process_int (int level, struct pt_regs *regs);
40 extern void q40_init_IRQ (void);
41 extern void q40_free_irq (unsigned int, void *);
42 extern int show_q40_interrupts (struct seq_file *, void *);
43 extern void q40_enable_irq (unsigned int);
44 extern void q40_disable_irq (unsigned int);
45 static void q40_get_model(char *model);
46 static int q40_get_hardware_list(char *buffer);
47 extern int q40_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id);
48 extern void q40_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
50 extern unsigned long q40_gettimeoffset (void);
51 extern int q40_hwclk (int, struct rtc_time *);
52 extern unsigned int q40_get_ss (void);
53 extern int q40_set_clock_mmss (unsigned long);
54 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
55 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
56 extern void q40_reset (void);
58 extern void q40_waitbut(void);
59 void q40_set_vectors (void);
61 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
63 extern char m68k_debug_device[];
64 static void q40_mem_console_write(struct console *co, const char *b,
69 static struct console q40_console_driver = {
71 .flags = CON_PRINTBUFFER,
76 /* early debugging function:*/
77 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
80 static void q40_mem_console_write(struct console *co, const char *s,
93 void printq40(char *str)
98 while (l-- >0 && _cpleft-- >0)
109 #ifdef CONFIG_HEARTBEAT
110 static void q40_heartbeat(int on)
124 printk ("\n\n*******************************************\n"
125 "Called q40_reset : press the RESET button!! \n"
126 "*******************************************\n");
133 printk ("\n\n*******************\n"
135 "*******************\n");
140 static void q40_get_model(char *model)
142 sprintf(model, "Q40");
145 /* No hardware options on Q40? */
147 static int q40_get_hardware_list(char *buffer)
153 static unsigned int serports[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
154 void q40_disable_irqs(void)
159 while((i=serports[j++])) outb(0,i+UART_IER);
160 master_outb(0,EXT_ENABLE_REG);
161 master_outb(0,KEY_IRQ_ENABLE_REG);
164 void __init config_q40(void)
166 mach_sched_init = q40_sched_init;
168 mach_init_IRQ = q40_init_IRQ;
169 mach_gettimeoffset = q40_gettimeoffset;
170 mach_hwclk = q40_hwclk;
171 mach_get_ss = q40_get_ss;
172 mach_get_rtc_pll = q40_get_rtc_pll;
173 mach_set_rtc_pll = q40_set_rtc_pll;
174 mach_set_clock_mmss = q40_set_clock_mmss;
176 mach_reset = q40_reset;
177 mach_free_irq = q40_free_irq;
178 mach_process_int = q40_process_int;
179 mach_get_irq_list = show_q40_interrupts;
180 mach_request_irq = q40_request_irq;
181 enable_irq = q40_enable_irq;
182 disable_irq = q40_disable_irq;
183 mach_get_model = q40_get_model;
184 mach_get_hardware_list = q40_get_hardware_list;
186 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
187 mach_beep = q40_mksound;
189 #ifdef CONFIG_HEARTBEAT
190 mach_heartbeat = q40_heartbeat;
192 mach_halt = q40_halt;
194 /* disable a few things that SMSQ might have left enabled */
197 /* no DMA at all, but ide-scsi requires it.. make sure
198 * all physical RAM fits into the boundary - otherwise
199 * allocator may play costly and useless tricks */
200 mach_max_dma_address = 1024*1024*1024;
202 /* useful for early debugging stages - writes kernel messages into SRAM */
203 if (!strncmp( m68k_debug_device,"mem",3 ))
205 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
206 _cpleft=2000-((long)q40_mem_cptr-0xff020000)/4;
207 q40_console_driver.write = q40_mem_console_write;
208 register_console(&q40_console_driver);
213 int q40_parse_bootinfo(const struct bi_record *rec)
219 static inline unsigned char bcd2bin (unsigned char b)
221 return ((b>>4)*10 + (b&15));
224 static inline unsigned char bin2bcd (unsigned char b)
226 return (((b/10)*16) + (b%10));
230 unsigned long q40_gettimeoffset (void)
232 return 5000*(ql_ticks!=0);
237 * Looks like op is non-zero for setting the clock, and zero for
240 * struct hwclk_time {
241 * unsigned sec; 0..59
242 * unsigned min; 0..59
243 * unsigned hour; 0..23
244 * unsigned day; 1..31
245 * unsigned mon; 0..11
246 * unsigned year; 00...
247 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
251 int q40_hwclk(int op, struct rtc_time *t)
255 Q40_RTC_CTRL |= Q40_RTC_WRITE;
257 Q40_RTC_SECS = bin2bcd(t->tm_sec);
258 Q40_RTC_MINS = bin2bcd(t->tm_min);
259 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
260 Q40_RTC_DATE = bin2bcd(t->tm_mday);
261 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
262 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
264 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
266 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
270 Q40_RTC_CTRL |= Q40_RTC_READ;
272 t->tm_year = bcd2bin (Q40_RTC_YEAR);
273 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
274 t->tm_mday = bcd2bin (Q40_RTC_DATE);
275 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
276 t->tm_min = bcd2bin (Q40_RTC_MINS);
277 t->tm_sec = bcd2bin (Q40_RTC_SECS);
279 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
283 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
290 unsigned int q40_get_ss(void)
292 return bcd2bin(Q40_RTC_SECS);
296 * Set the minutes and seconds from seconds value 'nowtime'. Fail if
297 * clock is out by > 30 minutes. Logic lifted from atari code.
300 int q40_set_clock_mmss (unsigned long nowtime)
303 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
308 rtc_minutes = bcd2bin (Q40_RTC_MINS);
310 if ((rtc_minutes < real_minutes
311 ? real_minutes - rtc_minutes
312 : rtc_minutes - real_minutes) < 30)
314 Q40_RTC_CTRL |= Q40_RTC_WRITE;
315 Q40_RTC_MINS = bin2bcd(real_minutes);
316 Q40_RTC_SECS = bin2bcd(real_seconds);
317 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
327 /* get and set PLL calibration of RTC clock */
328 #define Q40_RTC_PLL_MASK ((1<<5)-1)
329 #define Q40_RTC_PLL_SIGN (1<<5)
331 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
333 int tmp=Q40_RTC_CTRL;
334 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
335 if (tmp & Q40_RTC_PLL_SIGN)
336 pll->pll_value = -pll->pll_value;
339 pll->pll_posmult=512;
340 pll->pll_negmult=256;
341 pll->pll_clock=125829120;
345 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
348 /* the docs are a bit unclear so I am doublesetting */
349 /* RTC_WRITE here ... */
350 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
352 Q40_RTC_CTRL |= Q40_RTC_WRITE;
354 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);