arch/mips/dec/setup.c

   1 /*
   2  * System-specific setup, especially interrupts.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1998 Harald Koerfgen
   9  * Copyright (C) 2000, 2001, 2002, 2003, 2005  Maciej W. Rozycki
  10  */
  11 #include <linux/console.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/ioport.h>
  15 #include <linux/module.h>
  16 #include <linux/param.h>
  17 #include <linux/sched.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/types.h>
  20
  21 #include <asm/bootinfo.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/irq.h>
  25 #include <asm/irq_cpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/reboot.h>
  28 #include <asm/time.h>
  29 #include <asm/traps.h>
  30 #include <asm/wbflush.h>
  31
  32 #include <asm/dec/interrupts.h>
  33 #include <asm/dec/ioasic.h>
  34 #include <asm/dec/ioasic_addrs.h>
  35 #include <asm/dec/ioasic_ints.h>
  36 #include <asm/dec/kn01.h>
  37 #include <asm/dec/kn02.h>
  38 #include <asm/dec/kn02ba.h>
  39 #include <asm/dec/kn02ca.h>
  40 #include <asm/dec/kn03.h>
  41 #include <asm/dec/kn230.h>
  42
  43
  44 extern void dec_machine_restart(char *command);
  45 extern void dec_machine_halt(void);
  46 extern void dec_machine_power_off(void);
  47 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
  48
  49 extern asmlinkage void decstation_handle_int(void);
  50
  51 spinlock_t ioasic_ssr_lock;
  52
  53 volatile u32 *ioasic_base;
  54 unsigned long dec_kn_slot_size;
  55
  56 /*
  57  * IRQ routing and priority tables.  Priorites are set as follows:
  58  *
  59  *              KN01    KN230   KN02    KN02-BA KN02-CA KN03
  60  *
  61  * MEMORY       CPU     CPU     CPU     ASIC    CPU     CPU
  62  * RTC          CPU     CPU     CPU     ASIC    CPU     CPU
  63  * DMA          -       -       -       ASIC    ASIC    ASIC
  64  * SERIAL0      CPU     CPU     CSR     ASIC    ASIC    ASIC
  65  * SERIAL1      -       -       -       ASIC    -       ASIC
  66  * SCSI         CPU     CPU     CSR     ASIC    ASIC    ASIC
  67  * ETHERNET     CPU     *       CSR     ASIC    ASIC    ASIC
  68  * other        -       -       -       ASIC    -       -
  69  * TC2          -       -       CSR     CPU     ASIC    ASIC
  70  * TC1          -       -       CSR     CPU     ASIC    ASIC
  71  * TC0          -       -       CSR     CPU     ASIC    ASIC
  72  * other        -       CPU     -       CPU     ASIC    ASIC
  73  * other        -       -       -       -       CPU     CPU
  74  *
  75  * * -- shared with SCSI
  76  */
  77
  78 int dec_interrupt[DEC_NR_INTS] = {
  79         [0 ... DEC_NR_INTS - 1] = -1
  80 };
  81 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
  82         { { .i = ~0 }, { .p = dec_intr_unimplemented } },
  83 };
  84 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
  85         { { .i = ~0 }, { .p = asic_intr_unimplemented } },
  86 };
  87 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
  88
  89 static struct irqaction ioirq = {
  90         .handler = no_action,
  91         .name = "cascade",
  92 };
  93 static struct irqaction fpuirq = {
  94         .handler = no_action,
  95         .name = "fpu",
  96 };
  97
  98 static struct irqaction busirq = {
  99         .flags = SA_INTERRUPT,
 100         .name = "bus error",
 101 };
 102
 103 static struct irqaction haltirq = {
 104         .handler = dec_intr_halt,
 105         .name = "halt",
 106 };
 107
 108
 109 /*
 110  * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
 111  */
 112 void __init dec_be_init(void)
 113 {
 114         switch (mips_machtype) {
 115         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 116                 busirq.flags |= SA_SHIRQ;
 117                 break;
 118         case MACH_DS5000_200:   /* DS5000/200 3max */
 119         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 120         case MACH_DS5900:       /* DS5900 bigmax */
 121                 board_be_handler = dec_ecc_be_handler;
 122                 busirq.handler = dec_ecc_be_interrupt;
 123                 dec_ecc_be_init();
 124                 break;
 125         }
 126 }
 127
 128
 129 extern void dec_time_init(void);
 130 extern void dec_timer_setup(struct irqaction *);
 131
 132 void __init plat_setup(void)
 133 {
 134         board_be_init = dec_be_init;
 135         board_time_init = dec_time_init;
 136         board_timer_setup = dec_timer_setup;
 137
 138         wbflush_setup();
 139
 140         _machine_restart = dec_machine_restart;
 141         _machine_halt = dec_machine_halt;
 142         _machine_power_off = dec_machine_power_off;
 143
 144         ioport_resource.start = ~0UL;
 145         ioport_resource.end = 0UL;
 146 }
 147
 148 /*
 149  * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
 150  * or DS3100 (aka Pmax).
 151  */
 152 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
 153         [DEC_IRQ_CASCADE]       = -1,
 154         [DEC_IRQ_AB_RECV]       = -1,
 155         [DEC_IRQ_AB_XMIT]       = -1,
 156         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
 157         [DEC_IRQ_ASC]           = -1,
 158         [DEC_IRQ_FLOPPY]        = -1,
 159         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 160         [DEC_IRQ_HALT]          = -1,
 161         [DEC_IRQ_ISDN]          = -1,
 162         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
 163         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
 164         [DEC_IRQ_PSU]           = -1,
 165         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
 166         [DEC_IRQ_SCC0]          = -1,
 167         [DEC_IRQ_SCC1]          = -1,
 168         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
 169         [DEC_IRQ_TC0]           = -1,
 170         [DEC_IRQ_TC1]           = -1,
 171         [DEC_IRQ_TC2]           = -1,
 172         [DEC_IRQ_TIMER]         = -1,
 173         [DEC_IRQ_VIDEO]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
 174         [DEC_IRQ_ASC_MERR]      = -1,
 175         [DEC_IRQ_ASC_ERR]       = -1,
 176         [DEC_IRQ_ASC_DMA]       = -1,
 177         [DEC_IRQ_FLOPPY_ERR]    = -1,
 178         [DEC_IRQ_ISDN_ERR]      = -1,
 179         [DEC_IRQ_ISDN_RXDMA]    = -1,
 180         [DEC_IRQ_ISDN_TXDMA]    = -1,
 181         [DEC_IRQ_LANCE_MERR]    = -1,
 182         [DEC_IRQ_SCC0A_RXERR]   = -1,
 183         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 184         [DEC_IRQ_SCC0A_TXERR]   = -1,
 185         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 186         [DEC_IRQ_AB_RXERR]      = -1,
 187         [DEC_IRQ_AB_RXDMA]      = -1,
 188         [DEC_IRQ_AB_TXERR]      = -1,
 189         [DEC_IRQ_AB_TXDMA]      = -1,
 190         [DEC_IRQ_SCC1A_RXERR]   = -1,
 191         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 192         [DEC_IRQ_SCC1A_TXERR]   = -1,
 193         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 194 };
 195
 196 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
 197         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
 198                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
 199         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
 200                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
 201         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
 202                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
 203         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
 204                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
 205         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
 206                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
 207         { { .i = DEC_CPU_IRQ_ALL },
 208                 { .p = cpu_all_int } },
 209 };
 210
 211 void __init dec_init_kn01(void)
 212 {
 213         /* IRQ routing. */
 214         memcpy(&dec_interrupt, &kn01_interrupt,
 215                 sizeof(kn01_interrupt));
 216
 217         /* CPU IRQ priorities. */
 218         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
 219                 sizeof(kn01_cpu_mask_nr_tbl));
 220
 221         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 222
 223 }                               /* dec_init_kn01 */
 224
 225
 226 /*
 227  * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
 228  */
 229 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
 230         [DEC_IRQ_CASCADE]       = -1,
 231         [DEC_IRQ_AB_RECV]       = -1,
 232         [DEC_IRQ_AB_XMIT]       = -1,
 233         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
 234         [DEC_IRQ_ASC]           = -1,
 235         [DEC_IRQ_FLOPPY]        = -1,
 236         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 237         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
 238         [DEC_IRQ_ISDN]          = -1,
 239         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
 240         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
 241         [DEC_IRQ_PSU]           = -1,
 242         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
 243         [DEC_IRQ_SCC0]          = -1,
 244         [DEC_IRQ_SCC1]          = -1,
 245         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
 246         [DEC_IRQ_TC0]           = -1,
 247         [DEC_IRQ_TC1]           = -1,
 248         [DEC_IRQ_TC2]           = -1,
 249         [DEC_IRQ_TIMER]         = -1,
 250         [DEC_IRQ_VIDEO]         = -1,
 251         [DEC_IRQ_ASC_MERR]      = -1,
 252         [DEC_IRQ_ASC_ERR]       = -1,
 253         [DEC_IRQ_ASC_DMA]       = -1,
 254         [DEC_IRQ_FLOPPY_ERR]    = -1,
 255         [DEC_IRQ_ISDN_ERR]      = -1,
 256         [DEC_IRQ_ISDN_RXDMA]    = -1,
 257         [DEC_IRQ_ISDN_TXDMA]    = -1,
 258         [DEC_IRQ_LANCE_MERR]    = -1,
 259         [DEC_IRQ_SCC0A_RXERR]   = -1,
 260         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 261         [DEC_IRQ_SCC0A_TXERR]   = -1,
 262         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 263         [DEC_IRQ_AB_RXERR]      = -1,
 264         [DEC_IRQ_AB_RXDMA]      = -1,
 265         [DEC_IRQ_AB_TXERR]      = -1,
 266         [DEC_IRQ_AB_TXDMA]      = -1,
 267         [DEC_IRQ_SCC1A_RXERR]   = -1,
 268         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 269         [DEC_IRQ_SCC1A_TXERR]   = -1,
 270         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 271 };
 272
 273 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
 274         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
 275                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
 276         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
 277                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
 278         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
 279                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
 280         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
 281                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
 282         { { .i = DEC_CPU_IRQ_ALL },
 283                 { .p = cpu_all_int } },
 284 };
 285
 286 void __init dec_init_kn230(void)
 287 {
 288         /* IRQ routing. */
 289         memcpy(&dec_interrupt, &kn230_interrupt,
 290                 sizeof(kn230_interrupt));
 291
 292         /* CPU IRQ priorities. */
 293         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
 294                 sizeof(kn230_cpu_mask_nr_tbl));
 295
 296         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 297
 298 }                               /* dec_init_kn230 */
 299
 300
 301 /*
 302  * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
 303  */
 304 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
 305         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
 306         [DEC_IRQ_AB_RECV]       = -1,
 307         [DEC_IRQ_AB_XMIT]       = -1,
 308         [DEC_IRQ_DZ11]          = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
 309         [DEC_IRQ_ASC]           = KN02_IRQ_NR(KN02_CSR_INR_ASC),
 310         [DEC_IRQ_FLOPPY]        = -1,
 311         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 312         [DEC_IRQ_HALT]          = -1,
 313         [DEC_IRQ_ISDN]          = -1,
 314         [DEC_IRQ_LANCE]         = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
 315         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
 316         [DEC_IRQ_PSU]           = -1,
 317         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
 318         [DEC_IRQ_SCC0]          = -1,
 319         [DEC_IRQ_SCC1]          = -1,
 320         [DEC_IRQ_SII]           = -1,
 321         [DEC_IRQ_TC0]           = KN02_IRQ_NR(KN02_CSR_INR_TC0),
 322         [DEC_IRQ_TC1]           = KN02_IRQ_NR(KN02_CSR_INR_TC1),
 323         [DEC_IRQ_TC2]           = KN02_IRQ_NR(KN02_CSR_INR_TC2),
 324         [DEC_IRQ_TIMER]         = -1,
 325         [DEC_IRQ_VIDEO]         = -1,
 326         [DEC_IRQ_ASC_MERR]      = -1,
 327         [DEC_IRQ_ASC_ERR]       = -1,
 328         [DEC_IRQ_ASC_DMA]       = -1,
 329         [DEC_IRQ_FLOPPY_ERR]    = -1,
 330         [DEC_IRQ_ISDN_ERR]      = -1,
 331         [DEC_IRQ_ISDN_RXDMA]    = -1,
 332         [DEC_IRQ_ISDN_TXDMA]    = -1,
 333         [DEC_IRQ_LANCE_MERR]    = -1,
 334         [DEC_IRQ_SCC0A_RXERR]   = -1,
 335         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 336         [DEC_IRQ_SCC0A_TXERR]   = -1,
 337         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 338         [DEC_IRQ_AB_RXERR]      = -1,
 339         [DEC_IRQ_AB_RXDMA]      = -1,
 340         [DEC_IRQ_AB_TXERR]      = -1,
 341         [DEC_IRQ_AB_TXDMA]      = -1,
 342         [DEC_IRQ_SCC1A_RXERR]   = -1,
 343         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 344         [DEC_IRQ_SCC1A_TXERR]   = -1,
 345         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 346 };
 347
 348 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
 349         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
 350                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
 351         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
 352                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
 353         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
 354                 { .p = kn02_io_int } },
 355         { { .i = DEC_CPU_IRQ_ALL },
 356                 { .p = cpu_all_int } },
 357 };
 358
 359 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
 360         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
 361                 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
 362         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
 363                 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
 364         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
 365                 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
 366         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
 367                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
 368         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
 369                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
 370         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
 371                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
 372         { { .i = KN02_IRQ_ALL },
 373                 { .p = kn02_all_int } },
 374 };
 375
 376 void __init dec_init_kn02(void)
 377 {
 378         /* IRQ routing. */
 379         memcpy(&dec_interrupt, &kn02_interrupt,
 380                 sizeof(kn02_interrupt));
 381
 382         /* CPU IRQ priorities. */
 383         memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
 384                 sizeof(kn02_cpu_mask_nr_tbl));
 385
 386         /* KN02 CSR IRQ priorities. */
 387         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
 388                 sizeof(kn02_asic_mask_nr_tbl));
 389
 390         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 391         init_kn02_irqs(KN02_IRQ_BASE);
 392
 393 }                               /* dec_init_kn02 */
 394
 395
 396 /*
 397  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 398  * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
 399  * DS5000/150, aka 4min.
 400  */
 401 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
 402         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
 403         [DEC_IRQ_AB_RECV]       = -1,
 404         [DEC_IRQ_AB_XMIT]       = -1,
 405         [DEC_IRQ_DZ11]          = -1,
 406         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02BA_IO_INR_ASC),
 407         [DEC_IRQ_FLOPPY]        = -1,
 408         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 409         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
 410         [DEC_IRQ_ISDN]          = -1,
 411         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
 412         [DEC_IRQ_BUS]           = IO_IRQ_NR(KN02BA_IO_INR_BUS),
 413         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN02BA_IO_INR_PSU),
 414         [DEC_IRQ_RTC]           = IO_IRQ_NR(KN02BA_IO_INR_RTC),
 415         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
 416         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
 417         [DEC_IRQ_SII]           = -1,
 418         [DEC_IRQ_TC0]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
 419         [DEC_IRQ_TC1]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
 420         [DEC_IRQ_TC2]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
 421         [DEC_IRQ_TIMER]         = -1,
 422         [DEC_IRQ_VIDEO]         = -1,
 423         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 424         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 425         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 426         [DEC_IRQ_FLOPPY_ERR]    = -1,
 427         [DEC_IRQ_ISDN_ERR]      = -1,
 428         [DEC_IRQ_ISDN_RXDMA]    = -1,
 429         [DEC_IRQ_ISDN_TXDMA]    = -1,
 430         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 431         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 432         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 433         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 434         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 435         [DEC_IRQ_AB_RXERR]      = -1,
 436         [DEC_IRQ_AB_RXDMA]      = -1,
 437         [DEC_IRQ_AB_TXERR]      = -1,
 438         [DEC_IRQ_AB_TXDMA]      = -1,
 439         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 440         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 441         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 442         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 443 };
 444
 445 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
 446         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
 447                 { .p = kn02xa_io_int } },
 448         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
 449                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
 450         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
 451                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
 452         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
 453                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
 454         { { .i = DEC_CPU_IRQ_ALL },
 455                 { .p = cpu_all_int } },
 456 };
 457
 458 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
 459         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
 460                 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
 461         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
 462                 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
 463         { { .i = IO_IRQ_DMA },
 464                 { .p = asic_dma_int } },
 465         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
 466                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
 467         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
 468                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
 469         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
 470                 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
 471         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
 472                 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
 473         { { .i = IO_IRQ_ALL },
 474                 { .p = asic_all_int } },
 475 };
 476
 477 void __init dec_init_kn02ba(void)
 478 {
 479         /* IRQ routing. */
 480         memcpy(&dec_interrupt, &kn02ba_interrupt,
 481                 sizeof(kn02ba_interrupt));
 482
 483         /* CPU IRQ priorities. */
 484         memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
 485                 sizeof(kn02ba_cpu_mask_nr_tbl));
 486
 487         /* I/O ASIC IRQ priorities. */
 488         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
 489                 sizeof(kn02ba_asic_mask_nr_tbl));
 490
 491         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 492         init_ioasic_irqs(IO_IRQ_BASE);
 493
 494 }                               /* dec_init_kn02ba */
 495
 496
 497 /*
 498  * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
 499  * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
 500  * DS5000/50, aka 4MAXine.
 501  */
 502 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
 503         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
 504         [DEC_IRQ_AB_RECV]       = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
 505         [DEC_IRQ_AB_XMIT]       = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
 506         [DEC_IRQ_DZ11]          = -1,
 507         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02CA_IO_INR_ASC),
 508         [DEC_IRQ_FLOPPY]        = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
 509         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 510         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
 511         [DEC_IRQ_ISDN]          = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
 512         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
 513         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
 514         [DEC_IRQ_PSU]           = -1,
 515         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
 516         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
 517         [DEC_IRQ_SCC1]          = -1,
 518         [DEC_IRQ_SII]           = -1,
 519         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN02CA_IO_INR_TC0),
 520         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN02CA_IO_INR_TC1),
 521         [DEC_IRQ_TC2]           = -1,
 522         [DEC_IRQ_TIMER]         = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
 523         [DEC_IRQ_VIDEO]         = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
 524         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 525         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 526         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 527         [DEC_IRQ_FLOPPY_ERR]    = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
 528         [DEC_IRQ_ISDN_ERR]      = IO_IRQ_NR(IO_INR_ISDN_ERR),
 529         [DEC_IRQ_ISDN_RXDMA]    = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
 530         [DEC_IRQ_ISDN_TXDMA]    = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
 531         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 532         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 533         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 534         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 535         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 536         [DEC_IRQ_AB_RXERR]      = IO_IRQ_NR(IO_INR_AB_RXERR),
 537         [DEC_IRQ_AB_RXDMA]      = IO_IRQ_NR(IO_INR_AB_RXDMA),
 538         [DEC_IRQ_AB_TXERR]      = IO_IRQ_NR(IO_INR_AB_TXERR),
 539         [DEC_IRQ_AB_TXDMA]      = IO_IRQ_NR(IO_INR_AB_TXDMA),
 540         [DEC_IRQ_SCC1A_RXERR]   = -1,
 541         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 542         [DEC_IRQ_SCC1A_TXERR]   = -1,
 543         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 544 };
 545
 546 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
 547         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
 548                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
 549         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
 550                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
 551         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
 552                 { .p = kn02xa_io_int } },
 553         { { .i = DEC_CPU_IRQ_ALL },
 554                 { .p = cpu_all_int } },
 555 };
 556
 557 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
 558         { { .i = IO_IRQ_DMA },
 559                 { .p = asic_dma_int } },
 560         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
 561                 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
 562         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
 563                 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
 564         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
 565                 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
 566         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
 567                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
 568         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
 569                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
 570         { { .i = IO_IRQ_ALL },
 571                 { .p = asic_all_int } },
 572 };
 573
 574 void __init dec_init_kn02ca(void)
 575 {
 576         /* IRQ routing. */
 577         memcpy(&dec_interrupt, &kn02ca_interrupt,
 578                 sizeof(kn02ca_interrupt));
 579
 580         /* CPU IRQ priorities. */
 581         memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
 582                 sizeof(kn02ca_cpu_mask_nr_tbl));
 583
 584         /* I/O ASIC IRQ priorities. */
 585         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
 586                 sizeof(kn02ca_asic_mask_nr_tbl));
 587
 588         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 589         init_ioasic_irqs(IO_IRQ_BASE);
 590
 591 }                               /* dec_init_kn02ca */
 592
 593
 594 /*
 595  * Machine-specific initialisation for KN03, aka DS5000/240,
 596  * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
 597  * DS5000/260, aka 4max+ and DS5900/260.
 598  */
 599 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
 600         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
 601         [DEC_IRQ_AB_RECV]       = -1,
 602         [DEC_IRQ_AB_XMIT]       = -1,
 603         [DEC_IRQ_DZ11]          = -1,
 604         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN03_IO_INR_ASC),
 605         [DEC_IRQ_FLOPPY]        = -1,
 606         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 607         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
 608         [DEC_IRQ_ISDN]          = -1,
 609         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN03_IO_INR_LANCE),
 610         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
 611         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN03_IO_INR_PSU),
 612         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
 613         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN03_IO_INR_SCC0),
 614         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN03_IO_INR_SCC1),
 615         [DEC_IRQ_SII]           = -1,
 616         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN03_IO_INR_TC0),
 617         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN03_IO_INR_TC1),
 618         [DEC_IRQ_TC2]           = IO_IRQ_NR(KN03_IO_INR_TC2),
 619         [DEC_IRQ_TIMER]         = -1,
 620         [DEC_IRQ_VIDEO]         = -1,
 621         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 622         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 623         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 624         [DEC_IRQ_FLOPPY_ERR]    = -1,
 625         [DEC_IRQ_ISDN_ERR]      = -1,
 626         [DEC_IRQ_ISDN_RXDMA]    = -1,
 627         [DEC_IRQ_ISDN_TXDMA]    = -1,
 628         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 629         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 630         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 631         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 632         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 633         [DEC_IRQ_AB_RXERR]      = -1,
 634         [DEC_IRQ_AB_RXDMA]      = -1,
 635         [DEC_IRQ_AB_TXERR]      = -1,
 636         [DEC_IRQ_AB_TXDMA]      = -1,
 637         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 638         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 639         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 640         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 641 };
 642
 643 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
 644         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
 645                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
 646         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
 647                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
 648         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
 649                 { .p = kn03_io_int } },
 650         { { .i = DEC_CPU_IRQ_ALL },
 651                 { .p = cpu_all_int } },
 652 };
 653
 654 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
 655         { { .i = IO_IRQ_DMA },
 656                 { .p = asic_dma_int } },
 657         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
 658                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
 659         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
 660                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
 661         { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
 662                 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
 663         { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
 664                 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
 665         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
 666                 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
 667         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
 668                 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
 669         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
 670                 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
 671         { { .i = IO_IRQ_ALL },
 672                 { .p = asic_all_int } },
 673 };
 674
 675 void __init dec_init_kn03(void)
 676 {
 677         /* IRQ routing. */
 678         memcpy(&dec_interrupt, &kn03_interrupt,
 679                 sizeof(kn03_interrupt));
 680
 681         /* CPU IRQ priorities. */
 682         memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
 683                 sizeof(kn03_cpu_mask_nr_tbl));
 684
 685         /* I/O ASIC IRQ priorities. */
 686         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
 687                 sizeof(kn03_asic_mask_nr_tbl));
 688
 689         mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
 690         init_ioasic_irqs(IO_IRQ_BASE);
 691
 692 }                               /* dec_init_kn03 */
 693
 694
 695 void __init arch_init_irq(void)
 696 {
 697         switch (mips_machtype) {
 698         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 699                 dec_init_kn01();
 700                 break;
 701         case MACH_DS5100:       /* DS5100 MIPSmate */
 702                 dec_init_kn230();
 703                 break;
 704         case MACH_DS5000_200:   /* DS5000/200 3max */
 705                 dec_init_kn02();
 706                 break;
 707         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 708                 dec_init_kn02ba();
 709                 break;
 710         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 711         case MACH_DS5900:       /* DS5900 bigmax */
 712                 dec_init_kn03();
 713                 break;
 714         case MACH_DS5000_XX:    /* Personal DS5000/xx */
 715                 dec_init_kn02ca();
 716                 break;
 717         case MACH_DS5800:       /* DS5800 Isis */
 718                 panic("Don't know how to set this up!");
 719                 break;
 720         case MACH_DS5400:       /* DS5400 MIPSfair */
 721                 panic("Don't know how to set this up!");
 722                 break;
 723         case MACH_DS5500:       /* DS5500 MIPSfair-2 */
 724                 panic("Don't know how to set this up!");
 725                 break;
 726         }
 727         set_except_vector(0, decstation_handle_int);
 728
 729         /* Free the FPU interrupt if the exception is present. */
 730         if (!cpu_has_nofpuex) {
 731                 cpu_fpu_mask = 0;
 732                 dec_interrupt[DEC_IRQ_FPU] = -1;
 733         }
 734
 735         /* Register board interrupts: FPU and cascade. */
 736         if (dec_interrupt[DEC_IRQ_FPU] >= 0)
 737                 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
 738         if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
 739                 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
 740
 741         /* Register the bus error interrupt. */
 742         if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
 743                 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
 744
 745         /* Register the HALT interrupt. */
 746         if (dec_interrupt[DEC_IRQ_HALT] >= 0)
 747                 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
 748 }
 749
 750 EXPORT_SYMBOL(ioasic_base);
 751 EXPORT_SYMBOL(dec_kn_slot_size);
 752 EXPORT_SYMBOL(dec_interrupt);