2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
29 #include <asm/module.h>
30 #include <asm/pgtable.h>
31 #include <asm/ptrace.h>
32 #include <asm/sections.h>
33 #include <asm/system.h>
34 #include <asm/tlbdebug.h>
35 #include <asm/traps.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/watch.h>
39 #include <asm/types.h>
41 extern asmlinkage void handle_tlbm(void);
42 extern asmlinkage void handle_tlbl(void);
43 extern asmlinkage void handle_tlbs(void);
44 extern asmlinkage void handle_adel(void);
45 extern asmlinkage void handle_ades(void);
46 extern asmlinkage void handle_ibe(void);
47 extern asmlinkage void handle_dbe(void);
48 extern asmlinkage void handle_sys(void);
49 extern asmlinkage void handle_bp(void);
50 extern asmlinkage void handle_ri(void);
51 extern asmlinkage void handle_cpu(void);
52 extern asmlinkage void handle_ov(void);
53 extern asmlinkage void handle_tr(void);
54 extern asmlinkage void handle_fpe(void);
55 extern asmlinkage void handle_mdmx(void);
56 extern asmlinkage void handle_watch(void);
57 extern asmlinkage void handle_mcheck(void);
58 extern asmlinkage void handle_reserved(void);
60 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
61 struct mips_fpu_soft_struct *ctx);
63 void (*board_be_init)(void);
64 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
67 * These constant is for searching for possible module text segments.
68 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
70 #define MODULE_RANGE (8*1024*1024)
73 * This routine abuses get_user()/put_user() to reference pointers
74 * with at least a bit of error checking ...
76 void show_stack(struct task_struct *task, unsigned long *sp)
78 const int field = 2 * sizeof(unsigned long);
83 if (task && task != current)
84 sp = (unsigned long *) task->thread.reg29;
86 sp = (unsigned long *) &sp;
91 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
92 if (i && ((i % (64 / field)) == 0))
99 if (__get_user(stackdata, sp++)) {
100 printk(" (Bad stack address)");
104 printk(" %0*lx", field, stackdata);
110 void show_trace(struct task_struct *task, unsigned long *stack)
112 const int field = 2 * sizeof(unsigned long);
116 if (task && task != current)
117 stack = (unsigned long *) task->thread.reg29;
119 stack = (unsigned long *) &stack;
122 printk("Call Trace:");
123 #ifdef CONFIG_KALLSYMS
126 while (!kstack_end(stack)) {
128 if (__kernel_text_address(addr)) {
129 printk(" [<%0*lx>] ", field, addr);
130 print_symbol("%s\n", addr);
137 * The architecture-independent dump_stack generator
139 void dump_stack(void)
143 show_trace(current, &stack);
146 EXPORT_SYMBOL(dump_stack);
148 void show_code(unsigned int *pc)
154 for(i = -3 ; i < 6 ; i++) {
156 if (__get_user(insn, pc + i)) {
157 printk(" (Bad address in epc)\n");
160 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
164 void show_regs(struct pt_regs *regs)
166 const int field = 2 * sizeof(unsigned long);
167 unsigned int cause = regs->cp0_cause;
170 printk("Cpu %d\n", smp_processor_id());
173 * Saved main processor registers
175 for (i = 0; i < 32; ) {
179 printk(" %0*lx", field, 0UL);
180 else if (i == 26 || i == 27)
181 printk(" %*s", field, "");
183 printk(" %0*lx", field, regs->regs[i]);
190 printk("Hi : %0*lx\n", field, regs->hi);
191 printk("Lo : %0*lx\n", field, regs->lo);
194 * Saved cp0 registers
196 printk("epc : %0*lx ", field, regs->cp0_epc);
197 print_symbol("%s ", regs->cp0_epc);
198 printk(" %s\n", print_tainted());
199 printk("ra : %0*lx ", field, regs->regs[31]);
200 print_symbol("%s\n", regs->regs[31]);
202 printk("Status: %08x ", (uint32_t) regs->cp0_status);
204 if (regs->cp0_status & ST0_KX)
206 if (regs->cp0_status & ST0_SX)
208 if (regs->cp0_status & ST0_UX)
210 switch (regs->cp0_status & ST0_KSU) {
215 printk("SUPERVISOR ");
224 if (regs->cp0_status & ST0_ERL)
226 if (regs->cp0_status & ST0_EXL)
228 if (regs->cp0_status & ST0_IE)
232 printk("Cause : %08x\n", cause);
234 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
235 if (1 <= cause && cause <= 5)
236 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
238 printk("PrId : %08x\n", read_c0_prid());
241 void show_registers(struct pt_regs *regs)
245 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
246 current->comm, current->pid, current_thread_info(), current);
247 show_stack(current, (long *) regs->regs[29]);
248 show_trace(current, (long *) regs->regs[29]);
249 show_code((unsigned int *) regs->cp0_epc);
253 static DEFINE_SPINLOCK(die_lock);
255 NORET_TYPE void __die(const char * str, struct pt_regs * regs,
256 const char * file, const char * func, unsigned long line)
258 static int die_counter;
261 spin_lock_irq(&die_lock);
264 printk(" in %s:%s, line %ld", file, func, line);
265 printk("[#%d]:\n", ++die_counter);
266 show_registers(regs);
267 spin_unlock_irq(&die_lock);
271 void __die_if_kernel(const char * str, struct pt_regs * regs,
272 const char * file, const char * func, unsigned long line)
274 if (!user_mode(regs))
275 __die(str, regs, file, func, line);
278 extern const struct exception_table_entry __start___dbe_table[];
279 extern const struct exception_table_entry __stop___dbe_table[];
281 void __declare_dbe_table(void)
283 __asm__ __volatile__(
284 ".section\t__dbe_table,\"a\"\n\t"
289 /* Given an address, look for it in the exception tables. */
290 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
292 const struct exception_table_entry *e;
294 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
296 e = search_module_dbetables(addr);
300 asmlinkage void do_be(struct pt_regs *regs)
302 const int field = 2 * sizeof(unsigned long);
303 const struct exception_table_entry *fixup = NULL;
304 int data = regs->cp0_cause & 4;
305 int action = MIPS_BE_FATAL;
307 /* XXX For now. Fixme, this searches the wrong table ... */
308 if (data && !user_mode(regs))
309 fixup = search_dbe_tables(exception_epc(regs));
312 action = MIPS_BE_FIXUP;
314 if (board_be_handler)
315 action = board_be_handler(regs, fixup != 0);
318 case MIPS_BE_DISCARD:
322 regs->cp0_epc = fixup->nextinsn;
331 * Assume it would be too dangerous to continue ...
333 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
334 data ? "Data" : "Instruction",
335 field, regs->cp0_epc, field, regs->regs[31]);
336 die_if_kernel("Oops", regs);
337 force_sig(SIGBUS, current);
340 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
342 unsigned int __user *epc;
344 epc = (unsigned int __user *) regs->cp0_epc +
345 ((regs->cp0_cause & CAUSEF_BD) != 0);
346 if (!get_user(*opcode, epc))
349 force_sig(SIGSEGV, current);
357 #define OPCODE 0xfc000000
358 #define BASE 0x03e00000
359 #define RT 0x001f0000
360 #define OFFSET 0x0000ffff
361 #define LL 0xc0000000
362 #define SC 0xe0000000
363 #define SPEC3 0x7c000000
364 #define RD 0x0000f800
365 #define FUNC 0x0000003f
366 #define RDHWR 0x0000003b
369 * The ll_bit is cleared by r*_switch.S
372 unsigned long ll_bit;
374 static struct task_struct *ll_task = NULL;
376 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
378 unsigned long value, __user *vaddr;
383 * analyse the ll instruction that just caused a ri exception
384 * and put the referenced address to addr.
387 /* sign extend offset */
388 offset = opcode & OFFSET;
392 vaddr = (unsigned long __user *)
393 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
395 if ((unsigned long)vaddr & 3) {
399 if (get_user(value, vaddr)) {
406 if (ll_task == NULL || ll_task == current) {
415 compute_return_epc(regs);
417 regs->regs[(opcode & RT) >> 16] = value;
422 force_sig(signal, current);
425 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
427 unsigned long __user *vaddr;
433 * analyse the sc instruction that just caused a ri exception
434 * and put the referenced address to addr.
437 /* sign extend offset */
438 offset = opcode & OFFSET;
442 vaddr = (unsigned long __user *)
443 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
444 reg = (opcode & RT) >> 16;
446 if ((unsigned long)vaddr & 3) {
453 if (ll_bit == 0 || ll_task != current) {
454 compute_return_epc(regs);
462 if (put_user(regs->regs[reg], vaddr)) {
467 compute_return_epc(regs);
473 force_sig(signal, current);
477 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
478 * opcodes are supposed to result in coprocessor unusable exceptions if
479 * executed on ll/sc-less processors. That's the theory. In practice a
480 * few processors such as NEC's VR4100 throw reserved instruction exceptions
481 * instead, so we're doing the emulation thing in both exception handlers.
483 static inline int simulate_llsc(struct pt_regs *regs)
487 if (unlikely(get_insn_opcode(regs, &opcode)))
490 if ((opcode & OPCODE) == LL) {
491 simulate_ll(regs, opcode);
494 if ((opcode & OPCODE) == SC) {
495 simulate_sc(regs, opcode);
499 return -EFAULT; /* Strange things going on ... */
503 * Simulate trapping 'rdhwr' instructions to provide user accessible
504 * registers not implemented in hardware. The only current use of this
505 * is the thread area pointer.
507 static inline int simulate_rdhwr(struct pt_regs *regs)
509 struct thread_info *ti = current->thread_info;
512 if (unlikely(get_insn_opcode(regs, &opcode)))
515 if (unlikely(compute_return_epc(regs)))
518 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
519 int rd = (opcode & RD) >> 11;
520 int rt = (opcode & RT) >> 16;
523 regs->regs[rt] = ti->tp_value;
533 asmlinkage void do_ov(struct pt_regs *regs)
537 info.si_code = FPE_INTOVF;
538 info.si_signo = SIGFPE;
540 info.si_addr = (void __user *) regs->cp0_epc;
541 force_sig_info(SIGFPE, &info, current);
545 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
547 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
549 if (fcr31 & FPU_CSR_UNI_X) {
554 #ifdef CONFIG_PREEMPT
555 if (!is_fpu_owner()) {
556 /* We might lose fpu before disabling preempt... */
558 BUG_ON(!used_math());
563 * Unimplemented operation exception. If we've got the full
564 * software emulator on-board, let's use it...
566 * Force FPU to dump state into task/thread context. We're
567 * moving a lot of data here for what is probably a single
568 * instruction, but the alternative is to pre-decode the FP
569 * register operands before invoking the emulator, which seems
570 * a bit extreme for what should be an infrequent event.
573 /* Ensure 'resume' not overwrite saved fp context again. */
578 /* Run the emulator */
579 sig = fpu_emulator_cop1Handler (0, regs,
580 ¤t->thread.fpu.soft);
584 own_fpu(); /* Using the FPU again. */
586 * We can't allow the emulated instruction to leave any of
587 * the cause bit set in $fcr31.
589 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
591 /* Restore the hardware register state */
596 /* If something went wrong, signal */
598 force_sig(sig, current);
603 force_sig(SIGFPE, current);
606 asmlinkage void do_bp(struct pt_regs *regs)
608 unsigned int opcode, bcode;
611 die_if_kernel("Break instruction in kernel code", regs);
613 if (get_insn_opcode(regs, &opcode))
617 * There is the ancient bug in the MIPS assemblers that the break
618 * code starts left to bit 16 instead to bit 6 in the opcode.
619 * Gas is bug-compatible, but not always, grrr...
620 * We handle both cases with a simple heuristics. --macro
622 bcode = ((opcode >> 6) & ((1 << 20) - 1));
623 if (bcode < (1 << 10))
627 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
628 * insns, even for break codes that indicate arithmetic failures.
630 * But should we continue the brokenness??? --macro
633 case BRK_OVERFLOW << 10:
634 case BRK_DIVZERO << 10:
635 if (bcode == (BRK_DIVZERO << 10))
636 info.si_code = FPE_INTDIV;
638 info.si_code = FPE_INTOVF;
639 info.si_signo = SIGFPE;
641 info.si_addr = (void __user *) regs->cp0_epc;
642 force_sig_info(SIGFPE, &info, current);
645 force_sig(SIGTRAP, current);
649 asmlinkage void do_tr(struct pt_regs *regs)
651 unsigned int opcode, tcode = 0;
654 die_if_kernel("Trap instruction in kernel code", regs);
656 if (get_insn_opcode(regs, &opcode))
659 /* Immediate versions don't provide a code. */
660 if (!(opcode & OPCODE))
661 tcode = ((opcode >> 6) & ((1 << 10) - 1));
664 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
665 * insns, even for trap codes that indicate arithmetic failures.
667 * But should we continue the brokenness??? --macro
672 if (tcode == BRK_DIVZERO)
673 info.si_code = FPE_INTDIV;
675 info.si_code = FPE_INTOVF;
676 info.si_signo = SIGFPE;
678 info.si_addr = (void __user *) regs->cp0_epc;
679 force_sig_info(SIGFPE, &info, current);
682 force_sig(SIGTRAP, current);
686 asmlinkage void do_ri(struct pt_regs *regs)
688 die_if_kernel("Reserved instruction in kernel code", regs);
691 if (!simulate_llsc(regs))
694 if (!simulate_rdhwr(regs))
697 force_sig(SIGILL, current);
700 asmlinkage void do_cpu(struct pt_regs *regs)
704 die_if_kernel("do_cpu invoked from kernel context!", regs);
706 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
711 if (!simulate_llsc(regs))
714 if (!simulate_rdhwr(regs))
723 if (used_math()) { /* Using the FPU again. */
725 } else { /* First time FPU user. */
733 int sig = fpu_emulator_cop1Handler(0, regs,
734 ¤t->thread.fpu.soft);
736 force_sig(sig, current);
746 force_sig(SIGILL, current);
749 asmlinkage void do_mdmx(struct pt_regs *regs)
751 force_sig(SIGILL, current);
754 asmlinkage void do_watch(struct pt_regs *regs)
757 * We use the watch exception where available to detect stack
762 panic("Caught WATCH exception - probably caused by stack overflow.");
765 asmlinkage void do_mcheck(struct pt_regs *regs)
770 * Some chips may have other causes of machine check (e.g. SB1
773 panic("Caught Machine Check exception - %scaused by multiple "
774 "matching entries in the TLB.",
775 (regs->cp0_status & ST0_TS) ? "" : "not ");
778 asmlinkage void do_reserved(struct pt_regs *regs)
781 * Game over - no way to handle this if it ever occurs. Most probably
782 * caused by a new unknown cpu type or after another deadly
783 * hard/software error.
786 panic("Caught reserved exception %ld - should not happen.",
787 (regs->cp0_cause & 0x7f) >> 2);
791 * Some MIPS CPUs can enable/disable for cache parity detection, but do
794 static inline void parity_protection_init(void)
796 switch (current_cpu_data.cputype) {
799 write_c0_ecc(0x80000000);
800 back_to_back_c0_hazard();
801 /* Set the PE bit (bit 31) in the c0_errctl register. */
802 printk(KERN_INFO "Cache parity protection %sabled\n",
803 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
807 /* Clear the DE bit (bit 16) in the c0_status register. */
808 printk(KERN_INFO "Enable cache parity protection for "
809 "MIPS 20KC/25KF CPUs.\n");
810 clear_c0_status(ST0_DE);
817 asmlinkage void cache_parity_error(void)
819 const int field = 2 * sizeof(unsigned long);
820 unsigned int reg_val;
822 /* For the moment, report the problem and hang. */
823 printk("Cache error exception:\n");
824 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
825 reg_val = read_c0_cacheerr();
826 printk("c0_cacheerr == %08x\n", reg_val);
828 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
829 reg_val & (1<<30) ? "secondary" : "primary",
830 reg_val & (1<<31) ? "data" : "insn");
831 printk("Error bits: %s%s%s%s%s%s%s\n",
832 reg_val & (1<<29) ? "ED " : "",
833 reg_val & (1<<28) ? "ET " : "",
834 reg_val & (1<<26) ? "EE " : "",
835 reg_val & (1<<25) ? "EB " : "",
836 reg_val & (1<<24) ? "EI " : "",
837 reg_val & (1<<23) ? "E1 " : "",
838 reg_val & (1<<22) ? "E0 " : "");
839 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
841 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
842 if (reg_val & (1<<22))
843 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
845 if (reg_val & (1<<23))
846 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
849 panic("Can't handle the cache error!");
853 * SDBBP EJTAG debug exception handler.
854 * We skip the instruction and return to the next instruction.
856 void ejtag_exception_handler(struct pt_regs *regs)
858 const int field = 2 * sizeof(unsigned long);
859 unsigned long depc, old_epc;
862 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
863 depc = read_c0_depc();
864 debug = read_c0_debug();
865 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
866 if (debug & 0x80000000) {
868 * In branch delay slot.
869 * We cheat a little bit here and use EPC to calculate the
870 * debug return address (DEPC). EPC is restored after the
873 old_epc = regs->cp0_epc;
874 regs->cp0_epc = depc;
875 __compute_return_epc(regs);
876 depc = regs->cp0_epc;
877 regs->cp0_epc = old_epc;
883 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
884 write_c0_debug(debug | 0x100);
889 * NMI exception handler.
891 void nmi_exception_handler(struct pt_regs *regs)
893 printk("NMI taken!!!!\n");
898 unsigned long exception_handlers[32];
901 * As a side effect of the way this is implemented we're limited
902 * to interrupt handlers in the address range from
903 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
905 void *set_except_vector(int n, void *addr)
907 unsigned long handler = (unsigned long) addr;
908 unsigned long old_handler = exception_handlers[n];
910 exception_handlers[n] = handler;
911 if (n == 0 && cpu_has_divec) {
912 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
913 (0x03ffffff & (handler >> 2));
914 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
916 return (void *)old_handler;
920 * This is used by native signal handling
922 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
923 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
925 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
926 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
928 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
929 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
931 static inline void signal_init(void)
934 save_fp_context = _save_fp_context;
935 restore_fp_context = _restore_fp_context;
937 save_fp_context = fpu_emulator_save_context;
938 restore_fp_context = fpu_emulator_restore_context;
942 #ifdef CONFIG_MIPS32_COMPAT
945 * This is used by 32-bit signal stuff on the 64-bit kernel
947 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
948 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
950 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
951 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
953 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
954 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
956 static inline void signal32_init(void)
959 save_fp_context32 = _save_fp_context32;
960 restore_fp_context32 = _restore_fp_context32;
962 save_fp_context32 = fpu_emulator_save_context32;
963 restore_fp_context32 = fpu_emulator_restore_context32;
968 extern void cpu_cache_init(void);
969 extern void tlb_init(void);
971 void __init per_cpu_trap_init(void)
973 unsigned int cpu = smp_processor_id();
974 unsigned int status_set = ST0_CU0;
977 * Disable coprocessors and select 32-bit or 64-bit addressing
978 * and the 16/32 or 32/32 FPR register model. Reset the BEV
979 * flag that some firmware may have left set and the TS bit (for
980 * IP27). Set XX for ISA IV code to work.
983 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
985 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
986 status_set |= ST0_XX;
987 change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
991 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
992 * interrupt processing overhead. Use it where available.
995 set_c0_cause(CAUSEF_IV);
997 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
998 TLBMISS_HANDLER_SETUP();
1000 atomic_inc(&init_mm.mm_count);
1001 current->active_mm = &init_mm;
1002 BUG_ON(current->mm);
1003 enter_lazy_tlb(&init_mm, current);
1009 void __init trap_init(void)
1011 extern char except_vec3_generic, except_vec3_r4000;
1012 extern char except_vec_ejtag_debug;
1013 extern char except_vec4;
1016 per_cpu_trap_init();
1019 * Copy the generic exception handlers to their final destination.
1020 * This will be overriden later as suitable for a particular
1023 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1026 * Setup default vectors
1028 for (i = 0; i <= 31; i++)
1029 set_except_vector(i, handle_reserved);
1032 * Copy the EJTAG debug exception vector handler code to it's final
1036 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
1039 * Only some CPUs have the watch exceptions.
1042 set_except_vector(23, handle_watch);
1045 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
1046 * interrupt processing overhead. Use it where available.
1049 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
1052 * Some CPUs can enable/disable for cache parity detection, but does
1053 * it different ways.
1055 parity_protection_init();
1058 * The Data Bus Errors / Instruction Bus Errors are signaled
1059 * by external hardware. Therefore these two exceptions
1060 * may have board specific handlers.
1065 set_except_vector(1, handle_tlbm);
1066 set_except_vector(2, handle_tlbl);
1067 set_except_vector(3, handle_tlbs);
1069 set_except_vector(4, handle_adel);
1070 set_except_vector(5, handle_ades);
1072 set_except_vector(6, handle_ibe);
1073 set_except_vector(7, handle_dbe);
1075 set_except_vector(8, handle_sys);
1076 set_except_vector(9, handle_bp);
1077 set_except_vector(10, handle_ri);
1078 set_except_vector(11, handle_cpu);
1079 set_except_vector(12, handle_ov);
1080 set_except_vector(13, handle_tr);
1081 set_except_vector(22, handle_mdmx);
1083 if (cpu_has_fpu && !cpu_has_nofpuex)
1084 set_except_vector(15, handle_fpe);
1087 set_except_vector(24, handle_mcheck);
1090 /* Special exception: R4[04]00 uses also the divec space. */
1091 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1092 else if (cpu_has_4kex)
1093 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1095 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1097 if (current_cpu_data.cputype == CPU_R6000 ||
1098 current_cpu_data.cputype == CPU_R6000A) {
1100 * The R6000 is the only R-series CPU that features a machine
1101 * check exception (similar to the R4000 cache error) and
1102 * unaligned ldc1/sdc1 exception. The handlers have not been
1103 * written yet. Well, anyway there is no R6000 machine on the
1104 * current list of targets for Linux/MIPS.
1105 * (Duh, crap, there is someone with a triple R6k machine)
1107 //set_except_vector(14, handle_mc);
1108 //set_except_vector(15, handle_ndc);
1112 #ifdef CONFIG_MIPS32_COMPAT
1116 flush_icache_range(CAC_BASE, CAC_BASE + 0x400);