2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
15 #include <linux/bitops.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
21 #include <asm/cpu-features.h>
24 #include <asm/pgtable.h>
25 #include <asm/r4kcache.h>
26 #include <asm/system.h>
27 #include <asm/mmu_context.h>
30 static unsigned long icache_size, dcache_size, scache_size;
33 * Dummy cache handling routines for machines without boardcaches
35 static void no_sc_noop(void) {}
37 static struct bcache_ops no_sc_ops = {
38 .bc_enable = (void *)no_sc_noop,
39 .bc_disable = (void *)no_sc_noop,
40 .bc_wback_inv = (void *)no_sc_noop,
41 .bc_inv = (void *)no_sc_noop
44 struct bcache_ops *bcops = &no_sc_ops;
46 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
47 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
49 #define R4600_HIT_CACHEOP_WAR_IMPL \
51 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
52 *(volatile unsigned long *)CKSEG1; \
53 if (R4600_V1_HIT_CACHEOP_WAR) \
54 __asm__ __volatile__("nop;nop;nop;nop"); \
57 static void (*r4k_blast_dcache_page)(unsigned long addr);
59 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
61 R4600_HIT_CACHEOP_WAR_IMPL;
62 blast_dcache32_page(addr);
65 static inline void r4k_blast_dcache_page_setup(void)
67 unsigned long dc_lsize = cpu_dcache_line_size();
70 r4k_blast_dcache_page = blast_dcache16_page;
71 else if (dc_lsize == 32)
72 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
75 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
77 static inline void r4k_blast_dcache_page_indexed_setup(void)
79 unsigned long dc_lsize = cpu_dcache_line_size();
82 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
83 else if (dc_lsize == 32)
84 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
87 static void (* r4k_blast_dcache)(void);
89 static inline void r4k_blast_dcache_setup(void)
91 unsigned long dc_lsize = cpu_dcache_line_size();
94 r4k_blast_dcache = blast_dcache16;
95 else if (dc_lsize == 32)
96 r4k_blast_dcache = blast_dcache32;
99 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
100 #define JUMP_TO_ALIGN(order) \
101 __asm__ __volatile__( \
103 ".align\t" #order "\n\t" \
106 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
107 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
109 static inline void blast_r4600_v1_icache32(void)
113 local_irq_save(flags);
115 local_irq_restore(flags);
118 static inline void tx49_blast_icache32(void)
120 unsigned long start = INDEX_BASE;
121 unsigned long end = start + current_cpu_data.icache.waysize;
122 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
123 unsigned long ws_end = current_cpu_data.icache.ways <<
124 current_cpu_data.icache.waybit;
125 unsigned long ws, addr;
127 CACHE32_UNROLL32_ALIGN2;
128 /* I'm in even chunk. blast odd chunks */
129 for (ws = 0; ws < ws_end; ws += ws_inc)
130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
131 cache32_unroll32(addr|ws,Index_Invalidate_I);
132 CACHE32_UNROLL32_ALIGN;
133 /* I'm in odd chunk. blast even chunks */
134 for (ws = 0; ws < ws_end; ws += ws_inc)
135 for (addr = start; addr < end; addr += 0x400 * 2)
136 cache32_unroll32(addr|ws,Index_Invalidate_I);
139 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
143 local_irq_save(flags);
144 blast_icache32_page_indexed(page);
145 local_irq_restore(flags);
148 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
150 unsigned long start = page;
151 unsigned long end = start + PAGE_SIZE;
152 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
153 unsigned long ws_end = current_cpu_data.icache.ways <<
154 current_cpu_data.icache.waybit;
155 unsigned long ws, addr;
157 CACHE32_UNROLL32_ALIGN2;
158 /* I'm in even chunk. blast odd chunks */
159 for (ws = 0; ws < ws_end; ws += ws_inc)
160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
161 cache32_unroll32(addr|ws,Index_Invalidate_I);
162 CACHE32_UNROLL32_ALIGN;
163 /* I'm in odd chunk. blast even chunks */
164 for (ws = 0; ws < ws_end; ws += ws_inc)
165 for (addr = start; addr < end; addr += 0x400 * 2)
166 cache32_unroll32(addr|ws,Index_Invalidate_I);
169 static void (* r4k_blast_icache_page)(unsigned long addr);
171 static inline void r4k_blast_icache_page_setup(void)
173 unsigned long ic_lsize = cpu_icache_line_size();
176 r4k_blast_icache_page = blast_icache16_page;
177 else if (ic_lsize == 32)
178 r4k_blast_icache_page = blast_icache32_page;
179 else if (ic_lsize == 64)
180 r4k_blast_icache_page = blast_icache64_page;
184 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
186 static inline void r4k_blast_icache_page_indexed_setup(void)
188 unsigned long ic_lsize = cpu_icache_line_size();
191 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
192 else if (ic_lsize == 32) {
193 if (TX49XX_ICACHE_INDEX_INV_WAR)
194 r4k_blast_icache_page_indexed =
195 tx49_blast_icache32_page_indexed;
196 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
197 r4k_blast_icache_page_indexed =
198 blast_icache32_r4600_v1_page_indexed;
200 r4k_blast_icache_page_indexed =
201 blast_icache32_page_indexed;
202 } else if (ic_lsize == 64)
203 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
206 static void (* r4k_blast_icache)(void);
208 static inline void r4k_blast_icache_setup(void)
210 unsigned long ic_lsize = cpu_icache_line_size();
213 r4k_blast_icache = blast_icache16;
214 else if (ic_lsize == 32) {
215 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
216 r4k_blast_icache = blast_r4600_v1_icache32;
217 else if (TX49XX_ICACHE_INDEX_INV_WAR)
218 r4k_blast_icache = tx49_blast_icache32;
220 r4k_blast_icache = blast_icache32;
221 } else if (ic_lsize == 64)
222 r4k_blast_icache = blast_icache64;
225 static void (* r4k_blast_scache_page)(unsigned long addr);
227 static inline void r4k_blast_scache_page_setup(void)
229 unsigned long sc_lsize = cpu_scache_line_size();
232 r4k_blast_scache_page = blast_scache16_page;
233 else if (sc_lsize == 32)
234 r4k_blast_scache_page = blast_scache32_page;
235 else if (sc_lsize == 64)
236 r4k_blast_scache_page = blast_scache64_page;
237 else if (sc_lsize == 128)
238 r4k_blast_scache_page = blast_scache128_page;
241 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
243 static inline void r4k_blast_scache_page_indexed_setup(void)
245 unsigned long sc_lsize = cpu_scache_line_size();
248 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
249 else if (sc_lsize == 32)
250 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
251 else if (sc_lsize == 64)
252 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
253 else if (sc_lsize == 128)
254 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
257 static void (* r4k_blast_scache)(void);
259 static inline void r4k_blast_scache_setup(void)
261 unsigned long sc_lsize = cpu_scache_line_size();
264 r4k_blast_scache = blast_scache16;
265 else if (sc_lsize == 32)
266 r4k_blast_scache = blast_scache32;
267 else if (sc_lsize == 64)
268 r4k_blast_scache = blast_scache64;
269 else if (sc_lsize == 128)
270 r4k_blast_scache = blast_scache128;
274 * This is former mm's flush_cache_all() which really should be
275 * flush_cache_vunmap these days ...
277 static inline void local_r4k_flush_cache_all(void * args)
283 static void r4k_flush_cache_all(void)
285 if (!cpu_has_dc_aliases)
288 on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
291 static inline void local_r4k___flush_cache_all(void * args)
296 switch (current_cpu_data.cputype) {
307 static void r4k___flush_cache_all(void)
309 on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
312 static inline void local_r4k_flush_cache_range(void * args)
314 struct vm_area_struct *vma = args;
317 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
320 exec = vma->vm_flags & VM_EXEC;
321 if (cpu_has_dc_aliases || exec)
327 static void r4k_flush_cache_range(struct vm_area_struct *vma,
328 unsigned long start, unsigned long end)
330 on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
333 static inline void local_r4k_flush_cache_mm(void * args)
335 struct mm_struct *mm = args;
337 if (!cpu_context(smp_processor_id(), mm))
344 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
345 * only flush the primary caches but R10000 and R12000 behave sane ...
347 if (current_cpu_data.cputype == CPU_R4000SC ||
348 current_cpu_data.cputype == CPU_R4000MC ||
349 current_cpu_data.cputype == CPU_R4400SC ||
350 current_cpu_data.cputype == CPU_R4400MC)
354 static void r4k_flush_cache_mm(struct mm_struct *mm)
356 if (!cpu_has_dc_aliases)
359 on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
362 struct flush_cache_page_args {
363 struct vm_area_struct *vma;
367 static inline void local_r4k_flush_cache_page(void *args)
369 struct flush_cache_page_args *fcp_args = args;
370 struct vm_area_struct *vma = fcp_args->vma;
371 unsigned long page = fcp_args->page;
372 int exec = vma->vm_flags & VM_EXEC;
373 struct mm_struct *mm = vma->vm_mm;
380 * If ownes no valid ASID yet, cannot possibly have gotten
381 * this page into the cache.
383 if (cpu_context(smp_processor_id(), mm) == 0)
387 pgdp = pgd_offset(mm, page);
388 pudp = pud_offset(pgdp, page);
389 pmdp = pmd_offset(pudp, page);
390 ptep = pte_offset(pmdp, page);
393 * If the page isn't marked valid, the page cannot possibly be
396 if (!(pte_val(*ptep) & _PAGE_PRESENT))
400 * Doing flushes for another ASID than the current one is
401 * too difficult since stupid R4k caches do a TLB translation
402 * for every cache flush operation. So we do indexed flushes
403 * in that case, which doesn't overly flush the cache too much.
405 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
406 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
407 r4k_blast_dcache_page(page);
408 if (exec && !cpu_icache_snoops_remote_store)
409 r4k_blast_scache_page(page);
412 r4k_blast_icache_page(page);
418 * Do indexed flush, too much work to get the (possible) TLB refills
421 page = INDEX_BASE + (page & (dcache_size - 1));
422 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
423 r4k_blast_dcache_page_indexed(page);
424 if (exec && !cpu_icache_snoops_remote_store)
425 r4k_blast_scache_page_indexed(page);
428 if (cpu_has_vtag_icache) {
429 int cpu = smp_processor_id();
431 if (cpu_context(cpu, mm) != 0)
432 drop_mmu_context(mm, cpu);
434 r4k_blast_icache_page_indexed(page);
438 static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
440 struct flush_cache_page_args args;
445 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
448 static inline void local_r4k_flush_data_cache_page(void * addr)
450 r4k_blast_dcache_page((unsigned long) addr);
453 static void r4k_flush_data_cache_page(unsigned long addr)
455 on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
458 struct flush_icache_range_args {
459 unsigned long __user start;
460 unsigned long __user end;
463 static inline void local_r4k_flush_icache_range(void *args)
465 struct flush_icache_range_args *fir_args = args;
466 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
467 unsigned long ic_lsize = current_cpu_data.icache.linesz;
468 unsigned long sc_lsize = current_cpu_data.scache.linesz;
469 unsigned long start = fir_args->start;
470 unsigned long end = fir_args->end;
471 unsigned long addr, aend;
473 if (!cpu_has_ic_fills_f_dc) {
474 if (end - start > dcache_size) {
477 addr = start & ~(dc_lsize - 1);
478 aend = (end - 1) & ~(dc_lsize - 1);
481 /* Hit_Writeback_Inv_D */
482 protected_writeback_dcache_line(addr);
489 if (!cpu_icache_snoops_remote_store) {
490 if (end - start > scache_size) {
493 addr = start & ~(sc_lsize - 1);
494 aend = (end - 1) & ~(sc_lsize - 1);
497 /* Hit_Writeback_Inv_D */
498 protected_writeback_scache_line(addr);
507 if (end - start > icache_size)
510 addr = start & ~(ic_lsize - 1);
511 aend = (end - 1) & ~(ic_lsize - 1);
513 /* Hit_Invalidate_I */
514 protected_flush_icache_line(addr);
522 static void r4k_flush_icache_range(unsigned long __user start,
523 unsigned long __user end)
525 struct flush_icache_range_args args;
530 on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
534 * Ok, this seriously sucks. We use them to flush a user page but don't
535 * know the virtual address, so we have to blast away the whole icache
536 * which is significantly more expensive than the real thing. Otoh we at
537 * least know the kernel address of the page so we can flush it
541 struct flush_icache_page_args {
542 struct vm_area_struct *vma;
546 static inline void local_r4k_flush_icache_page(void *args)
548 struct flush_icache_page_args *fip_args = args;
549 struct vm_area_struct *vma = fip_args->vma;
550 struct page *page = fip_args->page;
553 * Tricky ... Because we don't know the virtual address we've got the
554 * choice of either invalidating the entire primary and secondary
555 * caches or invalidating the secondary caches also. With the subset
556 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
557 * secondary cache will result in any entries in the primary caches
558 * also getting invalidated which hopefully is a bit more economical.
560 if (cpu_has_subset_pcaches) {
561 unsigned long addr = (unsigned long) page_address(page);
563 r4k_blast_scache_page(addr);
564 ClearPageDcacheDirty(page);
569 if (!cpu_has_ic_fills_f_dc) {
570 unsigned long addr = (unsigned long) page_address(page);
571 r4k_blast_dcache_page(addr);
572 if (!cpu_icache_snoops_remote_store)
573 r4k_blast_scache_page(addr);
574 ClearPageDcacheDirty(page);
578 * We're not sure of the virtual address(es) involved here, so
579 * we have to flush the entire I-cache.
581 if (cpu_has_vtag_icache) {
582 int cpu = smp_processor_id();
584 if (cpu_context(cpu, vma->vm_mm) != 0)
585 drop_mmu_context(vma->vm_mm, cpu);
590 static void r4k_flush_icache_page(struct vm_area_struct *vma,
593 struct flush_icache_page_args args;
596 * If there's no context yet, or the page isn't executable, no I-cache
599 if (!(vma->vm_flags & VM_EXEC))
605 on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
609 #ifdef CONFIG_DMA_NONCOHERENT
611 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
613 unsigned long end, a;
615 /* Catch bad driver code */
618 if (cpu_has_subset_pcaches) {
619 unsigned long sc_lsize = current_cpu_data.scache.linesz;
621 if (size >= scache_size) {
626 a = addr & ~(sc_lsize - 1);
627 end = (addr + size - 1) & ~(sc_lsize - 1);
629 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
638 * Either no secondary cache or the available caches don't have the
639 * subset property so we have to flush the primary caches
642 if (size >= dcache_size) {
645 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
647 R4600_HIT_CACHEOP_WAR_IMPL;
648 a = addr & ~(dc_lsize - 1);
649 end = (addr + size - 1) & ~(dc_lsize - 1);
651 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
658 bc_wback_inv(addr, size);
661 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
663 unsigned long end, a;
665 /* Catch bad driver code */
668 if (cpu_has_subset_pcaches) {
669 unsigned long sc_lsize = current_cpu_data.scache.linesz;
671 if (size >= scache_size) {
676 a = addr & ~(sc_lsize - 1);
677 end = (addr + size - 1) & ~(sc_lsize - 1);
679 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
687 if (size >= dcache_size) {
690 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
692 R4600_HIT_CACHEOP_WAR_IMPL;
693 a = addr & ~(dc_lsize - 1);
694 end = (addr + size - 1) & ~(dc_lsize - 1);
696 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
705 #endif /* CONFIG_DMA_NONCOHERENT */
708 * While we're protected against bad userland addresses we don't care
709 * very much about what happens in that case. Usually a segmentation
710 * fault will dump the process later on anyway ...
712 static void local_r4k_flush_cache_sigtramp(void * arg)
714 unsigned long ic_lsize = current_cpu_data.icache.linesz;
715 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
716 unsigned long sc_lsize = current_cpu_data.scache.linesz;
717 unsigned long addr = (unsigned long) arg;
719 R4600_HIT_CACHEOP_WAR_IMPL;
720 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
721 if (!cpu_icache_snoops_remote_store)
722 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
723 protected_flush_icache_line(addr & ~(ic_lsize - 1));
724 if (MIPS4K_ICACHE_REFILL_WAR) {
725 __asm__ __volatile__ (
740 : "i" (Hit_Invalidate_I));
742 if (MIPS_CACHE_SYNC_WAR)
743 __asm__ __volatile__ ("sync");
746 static void r4k_flush_cache_sigtramp(unsigned long addr)
748 on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
751 static void r4k_flush_icache_all(void)
753 if (cpu_has_vtag_icache)
757 static inline void rm7k_erratum31(void)
759 const unsigned long ic_lsize = 32;
762 /* RM7000 erratum #31. The icache is screwed at startup. */
766 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
767 __asm__ __volatile__ (
770 "cache\t%1, 0(%0)\n\t"
771 "cache\t%1, 0x1000(%0)\n\t"
772 "cache\t%1, 0x2000(%0)\n\t"
773 "cache\t%1, 0x3000(%0)\n\t"
774 "cache\t%2, 0(%0)\n\t"
775 "cache\t%2, 0x1000(%0)\n\t"
776 "cache\t%2, 0x2000(%0)\n\t"
777 "cache\t%2, 0x3000(%0)\n\t"
778 "cache\t%1, 0(%0)\n\t"
779 "cache\t%1, 0x1000(%0)\n\t"
780 "cache\t%1, 0x2000(%0)\n\t"
781 "cache\t%1, 0x3000(%0)\n\t"
785 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
789 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
790 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
793 static void __init probe_pcache(void)
795 struct cpuinfo_mips *c = ¤t_cpu_data;
796 unsigned int config = read_c0_config();
797 unsigned int prid = read_c0_prid();
798 unsigned long config1;
801 switch (c->cputype) {
802 case CPU_R4600: /* QED style two way caches? */
806 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
807 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
809 c->icache.waybit = ffs(icache_size/2) - 1;
811 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
812 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
814 c->dcache.waybit= ffs(dcache_size/2) - 1;
816 c->options |= MIPS_CPU_CACHE_CDEX_P;
821 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
822 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
826 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
827 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
829 c->dcache.waybit = 0;
831 c->options |= MIPS_CPU_CACHE_CDEX_P;
835 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
836 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
840 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
841 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
843 c->dcache.waybit = 0;
845 c->options |= MIPS_CPU_CACHE_CDEX_P;
855 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
856 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
858 c->icache.waybit = 0; /* doesn't matter */
860 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
861 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
863 c->dcache.waybit = 0; /* does not matter */
865 c->options |= MIPS_CPU_CACHE_CDEX_P;
870 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
871 c->icache.linesz = 64;
873 c->icache.waybit = 0;
875 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
876 c->dcache.linesz = 32;
878 c->dcache.waybit = 0;
880 c->options |= MIPS_CPU_PREFETCH;
884 write_c0_config(config & ~CONF_EB);
886 /* Workaround for cache instruction bug of VR4131 */
887 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
888 c->processor_id == 0x0c82U) {
889 config &= ~0x00000030U;
890 config |= 0x00410000U;
891 write_c0_config(config);
893 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
894 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
896 c->icache.waybit = ffs(icache_size/2) - 1;
898 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
899 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
901 c->dcache.waybit = ffs(dcache_size/2) - 1;
903 c->options |= MIPS_CPU_CACHE_CDEX_P;
912 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
913 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
915 c->icache.waybit = 0; /* doesn't matter */
917 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
918 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
920 c->dcache.waybit = 0; /* does not matter */
922 c->options |= MIPS_CPU_CACHE_CDEX_P;
929 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
930 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
932 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
934 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
935 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
937 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
939 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
940 c->options |= MIPS_CPU_CACHE_CDEX_P;
942 c->options |= MIPS_CPU_PREFETCH;
946 if (!(config & MIPS_CONF_M))
947 panic("Don't know how to probe P-caches on this cpu.");
950 * So we seem to be a MIPS32 or MIPS64 CPU
951 * So let's probe the I-cache ...
953 config1 = read_c0_config1();
955 if ((lsize = ((config1 >> 19) & 7)))
956 c->icache.linesz = 2 << lsize;
958 c->icache.linesz = lsize;
959 c->icache.sets = 64 << ((config1 >> 22) & 7);
960 c->icache.ways = 1 + ((config1 >> 16) & 7);
962 icache_size = c->icache.sets *
965 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
967 if (config & 0x8) /* VI bit */
968 c->icache.flags |= MIPS_CACHE_VTAG;
971 * Now probe the MIPS32 / MIPS64 data cache.
975 if ((lsize = ((config1 >> 10) & 7)))
976 c->dcache.linesz = 2 << lsize;
978 c->dcache.linesz= lsize;
979 c->dcache.sets = 64 << ((config1 >> 13) & 7);
980 c->dcache.ways = 1 + ((config1 >> 7) & 7);
982 dcache_size = c->dcache.sets *
985 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
987 c->options |= MIPS_CPU_PREFETCH;
992 * Processor configuration sanity check for the R4000SC erratum
993 * #5. With page sizes larger than 32kB there is no possibility
994 * to get a VCE exception anymore so we don't care about this
995 * misconfiguration. The case is rather theoretical anyway;
996 * presumably no vendor is shipping his hardware in the "bad"
999 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1000 !(config & CONF_SC) && c->icache.linesz != 16 &&
1001 PAGE_SIZE <= 0x8000)
1002 panic("Improper R4000SC processor configuration detected");
1004 /* compute a couple of other cache variables */
1005 c->icache.waysize = icache_size / c->icache.ways;
1006 c->dcache.waysize = dcache_size / c->dcache.ways;
1008 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
1009 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
1012 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1013 * 2-way virtually indexed so normally would suffer from aliases. So
1014 * normally they'd suffer from aliases but magic in the hardware deals
1015 * with that for us so we don't need to take care ourselves.
1017 switch (c->cputype) {
1025 if (!(read_c0_config7() & (1 << 16)))
1027 if (c->dcache.waysize > PAGE_SIZE)
1028 c->dcache.flags |= MIPS_CACHE_ALIASES;
1031 switch (c->cputype) {
1034 * Some older 20Kc chips doesn't have the 'VI' bit in
1035 * the config register.
1037 c->icache.flags |= MIPS_CACHE_VTAG;
1045 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1049 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1051 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
1052 way_string[c->icache.ways], c->icache.linesz);
1054 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1055 dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
1059 * If you even _breathe_ on this function, look at the gcc output and make sure
1060 * it does not pop things on and off the stack for the cache sizing loop that
1061 * executes in KSEG1 space or else you will crash and burn badly. You have
1064 static int __init probe_scache(void)
1066 extern unsigned long stext;
1067 unsigned long flags, addr, begin, end, pow2;
1068 unsigned int config = read_c0_config();
1069 struct cpuinfo_mips *c = ¤t_cpu_data;
1072 if (config & CONF_SC)
1075 begin = (unsigned long) &stext;
1076 begin &= ~((4 * 1024 * 1024) - 1);
1077 end = begin + (4 * 1024 * 1024);
1080 * This is such a bitch, you'd think they would make it easy to do
1081 * this. Away you daemons of stupidity!
1083 local_irq_save(flags);
1085 /* Fill each size-multiple cache line with a valid tag. */
1087 for (addr = begin; addr < end; addr = (begin + pow2)) {
1088 unsigned long *p = (unsigned long *) addr;
1089 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1093 /* Load first line with zero (therefore invalid) tag. */
1096 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1097 cache_op(Index_Store_Tag_I, begin);
1098 cache_op(Index_Store_Tag_D, begin);
1099 cache_op(Index_Store_Tag_SD, begin);
1101 /* Now search for the wrap around point. */
1102 pow2 = (128 * 1024);
1104 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1105 cache_op(Index_Load_Tag_SD, addr);
1106 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1107 if (!read_c0_taglo())
1111 local_irq_restore(flags);
1115 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1117 c->dcache.waybit = 0; /* does not matter */
1122 typedef int (*probe_func_t)(unsigned long);
1123 extern int r5k_sc_init(void);
1124 extern int rm7k_sc_init(void);
1126 static void __init setup_scache(void)
1128 struct cpuinfo_mips *c = ¤t_cpu_data;
1129 unsigned int config = read_c0_config();
1130 probe_func_t probe_scache_kseg1;
1134 * Do the probing thing on R4000SC and R4400SC processors. Other
1135 * processors don't have a S-cache that would be relevant to the
1136 * Linux memory managment.
1138 switch (c->cputype) {
1143 probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache));
1144 sc_present = probe_scache_kseg1(config);
1146 c->options |= MIPS_CPU_CACHE_CDEX_S;
1151 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1152 c->scache.linesz = 64 << ((config >> 13) & 1);
1154 c->scache.waybit= 0;
1160 #ifdef CONFIG_R5000_CPU_SCACHE
1167 #ifdef CONFIG_RM7000_CPU_SCACHE
1179 if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1180 c->isa_level == MIPS_CPU_ISA_M64) &&
1181 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1182 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1184 /* compute a couple of other cache variables */
1185 c->scache.waysize = scache_size / c->scache.ways;
1187 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1189 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1190 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1192 c->options |= MIPS_CPU_SUBSET_CACHES;
1195 static inline void coherency_setup(void)
1197 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1200 * c0_status.cu=0 specifies that updates by the sc instruction use
1201 * the coherency mode specified by the TLB; 1 means cachable
1202 * coherent update on write will be used. Not all processors have
1203 * this bit and; some wire it to zero, others like Toshiba had the
1204 * silly idea of putting something else there ...
1206 switch (current_cpu_data.cputype) {
1213 clear_c0_config(CONF_CU);
1218 void __init ld_mmu_r4xx0(void)
1220 extern void build_clear_page(void);
1221 extern void build_copy_page(void);
1222 extern char except_vec2_generic;
1223 struct cpuinfo_mips *c = ¤t_cpu_data;
1225 /* Default cache error handler for R4000 and R5000 family */
1226 memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
1227 memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1232 r4k_blast_dcache_page_setup();
1233 r4k_blast_dcache_page_indexed_setup();
1234 r4k_blast_dcache_setup();
1235 r4k_blast_icache_page_setup();
1236 r4k_blast_icache_page_indexed_setup();
1237 r4k_blast_icache_setup();
1238 r4k_blast_scache_page_setup();
1239 r4k_blast_scache_page_indexed_setup();
1240 r4k_blast_scache_setup();
1243 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1244 * This code supports virtually indexed processors and will be
1245 * unnecessarily inefficient on physically indexed processors.
1247 shm_align_mask = max_t( unsigned long,
1248 c->dcache.sets * c->dcache.linesz - 1,
1251 flush_cache_all = r4k_flush_cache_all;
1252 __flush_cache_all = r4k___flush_cache_all;
1253 flush_cache_mm = r4k_flush_cache_mm;
1254 flush_cache_page = r4k_flush_cache_page;
1255 flush_icache_page = r4k_flush_icache_page;
1256 flush_cache_range = r4k_flush_cache_range;
1258 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1259 flush_icache_all = r4k_flush_icache_all;
1260 flush_data_cache_page = r4k_flush_data_cache_page;
1261 flush_icache_range = r4k_flush_icache_range;
1263 #ifdef CONFIG_DMA_NONCOHERENT
1264 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1265 _dma_cache_wback = r4k_dma_cache_wback_inv;
1266 _dma_cache_inv = r4k_dma_cache_inv;
1269 __flush_cache_all();