2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
15 #include <linux/bitops.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
21 #include <asm/cpu-features.h>
24 #include <asm/pgtable.h>
25 #include <asm/r4kcache.h>
26 #include <asm/system.h>
27 #include <asm/mmu_context.h>
29 #include <asm/cacheflush.h> /* for run_uncached() */
31 static unsigned long icache_size, dcache_size, scache_size;
34 * Dummy cache handling routines for machines without boardcaches
36 static void no_sc_noop(void) {}
38 static struct bcache_ops no_sc_ops = {
39 .bc_enable = (void *)no_sc_noop,
40 .bc_disable = (void *)no_sc_noop,
41 .bc_wback_inv = (void *)no_sc_noop,
42 .bc_inv = (void *)no_sc_noop
45 struct bcache_ops *bcops = &no_sc_ops;
47 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
48 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
50 #define R4600_HIT_CACHEOP_WAR_IMPL \
52 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
53 *(volatile unsigned long *)CKSEG1; \
54 if (R4600_V1_HIT_CACHEOP_WAR) \
55 __asm__ __volatile__("nop;nop;nop;nop"); \
58 static void (*r4k_blast_dcache_page)(unsigned long addr);
60 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
62 R4600_HIT_CACHEOP_WAR_IMPL;
63 blast_dcache32_page(addr);
66 static inline void r4k_blast_dcache_page_setup(void)
68 unsigned long dc_lsize = cpu_dcache_line_size();
71 r4k_blast_dcache_page = blast_dcache16_page;
72 else if (dc_lsize == 32)
73 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
76 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
78 static inline void r4k_blast_dcache_page_indexed_setup(void)
80 unsigned long dc_lsize = cpu_dcache_line_size();
83 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
84 else if (dc_lsize == 32)
85 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
88 static void (* r4k_blast_dcache)(void);
90 static inline void r4k_blast_dcache_setup(void)
92 unsigned long dc_lsize = cpu_dcache_line_size();
95 r4k_blast_dcache = blast_dcache16;
96 else if (dc_lsize == 32)
97 r4k_blast_dcache = blast_dcache32;
100 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
101 #define JUMP_TO_ALIGN(order) \
102 __asm__ __volatile__( \
104 ".align\t" #order "\n\t" \
107 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
108 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
110 static inline void blast_r4600_v1_icache32(void)
114 local_irq_save(flags);
116 local_irq_restore(flags);
119 static inline void tx49_blast_icache32(void)
121 unsigned long start = INDEX_BASE;
122 unsigned long end = start + current_cpu_data.icache.waysize;
123 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
124 unsigned long ws_end = current_cpu_data.icache.ways <<
125 current_cpu_data.icache.waybit;
126 unsigned long ws, addr;
128 CACHE32_UNROLL32_ALIGN2;
129 /* I'm in even chunk. blast odd chunks */
130 for (ws = 0; ws < ws_end; ws += ws_inc)
131 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
132 cache32_unroll32(addr|ws,Index_Invalidate_I);
133 CACHE32_UNROLL32_ALIGN;
134 /* I'm in odd chunk. blast even chunks */
135 for (ws = 0; ws < ws_end; ws += ws_inc)
136 for (addr = start; addr < end; addr += 0x400 * 2)
137 cache32_unroll32(addr|ws,Index_Invalidate_I);
140 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
144 local_irq_save(flags);
145 blast_icache32_page_indexed(page);
146 local_irq_restore(flags);
149 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
151 unsigned long start = page;
152 unsigned long end = start + PAGE_SIZE;
153 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
154 unsigned long ws_end = current_cpu_data.icache.ways <<
155 current_cpu_data.icache.waybit;
156 unsigned long ws, addr;
158 CACHE32_UNROLL32_ALIGN2;
159 /* I'm in even chunk. blast odd chunks */
160 for (ws = 0; ws < ws_end; ws += ws_inc)
161 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
162 cache32_unroll32(addr|ws,Index_Invalidate_I);
163 CACHE32_UNROLL32_ALIGN;
164 /* I'm in odd chunk. blast even chunks */
165 for (ws = 0; ws < ws_end; ws += ws_inc)
166 for (addr = start; addr < end; addr += 0x400 * 2)
167 cache32_unroll32(addr|ws,Index_Invalidate_I);
170 static void (* r4k_blast_icache_page)(unsigned long addr);
172 static inline void r4k_blast_icache_page_setup(void)
174 unsigned long ic_lsize = cpu_icache_line_size();
177 r4k_blast_icache_page = blast_icache16_page;
178 else if (ic_lsize == 32)
179 r4k_blast_icache_page = blast_icache32_page;
180 else if (ic_lsize == 64)
181 r4k_blast_icache_page = blast_icache64_page;
185 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
187 static inline void r4k_blast_icache_page_indexed_setup(void)
189 unsigned long ic_lsize = cpu_icache_line_size();
192 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
193 else if (ic_lsize == 32) {
194 if (TX49XX_ICACHE_INDEX_INV_WAR)
195 r4k_blast_icache_page_indexed =
196 tx49_blast_icache32_page_indexed;
197 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
198 r4k_blast_icache_page_indexed =
199 blast_icache32_r4600_v1_page_indexed;
201 r4k_blast_icache_page_indexed =
202 blast_icache32_page_indexed;
203 } else if (ic_lsize == 64)
204 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
207 static void (* r4k_blast_icache)(void);
209 static inline void r4k_blast_icache_setup(void)
211 unsigned long ic_lsize = cpu_icache_line_size();
214 r4k_blast_icache = blast_icache16;
215 else if (ic_lsize == 32) {
216 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
217 r4k_blast_icache = blast_r4600_v1_icache32;
218 else if (TX49XX_ICACHE_INDEX_INV_WAR)
219 r4k_blast_icache = tx49_blast_icache32;
221 r4k_blast_icache = blast_icache32;
222 } else if (ic_lsize == 64)
223 r4k_blast_icache = blast_icache64;
226 static void (* r4k_blast_scache_page)(unsigned long addr);
228 static inline void r4k_blast_scache_page_setup(void)
230 unsigned long sc_lsize = cpu_scache_line_size();
233 r4k_blast_scache_page = blast_scache16_page;
234 else if (sc_lsize == 32)
235 r4k_blast_scache_page = blast_scache32_page;
236 else if (sc_lsize == 64)
237 r4k_blast_scache_page = blast_scache64_page;
238 else if (sc_lsize == 128)
239 r4k_blast_scache_page = blast_scache128_page;
242 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
244 static inline void r4k_blast_scache_page_indexed_setup(void)
246 unsigned long sc_lsize = cpu_scache_line_size();
249 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
250 else if (sc_lsize == 32)
251 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
252 else if (sc_lsize == 64)
253 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
254 else if (sc_lsize == 128)
255 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
258 static void (* r4k_blast_scache)(void);
260 static inline void r4k_blast_scache_setup(void)
262 unsigned long sc_lsize = cpu_scache_line_size();
265 r4k_blast_scache = blast_scache16;
266 else if (sc_lsize == 32)
267 r4k_blast_scache = blast_scache32;
268 else if (sc_lsize == 64)
269 r4k_blast_scache = blast_scache64;
270 else if (sc_lsize == 128)
271 r4k_blast_scache = blast_scache128;
275 * This is former mm's flush_cache_all() which really should be
276 * flush_cache_vunmap these days ...
278 static inline void local_r4k_flush_cache_all(void * args)
284 static void r4k_flush_cache_all(void)
286 if (!cpu_has_dc_aliases)
289 on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
292 static inline void local_r4k___flush_cache_all(void * args)
297 switch (current_cpu_data.cputype) {
308 static void r4k___flush_cache_all(void)
310 on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
313 static inline void local_r4k_flush_cache_range(void * args)
315 struct vm_area_struct *vma = args;
318 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
321 exec = vma->vm_flags & VM_EXEC;
322 if (cpu_has_dc_aliases || exec)
328 static void r4k_flush_cache_range(struct vm_area_struct *vma,
329 unsigned long start, unsigned long end)
331 on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
334 static inline void local_r4k_flush_cache_mm(void * args)
336 struct mm_struct *mm = args;
338 if (!cpu_context(smp_processor_id(), mm))
345 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
346 * only flush the primary caches but R10000 and R12000 behave sane ...
348 if (current_cpu_data.cputype == CPU_R4000SC ||
349 current_cpu_data.cputype == CPU_R4000MC ||
350 current_cpu_data.cputype == CPU_R4400SC ||
351 current_cpu_data.cputype == CPU_R4400MC)
355 static void r4k_flush_cache_mm(struct mm_struct *mm)
357 if (!cpu_has_dc_aliases)
360 on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
363 struct flush_cache_page_args {
364 struct vm_area_struct *vma;
368 static inline void local_r4k_flush_cache_page(void *args)
370 struct flush_cache_page_args *fcp_args = args;
371 struct vm_area_struct *vma = fcp_args->vma;
372 unsigned long page = fcp_args->page;
373 int exec = vma->vm_flags & VM_EXEC;
374 struct mm_struct *mm = vma->vm_mm;
381 * If ownes no valid ASID yet, cannot possibly have gotten
382 * this page into the cache.
384 if (cpu_context(smp_processor_id(), mm) == 0)
388 pgdp = pgd_offset(mm, page);
389 pudp = pud_offset(pgdp, page);
390 pmdp = pmd_offset(pudp, page);
391 ptep = pte_offset(pmdp, page);
394 * If the page isn't marked valid, the page cannot possibly be
397 if (!(pte_val(*ptep) & _PAGE_PRESENT))
401 * Doing flushes for another ASID than the current one is
402 * too difficult since stupid R4k caches do a TLB translation
403 * for every cache flush operation. So we do indexed flushes
404 * in that case, which doesn't overly flush the cache too much.
406 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
407 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
408 r4k_blast_dcache_page(page);
409 if (exec && !cpu_icache_snoops_remote_store)
410 r4k_blast_scache_page(page);
413 r4k_blast_icache_page(page);
419 * Do indexed flush, too much work to get the (possible) TLB refills
422 page = INDEX_BASE + (page & (dcache_size - 1));
423 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
424 r4k_blast_dcache_page_indexed(page);
425 if (exec && !cpu_icache_snoops_remote_store)
426 r4k_blast_scache_page_indexed(page);
429 if (cpu_has_vtag_icache) {
430 int cpu = smp_processor_id();
432 if (cpu_context(cpu, mm) != 0)
433 drop_mmu_context(mm, cpu);
435 r4k_blast_icache_page_indexed(page);
439 static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
441 struct flush_cache_page_args args;
446 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
449 static inline void local_r4k_flush_data_cache_page(void * addr)
451 r4k_blast_dcache_page((unsigned long) addr);
454 static void r4k_flush_data_cache_page(unsigned long addr)
456 on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
459 struct flush_icache_range_args {
460 unsigned long __user start;
461 unsigned long __user end;
464 static inline void local_r4k_flush_icache_range(void *args)
466 struct flush_icache_range_args *fir_args = args;
467 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
468 unsigned long ic_lsize = current_cpu_data.icache.linesz;
469 unsigned long sc_lsize = current_cpu_data.scache.linesz;
470 unsigned long start = fir_args->start;
471 unsigned long end = fir_args->end;
472 unsigned long addr, aend;
474 if (!cpu_has_ic_fills_f_dc) {
475 if (end - start > dcache_size) {
478 addr = start & ~(dc_lsize - 1);
479 aend = (end - 1) & ~(dc_lsize - 1);
482 /* Hit_Writeback_Inv_D */
483 protected_writeback_dcache_line(addr);
490 if (!cpu_icache_snoops_remote_store) {
491 if (end - start > scache_size) {
494 addr = start & ~(sc_lsize - 1);
495 aend = (end - 1) & ~(sc_lsize - 1);
498 /* Hit_Writeback_Inv_D */
499 protected_writeback_scache_line(addr);
508 if (end - start > icache_size)
511 addr = start & ~(ic_lsize - 1);
512 aend = (end - 1) & ~(ic_lsize - 1);
514 /* Hit_Invalidate_I */
515 protected_flush_icache_line(addr);
523 static void r4k_flush_icache_range(unsigned long __user start,
524 unsigned long __user end)
526 struct flush_icache_range_args args;
531 on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
535 * Ok, this seriously sucks. We use them to flush a user page but don't
536 * know the virtual address, so we have to blast away the whole icache
537 * which is significantly more expensive than the real thing. Otoh we at
538 * least know the kernel address of the page so we can flush it
542 struct flush_icache_page_args {
543 struct vm_area_struct *vma;
547 static inline void local_r4k_flush_icache_page(void *args)
549 struct flush_icache_page_args *fip_args = args;
550 struct vm_area_struct *vma = fip_args->vma;
551 struct page *page = fip_args->page;
554 * Tricky ... Because we don't know the virtual address we've got the
555 * choice of either invalidating the entire primary and secondary
556 * caches or invalidating the secondary caches also. With the subset
557 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
558 * secondary cache will result in any entries in the primary caches
559 * also getting invalidated which hopefully is a bit more economical.
561 if (cpu_has_subset_pcaches) {
562 unsigned long addr = (unsigned long) page_address(page);
564 r4k_blast_scache_page(addr);
565 ClearPageDcacheDirty(page);
570 if (!cpu_has_ic_fills_f_dc) {
571 unsigned long addr = (unsigned long) page_address(page);
572 r4k_blast_dcache_page(addr);
573 if (!cpu_icache_snoops_remote_store)
574 r4k_blast_scache_page(addr);
575 ClearPageDcacheDirty(page);
579 * We're not sure of the virtual address(es) involved here, so
580 * we have to flush the entire I-cache.
582 if (cpu_has_vtag_icache) {
583 int cpu = smp_processor_id();
585 if (cpu_context(cpu, vma->vm_mm) != 0)
586 drop_mmu_context(vma->vm_mm, cpu);
591 static void r4k_flush_icache_page(struct vm_area_struct *vma,
594 struct flush_icache_page_args args;
597 * If there's no context yet, or the page isn't executable, no I-cache
600 if (!(vma->vm_flags & VM_EXEC))
606 on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
610 #ifdef CONFIG_DMA_NONCOHERENT
612 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
614 unsigned long end, a;
616 /* Catch bad driver code */
619 if (cpu_has_subset_pcaches) {
620 unsigned long sc_lsize = current_cpu_data.scache.linesz;
622 if (size >= scache_size) {
627 a = addr & ~(sc_lsize - 1);
628 end = (addr + size - 1) & ~(sc_lsize - 1);
630 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
639 * Either no secondary cache or the available caches don't have the
640 * subset property so we have to flush the primary caches
643 if (size >= dcache_size) {
646 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
648 R4600_HIT_CACHEOP_WAR_IMPL;
649 a = addr & ~(dc_lsize - 1);
650 end = (addr + size - 1) & ~(dc_lsize - 1);
652 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
659 bc_wback_inv(addr, size);
662 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
664 unsigned long end, a;
666 /* Catch bad driver code */
669 if (cpu_has_subset_pcaches) {
670 unsigned long sc_lsize = current_cpu_data.scache.linesz;
672 if (size >= scache_size) {
677 a = addr & ~(sc_lsize - 1);
678 end = (addr + size - 1) & ~(sc_lsize - 1);
680 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
688 if (size >= dcache_size) {
691 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
693 R4600_HIT_CACHEOP_WAR_IMPL;
694 a = addr & ~(dc_lsize - 1);
695 end = (addr + size - 1) & ~(dc_lsize - 1);
697 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
706 #endif /* CONFIG_DMA_NONCOHERENT */
709 * While we're protected against bad userland addresses we don't care
710 * very much about what happens in that case. Usually a segmentation
711 * fault will dump the process later on anyway ...
713 static void local_r4k_flush_cache_sigtramp(void * arg)
715 unsigned long ic_lsize = current_cpu_data.icache.linesz;
716 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
717 unsigned long sc_lsize = current_cpu_data.scache.linesz;
718 unsigned long addr = (unsigned long) arg;
720 R4600_HIT_CACHEOP_WAR_IMPL;
721 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
722 if (!cpu_icache_snoops_remote_store)
723 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
724 protected_flush_icache_line(addr & ~(ic_lsize - 1));
725 if (MIPS4K_ICACHE_REFILL_WAR) {
726 __asm__ __volatile__ (
741 : "i" (Hit_Invalidate_I));
743 if (MIPS_CACHE_SYNC_WAR)
744 __asm__ __volatile__ ("sync");
747 static void r4k_flush_cache_sigtramp(unsigned long addr)
749 on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
752 static void r4k_flush_icache_all(void)
754 if (cpu_has_vtag_icache)
758 static inline void rm7k_erratum31(void)
760 const unsigned long ic_lsize = 32;
763 /* RM7000 erratum #31. The icache is screwed at startup. */
767 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
768 __asm__ __volatile__ (
771 "cache\t%1, 0(%0)\n\t"
772 "cache\t%1, 0x1000(%0)\n\t"
773 "cache\t%1, 0x2000(%0)\n\t"
774 "cache\t%1, 0x3000(%0)\n\t"
775 "cache\t%2, 0(%0)\n\t"
776 "cache\t%2, 0x1000(%0)\n\t"
777 "cache\t%2, 0x2000(%0)\n\t"
778 "cache\t%2, 0x3000(%0)\n\t"
779 "cache\t%1, 0(%0)\n\t"
780 "cache\t%1, 0x1000(%0)\n\t"
781 "cache\t%1, 0x2000(%0)\n\t"
782 "cache\t%1, 0x3000(%0)\n\t"
786 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
790 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
791 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
794 static void __init probe_pcache(void)
796 struct cpuinfo_mips *c = ¤t_cpu_data;
797 unsigned int config = read_c0_config();
798 unsigned int prid = read_c0_prid();
799 unsigned long config1;
802 switch (c->cputype) {
803 case CPU_R4600: /* QED style two way caches? */
807 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
808 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
810 c->icache.waybit = ffs(icache_size/2) - 1;
812 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
813 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
815 c->dcache.waybit= ffs(dcache_size/2) - 1;
817 c->options |= MIPS_CPU_CACHE_CDEX_P;
822 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
823 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
827 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
828 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
830 c->dcache.waybit = 0;
832 c->options |= MIPS_CPU_CACHE_CDEX_P;
836 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
837 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
841 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
842 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
844 c->dcache.waybit = 0;
846 c->options |= MIPS_CPU_CACHE_CDEX_P;
856 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
857 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
859 c->icache.waybit = 0; /* doesn't matter */
861 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
862 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
864 c->dcache.waybit = 0; /* does not matter */
866 c->options |= MIPS_CPU_CACHE_CDEX_P;
871 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
872 c->icache.linesz = 64;
874 c->icache.waybit = 0;
876 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
877 c->dcache.linesz = 32;
879 c->dcache.waybit = 0;
881 c->options |= MIPS_CPU_PREFETCH;
885 write_c0_config(config & ~CONF_EB);
887 /* Workaround for cache instruction bug of VR4131 */
888 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
889 c->processor_id == 0x0c82U) {
890 config &= ~0x00000030U;
891 config |= 0x00410000U;
892 write_c0_config(config);
894 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
895 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
897 c->icache.waybit = ffs(icache_size/2) - 1;
899 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
900 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
902 c->dcache.waybit = ffs(dcache_size/2) - 1;
904 c->options |= MIPS_CPU_CACHE_CDEX_P;
913 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
914 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
916 c->icache.waybit = 0; /* doesn't matter */
918 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
919 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
921 c->dcache.waybit = 0; /* does not matter */
923 c->options |= MIPS_CPU_CACHE_CDEX_P;
930 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
931 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
933 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
935 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
936 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
938 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
940 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
941 c->options |= MIPS_CPU_CACHE_CDEX_P;
943 c->options |= MIPS_CPU_PREFETCH;
947 if (!(config & MIPS_CONF_M))
948 panic("Don't know how to probe P-caches on this cpu.");
951 * So we seem to be a MIPS32 or MIPS64 CPU
952 * So let's probe the I-cache ...
954 config1 = read_c0_config1();
956 if ((lsize = ((config1 >> 19) & 7)))
957 c->icache.linesz = 2 << lsize;
959 c->icache.linesz = lsize;
960 c->icache.sets = 64 << ((config1 >> 22) & 7);
961 c->icache.ways = 1 + ((config1 >> 16) & 7);
963 icache_size = c->icache.sets *
966 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
968 if (config & 0x8) /* VI bit */
969 c->icache.flags |= MIPS_CACHE_VTAG;
972 * Now probe the MIPS32 / MIPS64 data cache.
976 if ((lsize = ((config1 >> 10) & 7)))
977 c->dcache.linesz = 2 << lsize;
979 c->dcache.linesz= lsize;
980 c->dcache.sets = 64 << ((config1 >> 13) & 7);
981 c->dcache.ways = 1 + ((config1 >> 7) & 7);
983 dcache_size = c->dcache.sets *
986 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
988 c->options |= MIPS_CPU_PREFETCH;
993 * Processor configuration sanity check for the R4000SC erratum
994 * #5. With page sizes larger than 32kB there is no possibility
995 * to get a VCE exception anymore so we don't care about this
996 * misconfiguration. The case is rather theoretical anyway;
997 * presumably no vendor is shipping his hardware in the "bad"
1000 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1001 !(config & CONF_SC) && c->icache.linesz != 16 &&
1002 PAGE_SIZE <= 0x8000)
1003 panic("Improper R4000SC processor configuration detected");
1005 /* compute a couple of other cache variables */
1006 c->icache.waysize = icache_size / c->icache.ways;
1007 c->dcache.waysize = dcache_size / c->dcache.ways;
1009 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
1010 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
1013 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1014 * 2-way virtually indexed so normally would suffer from aliases. So
1015 * normally they'd suffer from aliases but magic in the hardware deals
1016 * with that for us so we don't need to take care ourselves.
1018 switch (c->cputype) {
1026 if (!(read_c0_config7() & (1 << 16)))
1028 if (c->dcache.waysize > PAGE_SIZE)
1029 c->dcache.flags |= MIPS_CACHE_ALIASES;
1032 switch (c->cputype) {
1035 * Some older 20Kc chips doesn't have the 'VI' bit in
1036 * the config register.
1038 c->icache.flags |= MIPS_CACHE_VTAG;
1046 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1050 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1052 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
1053 way_string[c->icache.ways], c->icache.linesz);
1055 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1056 dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
1060 * If you even _breathe_ on this function, look at the gcc output and make sure
1061 * it does not pop things on and off the stack for the cache sizing loop that
1062 * executes in KSEG1 space or else you will crash and burn badly. You have
1065 static int __init probe_scache(void)
1067 extern unsigned long stext;
1068 unsigned long flags, addr, begin, end, pow2;
1069 unsigned int config = read_c0_config();
1070 struct cpuinfo_mips *c = ¤t_cpu_data;
1073 if (config & CONF_SC)
1076 begin = (unsigned long) &stext;
1077 begin &= ~((4 * 1024 * 1024) - 1);
1078 end = begin + (4 * 1024 * 1024);
1081 * This is such a bitch, you'd think they would make it easy to do
1082 * this. Away you daemons of stupidity!
1084 local_irq_save(flags);
1086 /* Fill each size-multiple cache line with a valid tag. */
1088 for (addr = begin; addr < end; addr = (begin + pow2)) {
1089 unsigned long *p = (unsigned long *) addr;
1090 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1094 /* Load first line with zero (therefore invalid) tag. */
1097 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1098 cache_op(Index_Store_Tag_I, begin);
1099 cache_op(Index_Store_Tag_D, begin);
1100 cache_op(Index_Store_Tag_SD, begin);
1102 /* Now search for the wrap around point. */
1103 pow2 = (128 * 1024);
1105 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1106 cache_op(Index_Load_Tag_SD, addr);
1107 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1108 if (!read_c0_taglo())
1112 local_irq_restore(flags);
1116 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1118 c->dcache.waybit = 0; /* does not matter */
1123 extern int r5k_sc_init(void);
1124 extern int rm7k_sc_init(void);
1126 static void __init setup_scache(void)
1128 struct cpuinfo_mips *c = ¤t_cpu_data;
1129 unsigned int config = read_c0_config();
1133 * Do the probing thing on R4000SC and R4400SC processors. Other
1134 * processors don't have a S-cache that would be relevant to the
1135 * Linux memory managment.
1137 switch (c->cputype) {
1142 sc_present = run_uncached(probe_scache);
1144 c->options |= MIPS_CPU_CACHE_CDEX_S;
1149 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1150 c->scache.linesz = 64 << ((config >> 13) & 1);
1152 c->scache.waybit= 0;
1158 #ifdef CONFIG_R5000_CPU_SCACHE
1165 #ifdef CONFIG_RM7000_CPU_SCACHE
1177 if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1178 c->isa_level == MIPS_CPU_ISA_M64) &&
1179 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1180 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1182 /* compute a couple of other cache variables */
1183 c->scache.waysize = scache_size / c->scache.ways;
1185 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1187 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1188 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1190 c->options |= MIPS_CPU_SUBSET_CACHES;
1193 static inline void coherency_setup(void)
1195 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1198 * c0_status.cu=0 specifies that updates by the sc instruction use
1199 * the coherency mode specified by the TLB; 1 means cachable
1200 * coherent update on write will be used. Not all processors have
1201 * this bit and; some wire it to zero, others like Toshiba had the
1202 * silly idea of putting something else there ...
1204 switch (current_cpu_data.cputype) {
1211 clear_c0_config(CONF_CU);
1216 void __init ld_mmu_r4xx0(void)
1218 extern void build_clear_page(void);
1219 extern void build_copy_page(void);
1220 extern char except_vec2_generic;
1221 struct cpuinfo_mips *c = ¤t_cpu_data;
1223 /* Default cache error handler for R4000 and R5000 family */
1224 memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
1225 memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1230 r4k_blast_dcache_page_setup();
1231 r4k_blast_dcache_page_indexed_setup();
1232 r4k_blast_dcache_setup();
1233 r4k_blast_icache_page_setup();
1234 r4k_blast_icache_page_indexed_setup();
1235 r4k_blast_icache_setup();
1236 r4k_blast_scache_page_setup();
1237 r4k_blast_scache_page_indexed_setup();
1238 r4k_blast_scache_setup();
1241 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1242 * This code supports virtually indexed processors and will be
1243 * unnecessarily inefficient on physically indexed processors.
1245 shm_align_mask = max_t( unsigned long,
1246 c->dcache.sets * c->dcache.linesz - 1,
1249 flush_cache_all = r4k_flush_cache_all;
1250 __flush_cache_all = r4k___flush_cache_all;
1251 flush_cache_mm = r4k_flush_cache_mm;
1252 flush_cache_page = r4k_flush_cache_page;
1253 flush_icache_page = r4k_flush_icache_page;
1254 flush_cache_range = r4k_flush_cache_range;
1256 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1257 flush_icache_all = r4k_flush_icache_all;
1258 flush_data_cache_page = r4k_flush_data_cache_page;
1259 flush_icache_range = r4k_flush_icache_range;
1261 #ifdef CONFIG_DMA_NONCOHERENT
1262 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1263 _dma_cache_wback = r4k_dma_cache_wback_inv;
1264 _dma_cache_inv = r4k_dma_cache_inv;
1267 __flush_cache_all();