2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004,2005 by Thiemo Seufer
13 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
20 #include <asm/pgtable.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
28 /* #define DEBUG_TLB */
30 static __init int __attribute__((unused)) r45k_bvahwbug(void)
32 /* XXX: We should probe for the presence of this bug, but we don't. */
36 static __init int __attribute__((unused)) r4k_250MHZhwbug(void)
38 /* XXX: We should probe for the presence of this bug, but we don't. */
42 static __init int __attribute__((unused)) bcm1250_m3_war(void)
44 return BCM1250_M3_WAR;
47 static __init int __attribute__((unused)) r10000_llsc_war(void)
49 return R10000_LLSC_WAR;
53 * A little micro-assembler, intended for TLB refill handler
54 * synthesizing. It is intentionally kept simple, does only support
55 * a subset of instructions, and does not try to hide pipeline effects
56 * like branch delay slots.
82 #define IMM_MASK 0xffff
84 #define JIMM_MASK 0x3ffffff
86 #define FUNC_MASK 0x2f
91 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
92 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
93 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
94 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
95 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
96 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
97 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
98 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
99 insn_tlbwr, insn_xor, insn_xori
108 /* This macro sets the non-variable bits of an instruction. */
109 #define M(a, b, c, d, e, f) \
117 static __initdata struct insn insn_table[] = {
118 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
119 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
120 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
121 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
122 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
123 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
124 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
125 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
126 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
127 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
128 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
129 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
130 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
131 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD },
132 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD },
133 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
134 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
135 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
136 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
137 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
140 { insn_j, M(j_op,0,0,0,0,0), JIMM },
141 { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
142 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
143 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
144 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
145 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
146 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
147 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
148 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD },
149 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD },
150 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
151 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
152 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
153 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
154 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
155 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
156 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
157 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
158 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
159 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
160 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
161 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
162 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
163 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
164 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
165 { insn_invalid, 0, 0 }
170 static __init u32 build_rs(u32 arg)
173 printk(KERN_WARNING "TLB synthesizer field overflow\n");
175 return (arg & RS_MASK) << RS_SH;
178 static __init u32 build_rt(u32 arg)
181 printk(KERN_WARNING "TLB synthesizer field overflow\n");
183 return (arg & RT_MASK) << RT_SH;
186 static __init u32 build_rd(u32 arg)
189 printk(KERN_WARNING "TLB synthesizer field overflow\n");
191 return (arg & RD_MASK) << RD_SH;
194 static __init u32 build_re(u32 arg)
197 printk(KERN_WARNING "TLB synthesizer field overflow\n");
199 return (arg & RE_MASK) << RE_SH;
202 static __init u32 build_simm(s32 arg)
204 if (arg > 0x7fff || arg < -0x8000)
205 printk(KERN_WARNING "TLB synthesizer field overflow\n");
210 static __init u32 build_uimm(u32 arg)
213 printk(KERN_WARNING "TLB synthesizer field overflow\n");
215 return arg & IMM_MASK;
218 static __init u32 build_bimm(s32 arg)
220 if (arg > 0x1ffff || arg < -0x20000)
221 printk(KERN_WARNING "TLB synthesizer field overflow\n");
224 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n");
226 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
229 static __init u32 build_jimm(u32 arg)
231 if (arg & ~((JIMM_MASK) << 2))
232 printk(KERN_WARNING "TLB synthesizer field overflow\n");
234 return (arg >> 2) & JIMM_MASK;
237 static __init u32 build_func(u32 arg)
239 if (arg & ~FUNC_MASK)
240 printk(KERN_WARNING "TLB synthesizer field overflow\n");
242 return arg & FUNC_MASK;
246 * The order of opcode arguments is implicitly left to right,
247 * starting with RS and ending with FUNC or IMM.
249 static void __init build_insn(u32 **buf, enum opcode opc, ...)
251 struct insn *ip = NULL;
256 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
257 if (insn_table[i].opcode == opc) {
263 panic("Unsupported TLB synthesizer instruction %d", opc);
267 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32));
268 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32));
269 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32));
270 if (ip->fields & RE) op |= build_re(va_arg(ap, u32));
271 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32));
272 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32));
273 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32));
274 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32));
275 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32));
282 #define I_u1u2u3(op) \
283 static inline void i##op(u32 **buf, unsigned int a, \
284 unsigned int b, unsigned int c) \
286 build_insn(buf, insn##op, a, b, c); \
289 #define I_u2u1u3(op) \
290 static inline void i##op(u32 **buf, unsigned int a, \
291 unsigned int b, unsigned int c) \
293 build_insn(buf, insn##op, b, a, c); \
296 #define I_u3u1u2(op) \
297 static inline void i##op(u32 **buf, unsigned int a, \
298 unsigned int b, unsigned int c) \
300 build_insn(buf, insn##op, b, c, a); \
303 #define I_u1u2s3(op) \
304 static inline void i##op(u32 **buf, unsigned int a, \
305 unsigned int b, signed int c) \
307 build_insn(buf, insn##op, a, b, c); \
310 #define I_u2s3u1(op) \
311 static inline void i##op(u32 **buf, unsigned int a, \
312 signed int b, unsigned int c) \
314 build_insn(buf, insn##op, c, a, b); \
317 #define I_u2u1s3(op) \
318 static inline void i##op(u32 **buf, unsigned int a, \
319 unsigned int b, signed int c) \
321 build_insn(buf, insn##op, b, a, c); \
325 static inline void i##op(u32 **buf, unsigned int a, \
328 build_insn(buf, insn##op, a, b); \
332 static inline void i##op(u32 **buf, unsigned int a, \
335 build_insn(buf, insn##op, a, b); \
339 static inline void i##op(u32 **buf, unsigned int a) \
341 build_insn(buf, insn##op, a); \
345 static inline void i##op(u32 **buf) \
347 build_insn(buf, insn##op); \
413 label_smp_pgtable_change,
414 label_r3000_write_probe_fail,
415 label_r3000_write_probe_ok
423 static __init void build_label(struct label **lab, u32 *addr,
432 static inline void l##lb(struct label **lab, u32 *addr) \
434 build_label(lab, addr, label##lb); \
446 L_LA(_smp_pgtable_change)
447 L_LA(_r3000_write_probe_fail)
448 L_LA(_r3000_write_probe_ok)
450 /* convenience macros for instructions */
452 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
453 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
454 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
455 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
456 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
457 # define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd)
458 # define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd)
459 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
460 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
461 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
462 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
463 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
465 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
466 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
467 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
468 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
469 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
470 # define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd)
471 # define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd)
472 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
473 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
474 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
475 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
476 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
479 #define i_b(buf, off) i_beq(buf, 0, 0, off)
480 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
481 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
482 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
483 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
484 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
485 #define i_nop(buf) i_sll(buf, 0, 0, 0)
486 #define i_ssnop(buf) i_sll(buf, 0, 0, 1)
487 #define i_ehb(buf) i_sll(buf, 0, 0, 3)
490 static __init int __attribute__((unused)) in_compat_space_p(long addr)
492 /* Is this address in 32bit compat space? */
493 return (((addr) & 0xffffffff00000000) == 0xffffffff00000000);
496 static __init int __attribute__((unused)) rel_highest(long val)
498 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
501 static __init int __attribute__((unused)) rel_higher(long val)
503 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
507 static __init int rel_hi(long val)
509 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
512 static __init int rel_lo(long val)
514 return ((val & 0xffff) ^ 0x8000) - 0x8000;
517 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
520 if (!in_compat_space_p(addr)) {
521 i_lui(buf, rs, rel_highest(addr));
522 if (rel_higher(addr))
523 i_daddiu(buf, rs, rs, rel_higher(addr));
525 i_dsll(buf, rs, rs, 16);
526 i_daddiu(buf, rs, rs, rel_hi(addr));
527 i_dsll(buf, rs, rs, 16);
529 i_dsll32(buf, rs, rs, 0);
532 i_lui(buf, rs, rel_hi(addr));
535 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs,
538 i_LA_mostly(buf, rs, addr);
540 i_ADDIU(buf, rs, rs, rel_lo(addr));
553 static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
557 (*rel)->type = R_MIPS_PC16;
562 static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
564 long laddr = (long)lab->addr;
565 long raddr = (long)rel->addr;
569 *rel->addr |= build_bimm(laddr - (raddr + 4));
573 panic("Unsupported TLB synthesizer relocation %d",
578 static __init void resolve_relocs(struct reloc *rel, struct label *lab)
582 for (; rel->lab != label_invalid; rel++)
583 for (l = lab; l->lab != label_invalid; l++)
584 if (rel->lab == l->lab)
585 __resolve_relocs(rel, l);
588 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
591 for (; rel->lab != label_invalid; rel++)
592 if (rel->addr >= first && rel->addr < end)
596 static __init void move_labels(struct label *lab, u32 *first, u32 *end,
599 for (; lab->lab != label_invalid; lab++)
600 if (lab->addr >= first && lab->addr < end)
604 static __init void copy_handler(struct reloc *rel, struct label *lab,
605 u32 *first, u32 *end, u32 *target)
607 long off = (long)(target - first);
609 memcpy(target, first, (end - first) * sizeof(u32));
611 move_relocs(rel, first, end, off);
612 move_labels(lab, first, end, off);
615 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
618 for (; rel->lab != label_invalid; rel++) {
619 if (rel->addr == addr
620 && (rel->type == R_MIPS_PC16
621 || rel->type == R_MIPS_26))
628 /* convenience functions for labeled branches */
629 static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r,
630 unsigned int reg, enum label_id l)
632 r_mips_pc16(r, *p, l);
636 static void __attribute__((unused)) il_b(u32 **p, struct reloc **r,
639 r_mips_pc16(r, *p, l);
643 static void il_beqz(u32 **p, struct reloc **r, unsigned int reg,
646 r_mips_pc16(r, *p, l);
650 static void __attribute__((unused))
651 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
653 r_mips_pc16(r, *p, l);
657 static void il_bnez(u32 **p, struct reloc **r, unsigned int reg,
660 r_mips_pc16(r, *p, l);
664 static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
667 r_mips_pc16(r, *p, l);
671 /* The only general purpose registers allowed in TLB handlers. */
675 /* Some CP0 registers */
677 #define C0_ENTRYLO0 2
678 #define C0_ENTRYLO1 3
680 #define C0_BADVADDR 8
681 #define C0_ENTRYHI 10
683 #define C0_XCONTEXT 20
686 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
688 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
691 /* The worst case length of the handler is around 18 instructions for
692 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
693 * Maximum space available is 32 instructions for R3000 and 64
694 * instructions for R4000.
696 * We deliberately chose a buffer size of 128, so we won't scribble
697 * over anything important on overflow before we panic.
699 static __initdata u32 tlb_handler[128];
701 /* simply assume worst case size for labels and relocs */
702 static __initdata struct label labels[128];
703 static __initdata struct reloc relocs[128];
706 * The R3000 TLB handler is simple.
708 static void __init build_r3000_tlb_refill_handler(void)
710 long pgdc = (long)pgd_current;
713 memset(tlb_handler, 0, sizeof(tlb_handler));
716 i_mfc0(&p, K0, C0_BADVADDR);
717 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */
718 i_lw(&p, K1, rel_lo(pgdc), K1);
719 i_srl(&p, K0, K0, 22); /* load delay */
720 i_sll(&p, K0, K0, 2);
721 i_addu(&p, K1, K1, K0);
722 i_mfc0(&p, K0, C0_CONTEXT);
723 i_lw(&p, K1, 0, K1); /* cp0 delay */
724 i_andi(&p, K0, K0, 0xffc); /* load delay */
725 i_addu(&p, K1, K1, K0);
727 i_nop(&p); /* load delay */
728 i_mtc0(&p, K0, C0_ENTRYLO0);
729 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
730 i_tlbwr(&p); /* cp0 delay */
732 i_rfe(&p); /* branch delay */
734 if (p > tlb_handler + 32)
735 panic("TLB refill handler space exceeded");
737 printk("Synthesized TLB handler (%u instructions).\n",
738 (unsigned int)(p - tlb_handler));
743 for (i = 0; i < (p - tlb_handler); i++)
744 printk("%08x\n", tlb_handler[i]);
748 memcpy((void *)CAC_BASE, tlb_handler, 0x80);
749 flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
753 * The R4000 TLB handler is much more complicated. We have two
754 * consecutive handler areas with 32 instructions space each.
755 * Since they aren't used at the same time, we can overflow in the
756 * other one.To keep things simple, we first assume linear space,
757 * then we relocate it to the final handler layout as needed.
759 static __initdata u32 final_handler[64];
764 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
765 * 2. A timing hazard exists for the TLBP instruction.
767 * stalling_instruction
770 * The JTLB is being read for the TLBP throughout the stall generated by the
771 * previous instruction. This is not really correct as the stalling instruction
772 * can modify the address used to access the JTLB. The failure symptom is that
773 * the TLBP instruction will use an address created for the stalling instruction
774 * and not the address held in C0_ENHI and thus report the wrong results.
776 * The software work-around is to not allow the instruction preceding the TLBP
777 * to stall - make it an NOP or some other instruction guaranteed not to stall.
779 * Errata 2 will not be fixed. This errata is also on the R5000.
781 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
783 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
785 switch (current_cpu_data.cputype) {
800 * Write random or indexed TLB entry, and care about the hazards from
801 * the preceeding mtc0 and for the following eret.
803 enum tlb_write_entry { tlb_random, tlb_indexed };
805 static __init void build_tlb_write_entry(u32 **p, struct label **l,
807 enum tlb_write_entry wmode)
809 void(*tlbw)(u32 **) = NULL;
812 case tlb_random: tlbw = i_tlbwr; break;
813 case tlb_indexed: tlbw = i_tlbwi; break;
816 switch (current_cpu_data.cputype) {
824 * This branch uses up a mtc0 hazard nop slot and saves
825 * two nops after the tlbw instruction.
827 il_bgezl(p, r, 0, label_tlbw_hazard);
829 l_tlbw_hazard(l, *p);
860 i_nop(p); /* QED specifies 2 nops hazard */
862 * This branch uses up a mtc0 hazard nop slot and saves
863 * a nop after the tlbw instruction.
865 il_bgezl(p, r, 0, label_tlbw_hazard);
867 l_tlbw_hazard(l, *p);
886 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
887 * use of the JTLB for instructions should not occur for 4
888 * cpu cycles and use for data translations should not occur
922 panic("No TLB refill handler yet (CPU type: %d)",
923 current_cpu_data.cputype);
930 * TMP and PTR are scratch.
931 * TMP will be clobbered, PTR will hold the pmd entry.
934 build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
935 unsigned int tmp, unsigned int ptr)
937 long pgdc = (long)pgd_current;
940 * The vmalloc handling is not in the hotpath.
942 i_dmfc0(p, tmp, C0_BADVADDR);
943 il_bltz(p, r, tmp, label_vmalloc);
944 /* No i_nop needed here, since the next insn doesn't touch TMP. */
948 * 64 bit SMP has the lower part of &pgd_current[smp_processor_id()]
951 if (in_compat_space_p(pgdc)) {
952 i_dmfc0(p, ptr, C0_CONTEXT);
953 i_dsra(p, ptr, ptr, 23);
954 i_ld(p, ptr, 0, ptr);
956 #ifdef CONFIG_BUILD_ELF64
957 i_dmfc0(p, ptr, C0_CONTEXT);
958 i_dsrl(p, ptr, ptr, 23);
959 i_dsll(p, ptr, ptr, 3);
960 i_LA_mostly(p, tmp, pgdc);
961 i_daddu(p, ptr, ptr, tmp);
962 i_dmfc0(p, tmp, C0_BADVADDR);
963 i_ld(p, ptr, rel_lo(pgdc), ptr);
965 i_dmfc0(p, ptr, C0_CONTEXT);
966 i_lui(p, tmp, rel_highest(pgdc));
967 i_dsll(p, ptr, ptr, 9);
968 i_daddiu(p, tmp, tmp, rel_higher(pgdc));
969 i_dsrl32(p, ptr, ptr, 0);
970 i_and(p, ptr, ptr, tmp);
971 i_dmfc0(p, tmp, C0_BADVADDR);
972 i_ld(p, ptr, 0, ptr);
976 i_LA_mostly(p, ptr, pgdc);
977 i_ld(p, ptr, rel_lo(pgdc), ptr);
980 l_vmalloc_done(l, *p);
981 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */
982 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
983 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
984 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
985 i_ld(p, ptr, 0, ptr); /* get pmd pointer */
986 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
987 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
988 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
992 * BVADDR is the faulting address, PTR is scratch.
993 * PTR will hold the pgd for vmalloc.
996 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
997 unsigned int bvaddr, unsigned int ptr)
999 long swpd = (long)swapper_pg_dir;
1002 i_LA(p, ptr, VMALLOC_START);
1003 i_dsubu(p, bvaddr, bvaddr, ptr);
1005 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
1006 il_b(p, r, label_vmalloc_done);
1007 i_lui(p, ptr, rel_hi(swpd));
1009 i_LA_mostly(p, ptr, swpd);
1010 il_b(p, r, label_vmalloc_done);
1011 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1015 #else /* !CONFIG_64BIT */
1018 * TMP and PTR are scratch.
1019 * TMP will be clobbered, PTR will hold the pgd entry.
1021 static __init void __attribute__((unused))
1022 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1024 long pgdc = (long)pgd_current;
1026 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1028 i_mfc0(p, ptr, C0_CONTEXT);
1029 i_LA_mostly(p, tmp, pgdc);
1030 i_srl(p, ptr, ptr, 23);
1031 i_sll(p, ptr, ptr, 2);
1032 i_addu(p, ptr, tmp, ptr);
1034 i_LA_mostly(p, ptr, pgdc);
1036 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1037 i_lw(p, ptr, rel_lo(pgdc), ptr);
1038 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1039 i_sll(p, tmp, tmp, PGD_T_LOG2);
1040 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1043 #endif /* !CONFIG_64BIT */
1045 static __init void build_adjust_context(u32 **p, unsigned int ctx)
1047 unsigned int shift = 4 - (PTE_T_LOG2 + 1);
1048 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1050 switch (current_cpu_data.cputype) {
1067 i_SRL(p, ctx, ctx, shift);
1068 i_andi(p, ctx, ctx, mask);
1071 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1074 * Bug workaround for the Nevada. It seems as if under certain
1075 * circumstances the move from cp0_context might produce a
1076 * bogus result when the mfc0 instruction and its consumer are
1077 * in a different cacheline or a load instruction, probably any
1078 * memory reference, is between them.
1080 switch (current_cpu_data.cputype) {
1082 i_LW(p, ptr, 0, ptr);
1083 GET_CONTEXT(p, tmp); /* get context reg */
1087 GET_CONTEXT(p, tmp); /* get context reg */
1088 i_LW(p, ptr, 0, ptr);
1092 build_adjust_context(p, tmp);
1093 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1096 static __init void build_update_entries(u32 **p, unsigned int tmp,
1100 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1101 * Kernel is a special case. Only a few CPUs use it.
1103 #ifdef CONFIG_64BIT_PHYS_ADDR
1104 if (cpu_has_64bits) {
1105 i_ld(p, tmp, 0, ptep); /* get even pte */
1106 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1107 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
1108 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1109 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
1110 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1112 int pte_off_even = sizeof(pte_t) / 2;
1113 int pte_off_odd = pte_off_even + sizeof(pte_t);
1115 /* The pte entries are pre-shifted */
1116 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1117 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1118 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1119 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1122 i_LW(p, tmp, 0, ptep); /* get even pte */
1123 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1124 if (r45k_bvahwbug())
1125 build_tlb_probe_entry(p);
1126 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
1127 if (r4k_250MHZhwbug())
1128 i_mtc0(p, 0, C0_ENTRYLO0);
1129 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1130 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
1131 if (r45k_bvahwbug())
1132 i_mfc0(p, tmp, C0_INDEX);
1133 if (r4k_250MHZhwbug())
1134 i_mtc0(p, 0, C0_ENTRYLO1);
1135 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1139 static void __init build_r4000_tlb_refill_handler(void)
1141 u32 *p = tlb_handler;
1142 struct label *l = labels;
1143 struct reloc *r = relocs;
1145 unsigned int final_len;
1147 memset(tlb_handler, 0, sizeof(tlb_handler));
1148 memset(labels, 0, sizeof(labels));
1149 memset(relocs, 0, sizeof(relocs));
1150 memset(final_handler, 0, sizeof(final_handler));
1153 * create the plain linear handler
1155 if (bcm1250_m3_war()) {
1156 i_MFC0(&p, K0, C0_BADVADDR);
1157 i_MFC0(&p, K1, C0_ENTRYHI);
1158 i_xor(&p, K0, K0, K1);
1159 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1160 il_bnez(&p, &r, K0, label_leave);
1161 /* No need for i_nop */
1165 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1167 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1170 build_get_ptep(&p, K0, K1);
1171 build_update_entries(&p, K0, K1);
1172 build_tlb_write_entry(&p, &l, &r, tlb_random);
1174 i_eret(&p); /* return from trap */
1177 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1181 * Overflow check: For the 64bit handler, we need at least one
1182 * free instruction slot for the wrap-around branch. In worst
1183 * case, if the intended insertion point is a delay slot, we
1184 * need three, with the the second nop'ed and the third being
1188 if ((p - tlb_handler) > 64)
1189 panic("TLB refill handler space exceeded");
1191 if (((p - tlb_handler) > 63)
1192 || (((p - tlb_handler) > 61)
1193 && insn_has_bdelay(relocs, tlb_handler + 29)))
1194 panic("TLB refill handler space exceeded");
1198 * Now fold the handler in the TLB refill handler space.
1202 /* Simplest case, just copy the handler. */
1203 copy_handler(relocs, labels, tlb_handler, p, f);
1204 final_len = p - tlb_handler;
1205 #else /* CONFIG_64BIT */
1206 f = final_handler + 32;
1207 if ((p - tlb_handler) <= 32) {
1208 /* Just copy the handler. */
1209 copy_handler(relocs, labels, tlb_handler, p, f);
1210 final_len = p - tlb_handler;
1212 u32 *split = tlb_handler + 30;
1215 * Find the split point.
1217 if (insn_has_bdelay(relocs, split - 1))
1220 /* Copy first part of the handler. */
1221 copy_handler(relocs, labels, tlb_handler, split, f);
1222 f += split - tlb_handler;
1224 /* Insert branch. */
1225 l_split(&l, final_handler);
1226 il_b(&f, &r, label_split);
1227 if (insn_has_bdelay(relocs, split))
1230 copy_handler(relocs, labels, split, split + 1, f);
1231 move_labels(labels, f, f + 1, -1);
1236 /* Copy the rest of the handler. */
1237 copy_handler(relocs, labels, split, p, final_handler);
1238 final_len = (f - (final_handler + 32)) + (p - split);
1240 #endif /* CONFIG_64BIT */
1242 resolve_relocs(relocs, labels);
1243 printk("Synthesized TLB refill handler (%u instructions).\n",
1250 for (i = 0; i < 64; i++)
1251 printk("%08x\n", final_handler[i]);
1255 memcpy((void *)CAC_BASE, final_handler, 0x100);
1256 flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
1260 * TLB load/store/modify handlers.
1262 * Only the fastpath gets synthesized at runtime, the slowpath for
1263 * do_page_fault remains normal asm.
1265 extern void tlb_do_page_fault_0(void);
1266 extern void tlb_do_page_fault_1(void);
1268 #define __tlb_handler_align \
1269 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1272 * 128 instructions for the fastpath handler is generous and should
1273 * never be exceeded.
1275 #define FASTPATH_SIZE 128
1277 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
1278 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1279 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1282 iPTE_LW(u32 **p, struct label **l, unsigned int pte, int offset,
1286 # ifdef CONFIG_64BIT_PHYS_ADDR
1288 i_lld(p, pte, offset, ptr);
1291 i_LL(p, pte, offset, ptr);
1293 # ifdef CONFIG_64BIT_PHYS_ADDR
1295 i_ld(p, pte, offset, ptr);
1298 i_LW(p, pte, offset, ptr);
1303 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, int offset,
1307 # ifdef CONFIG_64BIT_PHYS_ADDR
1309 i_scd(p, pte, offset, ptr);
1312 i_SC(p, pte, offset, ptr);
1314 if (r10000_llsc_war())
1315 il_beqzl(p, r, pte, label_smp_pgtable_change);
1317 il_beqz(p, r, pte, label_smp_pgtable_change);
1319 # ifdef CONFIG_64BIT_PHYS_ADDR
1320 if (!cpu_has_64bits) {
1321 /* no i_nop needed */
1322 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1323 i_ori(p, pte, pte, _PAGE_VALID);
1324 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1325 il_beqz(p, r, pte, label_smp_pgtable_change);
1326 /* no i_nop needed */
1327 i_lw(p, pte, 0, ptr);
1334 # ifdef CONFIG_64BIT_PHYS_ADDR
1336 i_sd(p, pte, offset, ptr);
1339 i_SW(p, pte, offset, ptr);
1341 # ifdef CONFIG_64BIT_PHYS_ADDR
1342 if (!cpu_has_64bits) {
1343 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1344 i_ori(p, pte, pte, _PAGE_VALID);
1345 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1346 i_lw(p, pte, 0, ptr);
1353 * Check if PTE is present, if not then jump to LABEL. PTR points to
1354 * the page table where this PTE is located, PTE will be re-loaded
1355 * with it's original value.
1358 build_pte_present(u32 **p, struct label **l, struct reloc **r,
1359 unsigned int pte, unsigned int ptr, enum label_id lid)
1361 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1362 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1363 il_bnez(p, r, pte, lid);
1364 iPTE_LW(p, l, pte, 0, ptr);
1367 /* Make PTE valid, store result in PTR. */
1369 build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1372 i_ori(p, pte, pte, _PAGE_VALID | _PAGE_ACCESSED);
1373 iPTE_SW(p, r, pte, 0, ptr);
1377 * Check if PTE can be written to, if not branch to LABEL. Regardless
1378 * restore PTE with value from PTR when done.
1381 build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1382 unsigned int pte, unsigned int ptr, enum label_id lid)
1384 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1385 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1386 il_bnez(p, r, pte, lid);
1387 iPTE_LW(p, l, pte, 0, ptr);
1390 /* Make PTE writable, update software status bits as well, then store
1394 build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1398 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1399 iPTE_SW(p, r, pte, 0, ptr);
1403 * Check if PTE can be modified, if not branch to LABEL. Regardless
1404 * restore PTE with value from PTR when done.
1407 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1408 unsigned int pte, unsigned int ptr, enum label_id lid)
1410 i_andi(p, pte, pte, _PAGE_WRITE);
1411 il_beqz(p, r, pte, lid);
1412 iPTE_LW(p, l, pte, 0, ptr);
1416 * R3000 style TLB load/store/modify handlers.
1419 /* This places the pte in the page table at PTR into ENTRYLO0. */
1421 build_r3000_pte_reload(u32 **p, unsigned int ptr)
1423 i_lw(p, ptr, 0, ptr);
1424 i_nop(p); /* load delay */
1425 i_mtc0(p, ptr, C0_ENTRYLO0);
1426 i_nop(p); /* cp0 delay */
1430 * The index register may have the probe fail bit set,
1431 * because we would trap on access kseg2, i.e. without refill.
1434 build_r3000_tlb_write(u32 **p, struct label **l, struct reloc **r,
1437 i_mfc0(p, tmp, C0_INDEX);
1438 i_nop(p); /* cp0 delay */
1439 il_bltz(p, r, tmp, label_r3000_write_probe_fail);
1440 i_nop(p); /* branch delay */
1442 il_b(p, r, label_r3000_write_probe_ok);
1443 i_nop(p); /* branch delay */
1444 l_r3000_write_probe_fail(l, *p);
1446 l_r3000_write_probe_ok(l, *p);
1450 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1453 long pgdc = (long)pgd_current;
1455 i_mfc0(p, pte, C0_BADVADDR);
1456 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */
1457 i_lw(p, ptr, rel_lo(pgdc), ptr);
1458 i_srl(p, pte, pte, 22); /* load delay */
1459 i_sll(p, pte, pte, 2);
1460 i_addu(p, ptr, ptr, pte);
1461 i_mfc0(p, pte, C0_CONTEXT);
1462 i_lw(p, ptr, 0, ptr); /* cp0 delay */
1463 i_andi(p, pte, pte, 0xffc); /* load delay */
1464 i_addu(p, ptr, ptr, pte);
1465 i_lw(p, pte, 0, ptr);
1466 i_nop(p); /* load delay */
1471 build_r3000_tlbchange_handler_tail(u32 **p, unsigned int tmp)
1473 i_mfc0(p, tmp, C0_EPC);
1474 i_nop(p); /* cp0 delay */
1476 i_rfe(p); /* branch delay */
1479 static void __init build_r3000_tlb_load_handler(void)
1481 u32 *p = handle_tlbl;
1482 struct label *l = labels;
1483 struct reloc *r = relocs;
1485 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1486 memset(labels, 0, sizeof(labels));
1487 memset(relocs, 0, sizeof(relocs));
1489 build_r3000_tlbchange_handler_head(&p, K0, K1);
1490 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1491 build_make_valid(&p, &r, K0, K1);
1492 build_r3000_pte_reload(&p, K1);
1493 build_r3000_tlb_write(&p, &l, &r, K0);
1494 build_r3000_tlbchange_handler_tail(&p, K0);
1496 l_nopage_tlbl(&l, p);
1497 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1500 if ((p - handle_tlbl) > FASTPATH_SIZE)
1501 panic("TLB load handler fastpath space exceeded");
1503 resolve_relocs(relocs, labels);
1504 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1505 (unsigned int)(p - handle_tlbl));
1511 for (i = 0; i < FASTPATH_SIZE; i++)
1512 printk("%08x\n", handle_tlbl[i]);
1516 flush_icache_range((unsigned long)handle_tlbl,
1517 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1520 static void __init build_r3000_tlb_store_handler(void)
1522 u32 *p = handle_tlbs;
1523 struct label *l = labels;
1524 struct reloc *r = relocs;
1526 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1527 memset(labels, 0, sizeof(labels));
1528 memset(relocs, 0, sizeof(relocs));
1530 build_r3000_tlbchange_handler_head(&p, K0, K1);
1531 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1532 build_make_write(&p, &r, K0, K1);
1533 build_r3000_pte_reload(&p, K1);
1534 build_r3000_tlb_write(&p, &l, &r, K0);
1535 build_r3000_tlbchange_handler_tail(&p, K0);
1537 l_nopage_tlbs(&l, p);
1538 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1541 if ((p - handle_tlbs) > FASTPATH_SIZE)
1542 panic("TLB store handler fastpath space exceeded");
1544 resolve_relocs(relocs, labels);
1545 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1546 (unsigned int)(p - handle_tlbs));
1552 for (i = 0; i < FASTPATH_SIZE; i++)
1553 printk("%08x\n", handle_tlbs[i]);
1557 flush_icache_range((unsigned long)handle_tlbs,
1558 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1561 static void __init build_r3000_tlb_modify_handler(void)
1563 u32 *p = handle_tlbm;
1564 struct label *l = labels;
1565 struct reloc *r = relocs;
1567 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1568 memset(labels, 0, sizeof(labels));
1569 memset(relocs, 0, sizeof(relocs));
1571 build_r3000_tlbchange_handler_head(&p, K0, K1);
1572 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1573 build_make_write(&p, &r, K0, K1);
1574 build_r3000_pte_reload(&p, K1);
1576 build_r3000_tlbchange_handler_tail(&p, K0);
1578 l_nopage_tlbm(&l, p);
1579 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1582 if ((p - handle_tlbm) > FASTPATH_SIZE)
1583 panic("TLB modify handler fastpath space exceeded");
1585 resolve_relocs(relocs, labels);
1586 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1587 (unsigned int)(p - handle_tlbm));
1593 for (i = 0; i < FASTPATH_SIZE; i++)
1594 printk("%08x\n", handle_tlbm[i]);
1598 flush_icache_range((unsigned long)handle_tlbm,
1599 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1603 * R4000 style TLB load/store/modify handlers.
1606 build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1607 struct reloc **r, unsigned int pte,
1611 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1613 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1616 i_MFC0(p, pte, C0_BADVADDR);
1617 i_LW(p, ptr, 0, ptr);
1618 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1619 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1620 i_ADDU(p, ptr, ptr, pte);
1623 l_smp_pgtable_change(l, *p);
1625 iPTE_LW(p, l, pte, 0, ptr); /* get even pte */
1626 build_tlb_probe_entry(p);
1630 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1631 struct reloc **r, unsigned int tmp,
1634 i_ori(p, ptr, ptr, sizeof(pte_t));
1635 i_xori(p, ptr, ptr, sizeof(pte_t));
1636 build_update_entries(p, tmp, ptr);
1637 build_tlb_write_entry(p, l, r, tlb_indexed);
1639 i_eret(p); /* return from trap */
1642 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1646 static void __init build_r4000_tlb_load_handler(void)
1648 u32 *p = handle_tlbl;
1649 struct label *l = labels;
1650 struct reloc *r = relocs;
1652 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1653 memset(labels, 0, sizeof(labels));
1654 memset(relocs, 0, sizeof(relocs));
1656 if (bcm1250_m3_war()) {
1657 i_MFC0(&p, K0, C0_BADVADDR);
1658 i_MFC0(&p, K1, C0_ENTRYHI);
1659 i_xor(&p, K0, K0, K1);
1660 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1661 il_bnez(&p, &r, K0, label_leave);
1662 /* No need for i_nop */
1665 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1666 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1667 build_make_valid(&p, &r, K0, K1);
1668 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1670 l_nopage_tlbl(&l, p);
1671 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1674 if ((p - handle_tlbl) > FASTPATH_SIZE)
1675 panic("TLB load handler fastpath space exceeded");
1677 resolve_relocs(relocs, labels);
1678 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1679 (unsigned int)(p - handle_tlbl));
1685 for (i = 0; i < FASTPATH_SIZE; i++)
1686 printk("%08x\n", handle_tlbl[i]);
1690 flush_icache_range((unsigned long)handle_tlbl,
1691 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1694 static void __init build_r4000_tlb_store_handler(void)
1696 u32 *p = handle_tlbs;
1697 struct label *l = labels;
1698 struct reloc *r = relocs;
1700 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1701 memset(labels, 0, sizeof(labels));
1702 memset(relocs, 0, sizeof(relocs));
1704 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1705 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1706 build_make_write(&p, &r, K0, K1);
1707 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1709 l_nopage_tlbs(&l, p);
1710 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1713 if ((p - handle_tlbs) > FASTPATH_SIZE)
1714 panic("TLB store handler fastpath space exceeded");
1716 resolve_relocs(relocs, labels);
1717 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1718 (unsigned int)(p - handle_tlbs));
1724 for (i = 0; i < FASTPATH_SIZE; i++)
1725 printk("%08x\n", handle_tlbs[i]);
1729 flush_icache_range((unsigned long)handle_tlbs,
1730 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1733 static void __init build_r4000_tlb_modify_handler(void)
1735 u32 *p = handle_tlbm;
1736 struct label *l = labels;
1737 struct reloc *r = relocs;
1739 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1740 memset(labels, 0, sizeof(labels));
1741 memset(relocs, 0, sizeof(relocs));
1743 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1744 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1745 /* Present and writable bits set, set accessed and dirty bits. */
1746 build_make_write(&p, &r, K0, K1);
1747 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1749 l_nopage_tlbm(&l, p);
1750 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1753 if ((p - handle_tlbm) > FASTPATH_SIZE)
1754 panic("TLB modify handler fastpath space exceeded");
1756 resolve_relocs(relocs, labels);
1757 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1758 (unsigned int)(p - handle_tlbm));
1764 for (i = 0; i < FASTPATH_SIZE; i++)
1765 printk("%08x\n", handle_tlbm[i]);
1769 flush_icache_range((unsigned long)handle_tlbm,
1770 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1773 void __init build_tlb_refill_handler(void)
1776 * The refill handler is generated per-CPU, multi-node systems
1777 * may have local storage for it. The other handlers are only
1780 static int run_once = 0;
1782 switch (current_cpu_data.cputype) {
1790 build_r3000_tlb_refill_handler();
1792 build_r3000_tlb_load_handler();
1793 build_r3000_tlb_store_handler();
1794 build_r3000_tlb_modify_handler();
1801 panic("No R6000 TLB refill handler yet");
1805 panic("No R8000 TLB refill handler yet");
1809 build_r4000_tlb_refill_handler();
1811 build_r4000_tlb_load_handler();
1812 build_r4000_tlb_store_handler();
1813 build_r4000_tlb_modify_handler();