2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/config.h>
6 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/capability.h>
12 #include <linux/sched.h>
13 #include <linux/errno.h>
14 #include <linux/bootmem.h>
16 #include <asm/processor.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base = 0;
35 unsigned long isa_mem_base = 0;
36 unsigned long pci_dram_offset = 0;
37 int pcibios_assign_bus_offset = 1;
39 void pcibios_make_OF_bus_map(void);
41 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
42 static int probe_resource(struct pci_bus *parent, struct resource *pr,
43 struct resource *res, struct resource **conflict);
44 static void update_bridge_base(struct pci_bus *bus, int i);
45 static void pcibios_fixup_resources(struct pci_dev* dev);
46 static void fixup_broken_pcnet32(struct pci_dev* dev);
47 static int reparent_resources(struct resource *parent, struct resource *res);
48 static void fixup_cpc710_pci64(struct pci_dev* dev);
50 static u8* pci_to_OF_bus_map;
53 /* By default, we don't re-assign bus numbers. We do this only on
56 int pci_assign_all_buses;
58 struct pci_controller* hose_head;
59 struct pci_controller** hose_tail = &hose_head;
61 static int pci_bus_count;
64 fixup_broken_pcnet32(struct pci_dev* dev)
66 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
67 dev->vendor = PCI_VENDOR_ID_AMD;
68 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
71 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
74 fixup_cpc710_pci64(struct pci_dev* dev)
76 /* Hide the PCI64 BARs from the kernel as their content doesn't
77 * fit well in the resource management
79 dev->resource[0].start = dev->resource[0].end = 0;
80 dev->resource[0].flags = 0;
81 dev->resource[1].start = dev->resource[1].end = 0;
82 dev->resource[1].flags = 0;
84 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
87 pcibios_fixup_resources(struct pci_dev *dev)
89 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
94 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
97 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
98 struct resource *res = dev->resource + i;
101 if (res->end == 0xffffffff) {
102 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
103 pci_name(dev), i, res->start, res->end);
104 res->end -= res->start;
106 res->flags |= IORESOURCE_UNSET;
110 if (res->flags & IORESOURCE_MEM) {
111 offset = hose->pci_mem_offset;
112 } else if (res->flags & IORESOURCE_IO) {
113 offset = (unsigned long) hose->io_base_virt
117 res->start += offset;
120 printk("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
121 i, res->flags, pci_name(dev),
122 res->start - offset, res->start);
127 /* Call machine specific resource fixup */
128 if (ppc_md.pcibios_fixup_resources)
129 ppc_md.pcibios_fixup_resources(dev);
131 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
133 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
134 struct resource *res)
136 unsigned long offset = 0;
137 struct pci_controller *hose = dev->sysdata;
139 if (hose && res->flags & IORESOURCE_IO)
140 offset = (unsigned long)hose->io_base_virt - isa_io_base;
141 else if (hose && res->flags & IORESOURCE_MEM)
142 offset = hose->pci_mem_offset;
143 region->start = res->start - offset;
144 region->end = res->end - offset;
146 EXPORT_SYMBOL(pcibios_resource_to_bus);
148 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
149 struct pci_bus_region *region)
151 unsigned long offset = 0;
152 struct pci_controller *hose = dev->sysdata;
154 if (hose && res->flags & IORESOURCE_IO)
155 offset = (unsigned long)hose->io_base_virt - isa_io_base;
156 else if (hose && res->flags & IORESOURCE_MEM)
157 offset = hose->pci_mem_offset;
158 res->start = region->start + offset;
159 res->end = region->end + offset;
161 EXPORT_SYMBOL(pcibios_bus_to_resource);
164 * We need to avoid collisions with `mirrored' VGA ports
165 * and other strange ISA hardware, so we always want the
166 * addresses to be allocated in the 0x000-0x0ff region
169 * Why? Because some silly external IO cards only decode
170 * the low 10 bits of the IO address. The 0x00-0xff region
171 * is reserved for motherboard devices that decode all 16
172 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
173 * but we want to try to avoid allocating at 0x2900-0x2bff
174 * which might have be mirrored at 0x0100-0x03ff..
176 void pcibios_align_resource(void *data, struct resource *res,
177 resource_size_t size, resource_size_t align)
179 struct pci_dev *dev = data;
181 if (res->flags & IORESOURCE_IO) {
182 resource_size_t start = res->start;
185 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
186 " (%lld bytes)\n", pci_name(dev),
187 dev->resource - res, (unsigned long long)size);
191 start = (start + 0x3ff) & ~0x3ff;
196 EXPORT_SYMBOL(pcibios_align_resource);
199 * Handle resources of PCI devices. If the world were perfect, we could
200 * just allocate all the resource regions and do nothing more. It isn't.
201 * On the other hand, we cannot just re-allocate all devices, as it would
202 * require us to know lots of host bridge internals. So we attempt to
203 * keep as much of the original configuration as possible, but tweak it
204 * when it's found to be wrong.
206 * Known BIOS problems we have to work around:
207 * - I/O or memory regions not configured
208 * - regions configured, but not enabled in the command register
209 * - bogus I/O addresses above 64K used
210 * - expansion ROMs left enabled (this may sound harmless, but given
211 * the fact the PCI specs explicitly allow address decoders to be
212 * shared between expansion ROMs and other resource regions, it's
213 * at least dangerous)
216 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
217 * This gives us fixed barriers on where we can allocate.
218 * (2) Allocate resources for all enabled devices. If there is
219 * a collision, just mark the resource as unallocated. Also
220 * disable expansion ROMs during this step.
221 * (3) Try to allocate resources for disabled devices. If the
222 * resources were assigned correctly, everything goes well,
223 * if they weren't, they won't disturb allocation of other
225 * (4) Assign new addresses to resources which were either
226 * not configured at all or misconfigured. If explicitly
227 * requested by the user, configure expansion ROM address
232 pcibios_allocate_bus_resources(struct list_head *bus_list)
236 struct resource *res, *pr;
238 /* Depth-First Search on bus tree */
239 list_for_each_entry(bus, bus_list, node) {
240 for (i = 0; i < 4; ++i) {
241 if ((res = bus->resource[i]) == NULL || !res->flags
242 || res->start > res->end)
244 if (bus->parent == NULL)
245 pr = (res->flags & IORESOURCE_IO)?
246 &ioport_resource: &iomem_resource;
248 pr = pci_find_parent_resource(bus->self, res);
250 /* this happens when the generic PCI
251 * code (wrongly) decides that this
252 * bridge is transparent -- paulus
258 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
259 res->start, res->end, res->flags, pr);
261 if (request_resource(pr, res) == 0)
264 * Must be a conflict with an existing entry.
265 * Move that entry (or entries) under the
266 * bridge resource and try again.
268 if (reparent_resources(pr, res) == 0)
271 printk(KERN_ERR "PCI: Cannot allocate resource region "
272 "%d of PCI bridge %d\n", i, bus->number);
273 if (pci_relocate_bridge_resource(bus, i))
274 bus->resource[i] = NULL;
276 pcibios_allocate_bus_resources(&bus->children);
281 * Reparent resource children of pr that conflict with res
282 * under res, and make res replace those children.
285 reparent_resources(struct resource *parent, struct resource *res)
287 struct resource *p, **pp;
288 struct resource **firstpp = NULL;
290 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
291 if (p->end < res->start)
293 if (res->end < p->start)
295 if (p->start < res->start || p->end > res->end)
296 return -1; /* not completely contained */
301 return -1; /* didn't find any conflicting entries? */
302 res->parent = parent;
303 res->child = *firstpp;
307 for (p = res->child; p != NULL; p = p->sibling) {
309 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
310 p->name, p->start, p->end, res->name);
316 * A bridge has been allocated a range which is outside the range
317 * of its parent bridge, so it needs to be moved.
320 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
322 struct resource *res, *pr, *conflict;
323 unsigned long try, size;
325 struct pci_bus *parent = bus->parent;
327 if (parent == NULL) {
328 /* shouldn't ever happen */
329 printk(KERN_ERR "PCI: can't move host bridge resource\n");
332 res = bus->resource[i];
336 for (j = 0; j < 4; j++) {
337 struct resource *r = parent->resource[j];
340 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
342 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
346 if (res->flags & IORESOURCE_PREFETCH)
351 size = res->end - res->start;
352 if (pr->start > pr->end || size > pr->end - pr->start)
356 res->start = try - size;
358 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
360 if (conflict->start <= pr->start + size)
362 try = conflict->start - 1;
364 if (request_resource(pr, res)) {
365 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
366 res->start, res->end);
367 return -1; /* "can't happen" */
369 update_bridge_base(bus, i);
370 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
371 bus->number, i, (unsigned long long)res->start,
372 (unsigned long long)res->end);
377 probe_resource(struct pci_bus *parent, struct resource *pr,
378 struct resource *res, struct resource **conflict)
385 for (r = pr->child; r != NULL; r = r->sibling) {
386 if (r->end >= res->start && res->end >= r->start) {
391 list_for_each_entry(bus, &parent->children, node) {
392 for (i = 0; i < 4; ++i) {
393 if ((r = bus->resource[i]) == NULL)
395 if (!r->flags || r->start > r->end || r == res)
397 if (pci_find_parent_resource(bus->self, r) != pr)
399 if (r->end >= res->start && res->end >= r->start) {
405 list_for_each_entry(dev, &parent->devices, bus_list) {
406 for (i = 0; i < 6; ++i) {
407 r = &dev->resource[i];
408 if (!r->flags || (r->flags & IORESOURCE_UNSET))
410 if (pci_find_parent_resource(dev, r) != pr)
412 if (r->end >= res->start && res->end >= r->start) {
422 update_bridge_base(struct pci_bus *bus, int i)
424 struct resource *res = bus->resource[i];
425 u8 io_base_lo, io_limit_lo;
426 u16 mem_base, mem_limit;
428 unsigned long start, end, off;
429 struct pci_dev *dev = bus->self;
430 struct pci_controller *hose = dev->sysdata;
433 printk("update_bridge_base: no hose?\n");
436 pci_read_config_word(dev, PCI_COMMAND, &cmd);
437 pci_write_config_word(dev, PCI_COMMAND,
438 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
439 if (res->flags & IORESOURCE_IO) {
440 off = (unsigned long) hose->io_base_virt - isa_io_base;
441 start = res->start - off;
442 end = res->end - off;
443 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
444 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
446 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
448 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
450 io_base_lo |= PCI_IO_RANGE_TYPE_32;
452 io_base_lo |= PCI_IO_RANGE_TYPE_16;
453 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
454 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
456 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
458 off = hose->pci_mem_offset;
459 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
460 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
461 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
462 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
464 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
465 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
466 off = hose->pci_mem_offset;
467 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
468 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
469 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
470 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
473 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
474 pci_name(dev), i, res->flags);
476 pci_write_config_word(dev, PCI_COMMAND, cmd);
479 static inline void alloc_resource(struct pci_dev *dev, int idx)
481 struct resource *pr, *r = &dev->resource[idx];
483 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
484 pci_name(dev), idx, r->start, r->end, r->flags);
485 pr = pci_find_parent_resource(dev, r);
486 if (!pr || request_resource(pr, r) < 0) {
487 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
488 " of device %s\n", idx, pci_name(dev));
490 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
491 pr, pr->start, pr->end, pr->flags);
492 /* We'll assign a new address later */
493 r->flags |= IORESOURCE_UNSET;
500 pcibios_allocate_resources(int pass)
502 struct pci_dev *dev = NULL;
507 for_each_pci_dev(dev) {
508 pci_read_config_word(dev, PCI_COMMAND, &command);
509 for (idx = 0; idx < 6; idx++) {
510 r = &dev->resource[idx];
511 if (r->parent) /* Already allocated */
513 if (!r->flags || (r->flags & IORESOURCE_UNSET))
514 continue; /* Not assigned at all */
515 if (r->flags & IORESOURCE_IO)
516 disabled = !(command & PCI_COMMAND_IO);
518 disabled = !(command & PCI_COMMAND_MEMORY);
519 if (pass == disabled)
520 alloc_resource(dev, idx);
524 r = &dev->resource[PCI_ROM_RESOURCE];
525 if (r->flags & IORESOURCE_ROM_ENABLE) {
526 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
528 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
529 r->flags &= ~IORESOURCE_ROM_ENABLE;
530 pci_read_config_dword(dev, dev->rom_base_reg, ®);
531 pci_write_config_dword(dev, dev->rom_base_reg,
532 reg & ~PCI_ROM_ADDRESS_ENABLE);
538 pcibios_assign_resources(void)
540 struct pci_dev *dev = NULL;
544 for_each_pci_dev(dev) {
545 int class = dev->class >> 8;
547 /* Don't touch classless devices and host bridges */
548 if (!class || class == PCI_CLASS_BRIDGE_HOST)
551 for (idx = 0; idx < 6; idx++) {
552 r = &dev->resource[idx];
555 * We shall assign a new address to this resource,
556 * either because the BIOS (sic) forgot to do so
557 * or because we have decided the old address was
558 * unusable for some reason.
560 if ((r->flags & IORESOURCE_UNSET) && r->end &&
561 (!ppc_md.pcibios_enable_device_hook ||
562 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
563 r->flags &= ~IORESOURCE_UNSET;
564 pci_assign_resource(dev, idx);
568 #if 0 /* don't assign ROMs */
569 r = &dev->resource[PCI_ROM_RESOURCE];
573 pci_assign_resource(dev, PCI_ROM_RESOURCE);
580 pcibios_enable_resources(struct pci_dev *dev, int mask)
586 pci_read_config_word(dev, PCI_COMMAND, &cmd);
588 for (idx=0; idx<6; idx++) {
589 /* Only set up the requested stuff */
590 if (!(mask & (1<<idx)))
593 r = &dev->resource[idx];
594 if (r->flags & IORESOURCE_UNSET) {
595 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
598 if (r->flags & IORESOURCE_IO)
599 cmd |= PCI_COMMAND_IO;
600 if (r->flags & IORESOURCE_MEM)
601 cmd |= PCI_COMMAND_MEMORY;
603 if (dev->resource[PCI_ROM_RESOURCE].start)
604 cmd |= PCI_COMMAND_MEMORY;
605 if (cmd != old_cmd) {
606 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
607 pci_write_config_word(dev, PCI_COMMAND, cmd);
612 static int next_controller_index;
614 struct pci_controller * __init
615 pcibios_alloc_controller(void)
617 struct pci_controller *hose;
619 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
620 memset(hose, 0, sizeof(struct pci_controller));
623 hose_tail = &hose->next;
625 hose->index = next_controller_index++;
632 * Functions below are used on OpenFirmware machines.
635 make_one_node_map(struct device_node* node, u8 pci_bus)
640 if (pci_bus >= pci_bus_count)
642 bus_range = (int *) get_property(node, "bus-range", &len);
643 if (bus_range == NULL || len < 2 * sizeof(int)) {
644 printk(KERN_WARNING "Can't get bus-range for %s, "
645 "assuming it starts at 0\n", node->full_name);
646 pci_to_OF_bus_map[pci_bus] = 0;
648 pci_to_OF_bus_map[pci_bus] = bus_range[0];
650 for (node=node->child; node != 0;node = node->sibling) {
652 unsigned int *class_code, *reg;
654 class_code = (unsigned int *) get_property(node, "class-code", NULL);
655 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
656 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
658 reg = (unsigned int *)get_property(node, "reg", NULL);
661 dev = pci_find_slot(pci_bus, ((reg[0] >> 8) & 0xff));
662 if (!dev || !dev->subordinate)
664 make_one_node_map(node, dev->subordinate->number);
669 pcibios_make_OF_bus_map(void)
672 struct pci_controller* hose;
675 pci_to_OF_bus_map = (u8*)kmalloc(pci_bus_count, GFP_KERNEL);
676 if (!pci_to_OF_bus_map) {
677 printk(KERN_ERR "Can't allocate OF bus map !\n");
681 /* We fill the bus map with invalid values, that helps
684 for (i=0; i<pci_bus_count; i++)
685 pci_to_OF_bus_map[i] = 0xff;
687 /* For each hose, we begin searching bridges */
688 for(hose=hose_head; hose; hose=hose->next) {
689 struct device_node* node;
690 node = (struct device_node *)hose->arch_data;
693 make_one_node_map(node, hose->first_busno);
695 of_prop_map = get_property(find_path_device("/"), "pci-OF-bus-map", NULL);
697 memcpy(of_prop_map, pci_to_OF_bus_map, pci_bus_count);
699 printk("PCI->OF bus map:\n");
700 for (i=0; i<pci_bus_count; i++) {
701 if (pci_to_OF_bus_map[i] == 0xff)
703 printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
708 typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data);
710 static struct device_node*
711 scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data)
713 struct device_node* sub_node;
715 for (; node != 0;node = node->sibling) {
716 unsigned int *class_code;
718 if (filter(node, data))
721 /* For PCI<->PCI bridges or CardBus bridges, we go down
722 * Note: some OFs create a parent node "multifunc-device" as
723 * a fake root for all functions of a multi-function device,
724 * we go down them as well.
726 class_code = (unsigned int *) get_property(node, "class-code", NULL);
727 if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
728 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) &&
729 strcmp(node->name, "multifunc-device"))
731 sub_node = scan_OF_pci_childs(node->child, filter, data);
739 scan_OF_pci_childs_iterator(struct device_node* node, void* data)
742 u8* fdata = (u8*)data;
744 reg = (unsigned int *) get_property(node, "reg", NULL);
745 if (reg && ((reg[0] >> 8) & 0xff) == fdata[1]
746 && ((reg[0] >> 16) & 0xff) == fdata[0])
751 static struct device_node*
752 scan_OF_childs_for_device(struct device_node* node, u8 bus, u8 dev_fn)
754 u8 filter_data[2] = {bus, dev_fn};
756 return scan_OF_pci_childs(node, scan_OF_pci_childs_iterator, filter_data);
760 * Scans the OF tree for a device node matching a PCI device
763 pci_busdev_to_OF_node(struct pci_bus *bus, int devfn)
765 struct pci_controller *hose;
766 struct device_node *node;
772 /* Lookup the hose */
774 hose = pci_bus_to_hose(busnr);
778 /* Check it has an OF node associated */
779 node = (struct device_node *) hose->arch_data;
783 /* Fixup bus number according to what OF think it is. */
784 #ifdef CONFIG_PPC_PMAC
785 /* The G5 need a special case here. Basically, we don't remap all
786 * busses on it so we don't create the pci-OF-map. However, we do
787 * remap the AGP bus and so have to deal with it. A future better
788 * fix has to be done by making the remapping per-host and always
789 * filling the pci_to_OF map. --BenH
791 if (machine_is(powermac) && busnr >= 0xf0)
795 if (pci_to_OF_bus_map)
796 busnr = pci_to_OF_bus_map[busnr];
800 /* Now, lookup childs of the hose */
801 return scan_OF_childs_for_device(node->child, busnr, devfn);
803 EXPORT_SYMBOL(pci_busdev_to_OF_node);
806 pci_device_to_OF_node(struct pci_dev *dev)
808 return pci_busdev_to_OF_node(dev->bus, dev->devfn);
810 EXPORT_SYMBOL(pci_device_to_OF_node);
812 /* This routine is meant to be used early during boot, when the
813 * PCI bus numbers have not yet been assigned, and you need to
814 * issue PCI config cycles to an OF device.
815 * It could also be used to "fix" RTAS config cycles if you want
816 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
819 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
824 struct pci_controller* hose;
825 for (hose=hose_head;hose;hose=hose->next)
826 if (hose->arch_data == node)
834 find_OF_pci_device_filter(struct device_node* node, void* data)
836 return ((void *)node == data);
840 * Returns the PCI device matching a given OF node
843 pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
846 struct pci_controller* hose;
847 struct pci_dev* dev = NULL;
851 /* Make sure it's really a PCI device */
852 hose = pci_find_hose_for_OF_device(node);
853 if (!hose || !hose->arch_data)
855 if (!scan_OF_pci_childs(((struct device_node*)hose->arch_data)->child,
856 find_OF_pci_device_filter, (void *)node))
858 reg = (unsigned int *) get_property(node, "reg", NULL);
861 *bus = (reg[0] >> 16) & 0xff;
862 *devfn = ((reg[0] >> 8) & 0xff);
864 /* Ok, here we need some tweak. If we have already renumbered
865 * all busses, we can't rely on the OF bus number any more.
866 * the pci_to_OF_bus_map is not enough as several PCI busses
867 * may match the same OF bus number.
869 if (!pci_to_OF_bus_map)
872 for_each_pci_dev(dev)
873 if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
874 dev->devfn == *devfn) {
875 *bus = dev->bus->number;
882 EXPORT_SYMBOL(pci_device_from_OF_node);
885 pci_process_bridge_OF_ranges(struct pci_controller *hose,
886 struct device_node *dev, int primary)
888 static unsigned int static_lc_ranges[256] __initdata;
889 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
891 int rlen = 0, orig_rlen;
893 struct resource *res;
894 int np, na = prom_n_addr_cells(dev);
897 /* First we try to merge ranges to fix a problem with some pmacs
898 * that can have more than 3 ranges, fortunately using contiguous
901 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
904 /* Sanity check, though hopefully that never happens */
905 if (rlen > sizeof(static_lc_ranges)) {
906 printk(KERN_WARNING "OF ranges property too large !\n");
907 rlen = sizeof(static_lc_ranges);
909 lc_ranges = static_lc_ranges;
910 memcpy(lc_ranges, dt_ranges, rlen);
913 /* Let's work on a copy of the "ranges" property instead of damaging
914 * the device-tree image in memory
918 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
920 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
921 (prev[2] + prev[na+4]) == ranges[2] &&
922 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
923 prev[na+4] += ranges[na+4];
934 * The ranges property is laid out as an array of elements,
935 * each of which comprises:
936 * cells 0 - 2: a PCI address
937 * cells 3 or 3+4: a CPU physical address
938 * (size depending on dev->n_addr_cells)
939 * cells 4+5 or 5+6: the size of the range
943 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
946 switch ((ranges[0] >> 24) & 0x3) {
947 case 1: /* I/O space */
950 hose->io_base_phys = ranges[na+2];
951 /* limit I/O space to 16MB */
952 if (size > 0x01000000)
954 hose->io_base_virt = ioremap(ranges[na+2], size);
956 isa_io_base = (unsigned long) hose->io_base_virt;
957 res = &hose->io_resource;
958 res->flags = IORESOURCE_IO;
959 res->start = ranges[2];
960 DBG("PCI: IO 0x%llx -> 0x%llx\n",
961 res->start, res->start + size - 1);
963 case 2: /* memory space */
965 if (ranges[1] == 0 && ranges[2] == 0
966 && ranges[na+4] <= (16 << 20)) {
967 /* 1st 16MB, i.e. ISA memory area */
969 isa_mem_base = ranges[na+2];
972 while (memno < 3 && hose->mem_resources[memno].flags)
975 hose->pci_mem_offset = ranges[na+2] - ranges[2];
977 res = &hose->mem_resources[memno];
978 res->flags = IORESOURCE_MEM;
979 if(ranges[0] & 0x40000000)
980 res->flags |= IORESOURCE_PREFETCH;
981 res->start = ranges[na+2];
982 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
983 res->start, res->start + size - 1);
988 res->name = dev->full_name;
989 res->end = res->start + size - 1;
998 /* We create the "pci-OF-bus-map" property now so it appears in the
1002 pci_create_OF_bus_map(void)
1004 struct property* of_prop;
1006 of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256);
1007 if (of_prop && find_path_device("/")) {
1008 memset(of_prop, -1, sizeof(struct property) + 256);
1009 of_prop->name = "pci-OF-bus-map";
1010 of_prop->length = 256;
1011 of_prop->value = (unsigned char *)&of_prop[1];
1012 prom_add_property(find_path_device("/"), of_prop);
1016 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1018 struct pci_dev *pdev;
1019 struct device_node *np;
1021 pdev = to_pci_dev (dev);
1022 np = pci_device_to_OF_node(pdev);
1023 if (np == NULL || np->full_name == NULL)
1025 return sprintf(buf, "%s", np->full_name);
1027 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1029 #else /* CONFIG_PPC_OF */
1030 void pcibios_make_OF_bus_map(void)
1033 #endif /* CONFIG_PPC_OF */
1035 /* Add sysfs properties */
1036 void pcibios_add_platform_entries(struct pci_dev *pdev)
1038 #ifdef CONFIG_PPC_OF
1039 device_create_file(&pdev->dev, &dev_attr_devspec);
1040 #endif /* CONFIG_PPC_OF */
1044 #ifdef CONFIG_PPC_PMAC
1046 * This set of routines checks for PCI<->PCI bridges that have closed
1047 * IO resources and have child devices. It tries to re-open an IO
1050 * This is a _temporary_ fix to workaround a problem with Apple's OF
1051 * closing IO windows on P2P bridges when the OF drivers of cards
1052 * below this bridge don't claim any IO range (typically ATI or
1055 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1056 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1057 * ordering when creating the host bus resources, and maybe a few more
1061 /* Initialize bridges with base/limit values we have collected */
1063 do_update_p2p_io_resource(struct pci_bus *bus, int enable_vga)
1065 struct pci_dev *bridge = bus->self;
1066 struct pci_controller* hose = (struct pci_controller *)bridge->sysdata;
1069 struct resource res;
1071 if (bus->resource[0] == NULL)
1073 res = *(bus->resource[0]);
1075 DBG("Remapping Bus %d, bridge: %s\n", bus->number, pci_name(bridge));
1076 res.start -= ((unsigned long) hose->io_base_virt - isa_io_base);
1077 res.end -= ((unsigned long) hose->io_base_virt - isa_io_base);
1078 DBG(" IO window: %016llx-%016llx\n", res.start, res.end);
1080 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1081 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
1083 l |= (res.start >> 8) & 0x00f0;
1084 l |= res.end & 0xf000;
1085 pci_write_config_dword(bridge, PCI_IO_BASE, l);
1087 if ((l & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1088 l = (res.start >> 16) | (res.end & 0xffff0000);
1089 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, l);
1092 pci_read_config_word(bridge, PCI_COMMAND, &w);
1093 w |= PCI_COMMAND_IO;
1094 pci_write_config_word(bridge, PCI_COMMAND, w);
1096 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1098 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, &w);
1099 w |= PCI_BRIDGE_CTL_VGA;
1100 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, w);
1105 /* This function is pretty basic and actually quite broken for the
1106 * general case, it's enough for us right now though. It's supposed
1107 * to tell us if we need to open an IO range at all or not and what
1111 check_for_io_childs(struct pci_bus *bus, struct resource* res, int *found_vga)
1113 struct pci_dev *dev;
1117 #define push_end(res, mask) do { \
1118 BUG_ON((mask+1) & mask); \
1119 res->end = (res->end + mask) | mask; \
1122 list_for_each_entry(dev, &bus->devices, bus_list) {
1123 u16 class = dev->class >> 8;
1125 if (class == PCI_CLASS_DISPLAY_VGA ||
1126 class == PCI_CLASS_NOT_DEFINED_VGA)
1128 if (class >> 8 == PCI_BASE_CLASS_BRIDGE && dev->subordinate)
1129 rc |= check_for_io_childs(dev->subordinate, res, found_vga);
1130 if (class == PCI_CLASS_BRIDGE_CARDBUS)
1131 push_end(res, 0xfff);
1133 for (i=0; i<PCI_NUM_RESOURCES; i++) {
1135 unsigned long r_size;
1137 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI
1138 && i >= PCI_BRIDGE_RESOURCES)
1140 r = &dev->resource[i];
1141 r_size = r->end - r->start;
1144 if (r->flags & IORESOURCE_IO && (r_size) != 0) {
1146 push_end(res, r_size);
1154 /* Here we scan all P2P bridges of a given level that have a closed
1155 * IO window. Note that the test for the presence of a VGA card should
1156 * be improved to take into account already configured P2P bridges,
1157 * currently, we don't see them and might end up configuring 2 bridges
1158 * with VGA pass through enabled
1161 do_fixup_p2p_level(struct pci_bus *bus)
1167 for (parent_io=0; parent_io<4; parent_io++)
1168 if (bus->resource[parent_io]
1169 && bus->resource[parent_io]->flags & IORESOURCE_IO)
1174 list_for_each_entry(b, &bus->children, node) {
1175 struct pci_dev *d = b->self;
1176 struct pci_controller* hose = (struct pci_controller *)d->sysdata;
1177 struct resource *res = b->resource[0];
1178 struct resource tmp_res;
1182 memset(&tmp_res, 0, sizeof(tmp_res));
1183 tmp_res.start = bus->resource[parent_io]->start;
1185 /* We don't let low addresses go through that closed P2P bridge, well,
1186 * that may not be necessary but I feel safer that way
1188 if (tmp_res.start == 0)
1189 tmp_res.start = 0x1000;
1191 if (!list_empty(&b->devices) && res && res->flags == 0 &&
1192 res != bus->resource[parent_io] &&
1193 (d->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1194 check_for_io_childs(b, &tmp_res, &found_vga)) {
1197 printk(KERN_INFO "Fixing up IO bus %s\n", b->name);
1201 printk(KERN_WARNING "Skipping VGA, already active"
1202 " on bus segment\n");
1207 pci_read_config_byte(d, PCI_IO_BASE, &io_base_lo);
1209 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32)
1210 max = ((unsigned long) hose->io_base_virt
1211 - isa_io_base) + 0xffffffff;
1213 max = ((unsigned long) hose->io_base_virt
1214 - isa_io_base) + 0xffff;
1217 res->flags = IORESOURCE_IO;
1218 res->name = b->name;
1220 /* Find a resource in the parent where we can allocate */
1221 for (i = 0 ; i < 4; i++) {
1222 struct resource *r = bus->resource[i];
1225 if ((r->flags & IORESOURCE_IO) == 0)
1227 DBG("Trying to allocate from %016llx, size %016llx from parent"
1228 " res %d: %016llx -> %016llx\n",
1229 res->start, res->end, i, r->start, r->end);
1231 if (allocate_resource(r, res, res->end + 1, res->start, max,
1232 res->end + 1, NULL, NULL) < 0) {
1236 do_update_p2p_io_resource(b, found_vga);
1240 do_fixup_p2p_level(b);
1245 pcibios_fixup_p2p_bridges(void)
1249 list_for_each_entry(b, &pci_root_buses, node)
1250 do_fixup_p2p_level(b);
1253 #endif /* CONFIG_PPC_PMAC */
1258 struct pci_controller *hose;
1259 struct pci_bus *bus;
1262 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1264 /* Scan all of the recorded PCI controllers. */
1265 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
1266 if (pci_assign_all_buses)
1267 hose->first_busno = next_busno;
1268 hose->last_busno = 0xff;
1269 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
1270 hose->last_busno = bus->subordinate;
1271 if (pci_assign_all_buses || next_busno <= hose->last_busno)
1272 next_busno = hose->last_busno + pcibios_assign_bus_offset;
1274 pci_bus_count = next_busno;
1276 /* OpenFirmware based machines need a map of OF bus
1277 * numbers vs. kernel bus numbers since we may have to
1280 if (pci_assign_all_buses && have_of)
1281 pcibios_make_OF_bus_map();
1283 /* Do machine dependent PCI interrupt routing */
1284 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
1285 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
1287 /* Call machine dependent fixup */
1288 if (ppc_md.pcibios_fixup)
1289 ppc_md.pcibios_fixup();
1291 /* Allocate and assign resources */
1292 pcibios_allocate_bus_resources(&pci_root_buses);
1293 pcibios_allocate_resources(0);
1294 pcibios_allocate_resources(1);
1295 #ifdef CONFIG_PPC_PMAC
1296 pcibios_fixup_p2p_bridges();
1297 #endif /* CONFIG_PPC_PMAC */
1298 pcibios_assign_resources();
1300 /* Call machine dependent post-init code */
1301 if (ppc_md.pcibios_after_init)
1302 ppc_md.pcibios_after_init();
1307 subsys_initcall(pcibios_init);
1309 unsigned char __init
1310 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
1312 struct pci_controller *hose = dev->sysdata;
1314 if (dev->bus->number != hose->first_busno) {
1317 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
1318 /* Move up the chain of bridges. */
1319 dev = dev->bus->self;
1320 } while (dev->bus->self);
1323 /* The slot is the idsel of the last bridge. */
1325 return PCI_SLOT(dev->devfn);
1328 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
1329 unsigned long start, unsigned long size)
1334 void __init pcibios_fixup_bus(struct pci_bus *bus)
1336 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1337 unsigned long io_offset;
1338 struct resource *res;
1341 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1342 if (bus->parent == NULL) {
1343 /* This is a host bridge - fill in its resources */
1346 bus->resource[0] = res = &hose->io_resource;
1349 printk(KERN_ERR "I/O resource not set for host"
1350 " bridge %d\n", hose->index);
1352 res->end = IO_SPACE_LIMIT;
1353 res->flags = IORESOURCE_IO;
1355 res->start += io_offset;
1356 res->end += io_offset;
1358 for (i = 0; i < 3; ++i) {
1359 res = &hose->mem_resources[i];
1363 printk(KERN_ERR "Memory resource not set for "
1364 "host bridge %d\n", hose->index);
1365 res->start = hose->pci_mem_offset;
1367 res->flags = IORESOURCE_MEM;
1369 bus->resource[i+1] = res;
1372 /* This is a subordinate bridge */
1373 pci_read_bridge_bases(bus);
1375 for (i = 0; i < 4; ++i) {
1376 if ((res = bus->resource[i]) == NULL)
1380 if (io_offset && (res->flags & IORESOURCE_IO)) {
1381 res->start += io_offset;
1382 res->end += io_offset;
1383 } else if (hose->pci_mem_offset
1384 && (res->flags & IORESOURCE_MEM)) {
1385 res->start += hose->pci_mem_offset;
1386 res->end += hose->pci_mem_offset;
1391 if (ppc_md.pcibios_fixup_bus)
1392 ppc_md.pcibios_fixup_bus(bus);
1395 char __init *pcibios_setup(char *str)
1400 /* the next one is stolen from the alpha port... */
1402 pcibios_update_irq(struct pci_dev *dev, int irq)
1404 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
1405 /* XXX FIXME - update OF device tree node interrupt property */
1408 int pcibios_enable_device(struct pci_dev *dev, int mask)
1414 if (ppc_md.pcibios_enable_device_hook)
1415 if (ppc_md.pcibios_enable_device_hook(dev, 0))
1418 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1420 for (idx=0; idx<6; idx++) {
1421 r = &dev->resource[idx];
1422 if (r->flags & IORESOURCE_UNSET) {
1423 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
1426 if (r->flags & IORESOURCE_IO)
1427 cmd |= PCI_COMMAND_IO;
1428 if (r->flags & IORESOURCE_MEM)
1429 cmd |= PCI_COMMAND_MEMORY;
1431 if (cmd != old_cmd) {
1432 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1433 pci_name(dev), old_cmd, cmd);
1434 pci_write_config_word(dev, PCI_COMMAND, cmd);
1439 struct pci_controller*
1440 pci_bus_to_hose(int bus)
1442 struct pci_controller* hose = hose_head;
1444 for (; hose; hose = hose->next)
1445 if (bus >= hose->first_busno && bus <= hose->last_busno)
1451 pci_bus_io_base(unsigned int bus)
1453 struct pci_controller *hose;
1455 hose = pci_bus_to_hose(bus);
1458 return hose->io_base_virt;
1462 pci_bus_io_base_phys(unsigned int bus)
1464 struct pci_controller *hose;
1466 hose = pci_bus_to_hose(bus);
1469 return hose->io_base_phys;
1473 pci_bus_mem_base_phys(unsigned int bus)
1475 struct pci_controller *hose;
1477 hose = pci_bus_to_hose(bus);
1480 return hose->pci_mem_offset;
1484 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
1486 /* Hack alert again ! See comments in chrp_pci.c
1488 struct pci_controller* hose =
1489 (struct pci_controller *)pdev->sysdata;
1490 if (hose && res->flags & IORESOURCE_MEM)
1491 return res->start - hose->pci_mem_offset;
1492 /* We may want to do something with IOs here... */
1497 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
1498 unsigned long *offset,
1499 enum pci_mmap_state mmap_state)
1501 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1502 unsigned long io_offset = 0;
1506 return NULL; /* should never happen */
1508 /* If memory, add on the PCI bridge address offset */
1509 if (mmap_state == pci_mmap_mem) {
1510 *offset += hose->pci_mem_offset;
1511 res_bit = IORESOURCE_MEM;
1513 io_offset = hose->io_base_virt - ___IO_BASE;
1514 *offset += io_offset;
1515 res_bit = IORESOURCE_IO;
1519 * Check that the offset requested corresponds to one of the
1520 * resources of the device.
1522 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1523 struct resource *rp = &dev->resource[i];
1524 int flags = rp->flags;
1526 /* treat ROM as memory (should be already) */
1527 if (i == PCI_ROM_RESOURCE)
1528 flags |= IORESOURCE_MEM;
1530 /* Active and same type? */
1531 if ((flags & res_bit) == 0)
1534 /* In the range of this resource? */
1535 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
1538 /* found it! construct the final physical address */
1539 if (mmap_state == pci_mmap_io)
1540 *offset += hose->io_base_phys - io_offset;
1548 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1551 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
1552 pgprot_t protection,
1553 enum pci_mmap_state mmap_state,
1556 unsigned long prot = pgprot_val(protection);
1558 /* Write combine is always 0 on non-memory space mappings. On
1559 * memory space, if the user didn't pass 1, we check for a
1560 * "prefetchable" resource. This is a bit hackish, but we use
1561 * this to workaround the inability of /sysfs to provide a write
1564 if (mmap_state != pci_mmap_mem)
1566 else if (write_combine == 0) {
1567 if (rp->flags & IORESOURCE_PREFETCH)
1571 /* XXX would be nice to have a way to ask for write-through */
1572 prot |= _PAGE_NO_CACHE;
1574 prot &= ~_PAGE_GUARDED;
1576 prot |= _PAGE_GUARDED;
1578 printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev),
1579 (unsigned long long)rp->start, prot);
1581 return __pgprot(prot);
1585 * This one is used by /dev/mem and fbdev who have no clue about the
1586 * PCI device, it tries to find the PCI device first and calls the
1589 pgprot_t pci_phys_mem_access_prot(struct file *file,
1592 pgprot_t protection)
1594 struct pci_dev *pdev = NULL;
1595 struct resource *found = NULL;
1596 unsigned long prot = pgprot_val(protection);
1597 unsigned long offset = pfn << PAGE_SHIFT;
1600 if (page_is_ram(pfn))
1603 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
1605 for_each_pci_dev(pdev) {
1606 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1607 struct resource *rp = &pdev->resource[i];
1608 int flags = rp->flags;
1610 /* Active and same type? */
1611 if ((flags & IORESOURCE_MEM) == 0)
1613 /* In the range of this resource? */
1614 if (offset < (rp->start & PAGE_MASK) ||
1624 if (found->flags & IORESOURCE_PREFETCH)
1625 prot &= ~_PAGE_GUARDED;
1629 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1631 return __pgprot(prot);
1636 * Perform the actual remap of the pages for a PCI device mapping, as
1637 * appropriate for this architecture. The region in the process to map
1638 * is described by vm_start and vm_end members of VMA, the base physical
1639 * address is found in vm_pgoff.
1640 * The pci device structure is provided so that architectures may make mapping
1641 * decisions on a per-device or per-bus basis.
1643 * Returns a negative error code on failure, zero on success.
1645 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1646 enum pci_mmap_state mmap_state,
1649 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1650 struct resource *rp;
1653 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1657 vma->vm_pgoff = offset >> PAGE_SHIFT;
1658 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1660 mmap_state, write_combine);
1662 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1663 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1668 /* Obsolete functions. Should be removed once the symbios driver
1672 phys_to_bus(unsigned long pa)
1674 struct pci_controller *hose;
1677 for (hose = hose_head; hose; hose = hose->next) {
1678 for (i = 0; i < 3; ++i) {
1679 if (pa >= hose->mem_resources[i].start
1680 && pa <= hose->mem_resources[i].end) {
1682 * XXX the hose->pci_mem_offset really
1683 * only applies to mem_resources[0].
1684 * We need a way to store an offset for
1685 * the others. -- paulus
1688 pa -= hose->pci_mem_offset;
1693 /* hmmm, didn't find it */
1698 pci_phys_to_bus(unsigned long pa, int busnr)
1700 struct pci_controller* hose = pci_bus_to_hose(busnr);
1703 return pa - hose->pci_mem_offset;
1707 pci_bus_to_phys(unsigned int ba, int busnr)
1709 struct pci_controller* hose = pci_bus_to_hose(busnr);
1712 return ba + hose->pci_mem_offset;
1715 /* Provide information on locations of various I/O regions in physical
1716 * memory. Do this on a per-card basis so that we choose the right
1718 * Note that the returned IO or memory base is a physical address
1721 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1723 struct pci_controller* hose;
1724 long result = -EOPNOTSUPP;
1726 /* Argh ! Please forgive me for that hack, but that's the
1727 * simplest way to get existing XFree to not lockup on some
1728 * G5 machines... So when something asks for bus 0 io base
1729 * (bus 0 is HT root), we return the AGP one instead.
1731 #ifdef CONFIG_PPC_PMAC
1732 if (machine_is(powermac) && machine_is_compatible("MacRISC4"))
1735 #endif /* CONFIG_PPC_PMAC */
1737 hose = pci_bus_to_hose(bus);
1742 case IOBASE_BRIDGE_NUMBER:
1743 return (long)hose->first_busno;
1745 return (long)hose->pci_mem_offset;
1747 return (long)hose->io_base_phys;
1749 return (long)isa_io_base;
1750 case IOBASE_ISA_MEM:
1751 return (long)isa_mem_base;
1757 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1758 const struct resource *rsrc,
1759 resource_size_t *start, resource_size_t *end)
1761 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1762 unsigned long offset = 0;
1767 if (rsrc->flags & IORESOURCE_IO)
1768 offset = ___IO_BASE - hose->io_base_virt + hose->io_base_phys;
1770 *start = rsrc->start + offset;
1771 *end = rsrc->end + offset;
1775 pci_init_resource(struct resource *res, unsigned long start, unsigned long end,
1776 int flags, char *name)
1783 res->sibling = NULL;
1787 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1789 unsigned long start = pci_resource_start(dev, bar);
1790 unsigned long len = pci_resource_len(dev, bar);
1791 unsigned long flags = pci_resource_flags(dev, bar);
1795 if (max && len > max)
1797 if (flags & IORESOURCE_IO)
1798 return ioport_map(start, len);
1799 if (flags & IORESOURCE_MEM)
1800 /* Not checking IORESOURCE_CACHEABLE because PPC does
1801 * not currently distinguish between ioremap and
1804 return ioremap(start, len);
1809 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1813 EXPORT_SYMBOL(pci_iomap);
1814 EXPORT_SYMBOL(pci_iounmap);
1816 unsigned long pci_address_to_pio(phys_addr_t address)
1818 struct pci_controller* hose = hose_head;
1820 for (; hose; hose = hose->next) {
1821 unsigned int size = hose->io_resource.end -
1822 hose->io_resource.start + 1;
1823 if (address >= hose->io_base_phys &&
1824 address < (hose->io_base_phys + size)) {
1825 unsigned long base =
1826 (unsigned long)hose->io_base_virt - _IO_BASE;
1827 return base + (address - hose->io_base_phys);
1830 return (unsigned int)-1;
1832 EXPORT_SYMBOL(pci_address_to_pio);
1835 * Null PCI config access functions, for the case when we can't
1838 #define NULL_PCI_OP(rw, size, type) \
1840 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1842 return PCIBIOS_DEVICE_NOT_FOUND; \
1846 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1849 return PCIBIOS_DEVICE_NOT_FOUND;
1853 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1856 return PCIBIOS_DEVICE_NOT_FOUND;
1859 static struct pci_ops null_pci_ops =
1866 * These functions are used early on before PCI scanning is done
1867 * and all of the pci_dev and pci_bus structures have been created.
1869 static struct pci_bus *
1870 fake_pci_bus(struct pci_controller *hose, int busnr)
1872 static struct pci_bus bus;
1875 hose = pci_bus_to_hose(busnr);
1877 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1881 bus.ops = hose? hose->ops: &null_pci_ops;
1885 #define EARLY_PCI_OP(rw, size, type) \
1886 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1887 int devfn, int offset, type value) \
1889 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1890 devfn, offset, value); \
1893 EARLY_PCI_OP(read, byte, u8 *)
1894 EARLY_PCI_OP(read, word, u16 *)
1895 EARLY_PCI_OP(read, dword, u32 *)
1896 EARLY_PCI_OP(write, byte, u8)
1897 EARLY_PCI_OP(write, word, u16)
1898 EARLY_PCI_OP(write, dword, u32)