3 * Programmable Interrupt Controller functions for the Freescale MPC52xx.
5 * Copyright (C) 2006 bplan GmbH
7 * Based on the code from the 2.4 kernel by
8 * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
10 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
11 * Copyright (C) 2003 Montavista Software, Inc
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
21 #include <linux/stddef.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/signal.h>
25 #include <linux/delay.h>
26 #include <linux/irq.h>
27 #include <linux/hardirq.h>
30 #include <asm/processor.h>
31 #include <asm/system.h>
34 #include <asm/mpc52xx.h>
35 #include "mpc52xx_pic.h"
41 static struct mpc52xx_intr __iomem *intr;
42 static struct mpc52xx_sdma __iomem *sdma;
43 static struct irq_host *mpc52xx_irqhost = NULL;
45 static unsigned char mpc52xx_map_senses[4] = {
48 IRQ_TYPE_EDGE_FALLING,
56 static inline void io_be_setbit(u32 __iomem *addr, int bitno)
58 out_be32(addr, in_be32(addr) | (1 << bitno));
61 static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
63 out_be32(addr, in_be32(addr) & ~(1 << bitno));
67 * IRQ[0-3] interrupt irq_chip
70 static void mpc52xx_extirq_mask(unsigned int virq)
75 irq = irq_map[virq].hwirq;
76 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
78 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
80 io_be_clrbit(&intr->ctrl, 11 - l2irq);
83 static void mpc52xx_extirq_unmask(unsigned int virq)
88 irq = irq_map[virq].hwirq;
89 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
91 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
93 io_be_setbit(&intr->ctrl, 11 - l2irq);
96 static void mpc52xx_extirq_ack(unsigned int virq)
101 irq = irq_map[virq].hwirq;
102 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
104 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
106 io_be_setbit(&intr->ctrl, 27-l2irq);
109 static struct irq_chip mpc52xx_extirq_irqchip = {
110 .typename = " MPC52xx IRQ[0-3] ",
111 .mask = mpc52xx_extirq_mask,
112 .unmask = mpc52xx_extirq_unmask,
113 .ack = mpc52xx_extirq_ack,
117 * Main interrupt irq_chip
120 static void mpc52xx_main_mask(unsigned int virq)
125 irq = irq_map[virq].hwirq;
126 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
128 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
130 io_be_setbit(&intr->main_mask, 16 - l2irq);
133 static void mpc52xx_main_unmask(unsigned int virq)
138 irq = irq_map[virq].hwirq;
139 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
141 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
143 io_be_clrbit(&intr->main_mask, 16 - l2irq);
146 static struct irq_chip mpc52xx_main_irqchip = {
147 .typename = "MPC52xx Main",
148 .mask = mpc52xx_main_mask,
149 .mask_ack = mpc52xx_main_mask,
150 .unmask = mpc52xx_main_unmask,
154 * Peripherals interrupt irq_chip
157 static void mpc52xx_periph_mask(unsigned int virq)
162 irq = irq_map[virq].hwirq;
163 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
165 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
167 io_be_setbit(&intr->per_mask, 31 - l2irq);
170 static void mpc52xx_periph_unmask(unsigned int virq)
175 irq = irq_map[virq].hwirq;
176 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
178 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
180 io_be_clrbit(&intr->per_mask, 31 - l2irq);
183 static struct irq_chip mpc52xx_periph_irqchip = {
184 .typename = "MPC52xx Peripherals",
185 .mask = mpc52xx_periph_mask,
186 .mask_ack = mpc52xx_periph_mask,
187 .unmask = mpc52xx_periph_unmask,
191 * SDMA interrupt irq_chip
194 static void mpc52xx_sdma_mask(unsigned int virq)
199 irq = irq_map[virq].hwirq;
200 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
202 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
204 io_be_setbit(&sdma->IntMask, l2irq);
207 static void mpc52xx_sdma_unmask(unsigned int virq)
212 irq = irq_map[virq].hwirq;
213 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
215 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
217 io_be_clrbit(&sdma->IntMask, l2irq);
220 static void mpc52xx_sdma_ack(unsigned int virq)
225 irq = irq_map[virq].hwirq;
226 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
228 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
230 out_be32(&sdma->IntPend, 1 << l2irq);
233 static struct irq_chip mpc52xx_sdma_irqchip = {
234 .typename = "MPC52xx SDMA",
235 .mask = mpc52xx_sdma_mask,
236 .unmask = mpc52xx_sdma_unmask,
237 .ack = mpc52xx_sdma_ack,
244 static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
246 pr_debug("%s: node=%p\n", __func__, node);
247 return mpc52xx_irqhost->host_data == node;
250 static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
251 u32 * intspec, unsigned int intsize,
252 irq_hw_number_t * out_hwirq,
253 unsigned int *out_flags)
263 intrvect_l1 = (int)intspec[0];
264 intrvect_l2 = (int)intspec[1];
265 intrvect_type = (int)intspec[2];
268 (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
270 (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
272 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
275 *out_hwirq = intrvect_linux;
276 *out_flags = mpc52xx_map_senses[intrvect_type];
282 * this function retrieves the correct IRQ type out
284 * Only externals IRQs needs this
286 static int mpc52xx_irqx_gettype(int irq)
291 ctrl_reg = in_be32(&intr->ctrl);
292 type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
294 return mpc52xx_map_senses[type];
297 static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
302 struct irq_chip *good_irqchip;
306 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
307 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
310 * Most of ours IRQs will be level low
311 * Only external IRQs on some platform may be others
313 type = IRQ_TYPE_LEVEL_LOW;
316 case MPC52xx_IRQ_L1_CRIT:
317 pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
321 type = mpc52xx_irqx_gettype(l2irq);
322 good_irqchip = &mpc52xx_extirq_irqchip;
325 case MPC52xx_IRQ_L1_MAIN:
326 pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
328 if ((l2irq >= 1) && (l2irq <= 3)) {
329 type = mpc52xx_irqx_gettype(l2irq);
330 good_irqchip = &mpc52xx_extirq_irqchip;
332 good_irqchip = &mpc52xx_main_irqchip;
336 case MPC52xx_IRQ_L1_PERP:
337 pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
338 good_irqchip = &mpc52xx_periph_irqchip;
341 case MPC52xx_IRQ_L1_SDMA:
342 pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
343 good_irqchip = &mpc52xx_sdma_irqchip;
347 pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
348 printk(KERN_ERR "Unknow IRQ!\n");
353 case IRQ_TYPE_EDGE_FALLING:
354 case IRQ_TYPE_EDGE_RISING:
355 good_handle = handle_edge_irq;
358 good_handle = handle_level_irq;
361 set_irq_chip_and_handler(virq, good_irqchip, good_handle);
363 pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
369 static struct irq_host_ops mpc52xx_irqhost_ops = {
370 .match = mpc52xx_irqhost_match,
371 .xlate = mpc52xx_irqhost_xlate,
372 .map = mpc52xx_irqhost_map,
379 void __init mpc52xx_init_irq(void)
382 struct device_node *picnode;
384 /* Remap the necessary zones */
385 picnode = of_find_compatible_node(NULL, NULL, "mpc5200-pic");
387 intr = mpc52xx_find_and_map("mpc5200-pic");
389 panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. "
392 sdma = mpc52xx_find_and_map("mpc5200-bestcomm");
394 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
397 /* Disable all interrupt sources. */
398 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
399 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
400 out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
401 out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
402 intr_ctrl = in_be32(&intr->ctrl);
403 intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
404 intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
405 0x00001000 | /* MEE master external enable */
406 0x00000000 | /* 0 means disable IRQ 0-3 */
407 0x00000001; /* CEb route critical normally */
408 out_be32(&intr->ctrl, intr_ctrl);
410 /* Zero a bunch of the priority settings. */
411 out_be32(&intr->per_pri1, 0);
412 out_be32(&intr->per_pri2, 0);
413 out_be32(&intr->per_pri3, 0);
414 out_be32(&intr->main_pri1, 0);
415 out_be32(&intr->main_pri2, 0);
418 * As last step, add an irq host to translate the real
419 * hw irq information provided by the ofw to linux virq
422 mpc52xx_irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
423 MPC52xx_IRQ_HIGHTESTHWIRQ,
424 &mpc52xx_irqhost_ops, -1);
426 if (!mpc52xx_irqhost)
427 panic(__FILE__ ": Cannot allocate the IRQ host\n");
429 mpc52xx_irqhost->host_data = picnode;
430 printk(KERN_INFO "MPC52xx PIC is up and running!\n");
436 unsigned int mpc52xx_get_irq(void)
439 int irq = NO_IRQ_IGNORE;
441 status = in_be32(&intr->enc_status);
442 if (status & 0x00000400) { /* critical */
443 irq = (status >> 8) & 0x3;
444 if (irq == 2) /* high priority peripheral */
446 irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
448 } else if (status & 0x00200000) { /* main */
449 irq = (status >> 16) & 0x1f;
450 if (irq == 4) /* low priority peripheral */
452 irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
454 } else if (status & 0x20000000) { /* peripheral */
456 irq = (status >> 24) & 0x1f;
457 if (irq == 0) { /* bestcomm */
458 status = in_be32(&sdma->IntPend);
459 irq = ffs(status) - 1;
460 irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
463 irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
468 pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
469 irq_linear_revmap(mpc52xx_irqhost, irq));
471 return irq_linear_revmap(mpc52xx_irqhost, irq);