2 * General Purpose functions for the global management of the
3 * Communication Processor Module.
4 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
6 * In addition to the individual control of the communication
7 * channels, there are a few functions that globally affect the
8 * communication processor.
10 * Buffer descriptors must be allocated from the dual ported memory
11 * space. The allocator for that is here. When the communication
12 * process is reset, we reclaim the memory available. There is
13 * currently no deallocator for this memory.
14 * The amount of space available is platform dependent. On the
15 * MBX, the EPPC software loads additional microcode into the
16 * communication processor, and uses some of the DP ram for this
17 * purpose. Current, the first 512 bytes and the last 256 bytes of
18 * memory are used. Right now I am conservative and only use the
19 * memory that can never be used for microcode. If there are
20 * applications that require more DP ram, we can expand the boundaries
21 * but then we have to be careful of any downloaded microcode.
23 #include <linux/errno.h>
24 #include <linux/sched.h>
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/param.h>
28 #include <linux/string.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <asm/mpc8xx.h>
35 #include <asm/pgtable.h>
36 #include <asm/8xx_immap.h>
37 #include <asm/commproc.h>
39 #include <asm/tlbflush.h>
40 #include <asm/rheap.h>
43 #include <asm/fs_pd.h>
45 #define CPM_MAP_SIZE (0x4000)
47 static void m8xx_cpm_dpinit(void);
48 static uint host_buffer; /* One page of host buffer */
49 static uint host_end; /* end + 1 */
50 cpm8xx_t *cpmp; /* Pointer to comm processor space */
53 static struct irq_host *cpm_pic_host;
55 static void cpm_mask_irq(unsigned int irq)
57 unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
59 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
62 static void cpm_unmask_irq(unsigned int irq)
64 unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
66 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
69 static void cpm_end_irq(unsigned int irq)
71 unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
73 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
76 static struct irq_chip cpm_pic = {
77 .typename = " CPM PIC ",
79 .unmask = cpm_unmask_irq,
87 /* Get the vector by setting the ACK bit and then reading
90 out_be16(&cpic_reg->cpic_civr, 1);
91 cpm_vec = in_be16(&cpic_reg->cpic_civr);
94 return irq_linear_revmap(cpm_pic_host, cpm_vec);
97 static int cpm_pic_host_match(struct irq_host *h, struct device_node *node)
99 return h->of_node == node;
102 static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
105 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
107 get_irq_desc(virq)->status |= IRQ_LEVEL;
108 set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
112 /* The CPM can generate the error interrupt when there is a race condition
113 * between generating and masking interrupts. All we have to do is ACK it
114 * and return. This is a no-op function so we don't need any special
115 * tests in the interrupt handler.
117 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
122 static struct irqaction cpm_error_irqaction = {
123 .handler = cpm_error_interrupt,
124 .mask = CPU_MASK_NONE,
128 static struct irq_host_ops cpm_pic_host_ops = {
129 .match = cpm_pic_host_match,
130 .map = cpm_pic_host_map,
133 unsigned int cpm_pic_init(void)
135 struct device_node *np = NULL;
137 unsigned int sirq = NO_IRQ, hwirq, eirq;
140 pr_debug("cpm_pic_init\n");
142 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
144 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
147 ret = of_address_to_resource(np, 0, &res);
151 cpic_reg = (void *)ioremap(res.start, res.end - res.start + 1);
152 if (cpic_reg == NULL)
155 sirq = irq_of_parse_and_map(np, 0);
159 /* Initialize the CPM interrupt controller. */
160 hwirq = (unsigned int)irq_map[sirq].hwirq;
161 out_be32(&cpic_reg->cpic_cicr,
162 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
163 ((hwirq/2) << 13) | CICR_HP_MASK);
165 out_be32(&cpic_reg->cpic_cimr, 0);
167 cpm_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR,
168 64, &cpm_pic_host_ops, 64);
169 if (cpm_pic_host == NULL) {
170 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
176 /* Install our own error handler. */
177 np = of_find_node_by_type(NULL, "cpm");
179 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
182 eirq = irq_of_parse_and_map(np, 0);
186 if (setup_irq(eirq, &cpm_error_irqaction))
187 printk(KERN_ERR "Could not allocate CPM error IRQ!");
189 setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
199 sysconf8xx_t *siu_conf;
201 commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
203 #ifdef CONFIG_UCODE_PATCH
206 out_be16(&commproc->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
210 while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);
212 cpm_load_patch(commproc);
215 /* Set SDMA Bus Request priority 5.
216 * On 860T, this also enables FEC priority 6. I am not sure
217 * this is what we realy want for some applications, but the
218 * manual recommends it.
219 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
221 siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);
222 out_be32(&siu_conf->sc_sdcr, 1);
223 immr_unmap(siu_conf);
225 /* Reclaim the DP memory for our use. */
228 /* Tell everyone where the comm processor resides.
233 /* We used to do this earlier, but have to postpone as long as possible
234 * to ensure the kernel VM is now running.
237 alloc_host_memory(void)
241 /* Set the host page for allocation.
243 host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr,
245 host_end = host_buffer + PAGE_SIZE;
248 /* We also own one page of host buffer space for the allocation of
249 * UART "fifos" and the like.
252 m8xx_cpm_hostalloc(uint size)
256 if (host_buffer == 0)
259 if ((host_buffer + size) >= host_end)
262 retloc = host_buffer;
268 /* Set a baud rate generator. This needs lots of work. There are
269 * four BRGs, any of which can be wired to any channel.
270 * The internal baud rate clock is the system clock divided by 16.
271 * This assumes the baudrate is 16x oversampled by the uart.
273 #define BRG_INT_CLK (get_brgfreq())
274 #define BRG_UART_CLK (BRG_INT_CLK/16)
275 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
278 cpm_setbrg(uint brg, uint rate)
282 /* This is good enough to get SMCs running.....
284 bp = (uint *)&cpmp->cp_brgc1;
286 /* The BRG has a 12-bit counter. For really slow baud rates (or
287 * really fast processors), we may have to further divide by 16.
289 if (((BRG_UART_CLK / rate) - 1) < 4096)
290 *bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
292 *bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
293 CPM_BRG_EN | CPM_BRG_DIV16;
297 * dpalloc / dpfree bits.
299 static spinlock_t cpm_dpmem_lock;
301 * 16 blocks should be enough to satisfy all requests
302 * until the memory subsystem goes up...
304 static rh_block_t cpm_boot_dpmem_rh_block[16];
305 static rh_info_t cpm_dpmem_info;
307 #define CPM_DPMEM_ALIGNMENT 8
308 static u8 *dpram_vbase;
309 static uint dpram_pbase;
311 void m8xx_cpm_dpinit(void)
313 spin_lock_init(&cpm_dpmem_lock);
315 dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
316 dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;
318 /* Initialize the info header */
319 rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
320 sizeof(cpm_boot_dpmem_rh_block) /
321 sizeof(cpm_boot_dpmem_rh_block[0]),
322 cpm_boot_dpmem_rh_block);
325 * Attach the usable dpmem area.
326 * XXX: This is actually crap. CPM_DATAONLY_BASE and
327 * CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
328 * with the processor and the microcode patches applied / activated.
329 * But the following should be at least safe.
331 rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
335 * Allocate the requested size worth of DP memory.
336 * This function returns an offset into the DPRAM area.
337 * Use cpm_dpram_addr() to get the virtual address of the area.
339 unsigned long cpm_dpalloc(uint size, uint align)
344 spin_lock_irqsave(&cpm_dpmem_lock, flags);
345 cpm_dpmem_info.alignment = align;
346 start = rh_alloc(&cpm_dpmem_info, size, "commproc");
347 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
351 EXPORT_SYMBOL(cpm_dpalloc);
353 int cpm_dpfree(unsigned long offset)
358 spin_lock_irqsave(&cpm_dpmem_lock, flags);
359 ret = rh_free(&cpm_dpmem_info, offset);
360 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
364 EXPORT_SYMBOL(cpm_dpfree);
366 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
371 spin_lock_irqsave(&cpm_dpmem_lock, flags);
372 cpm_dpmem_info.alignment = align;
373 start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
374 spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
378 EXPORT_SYMBOL(cpm_dpalloc_fixed);
380 void cpm_dpdump(void)
382 rh_dump(&cpm_dpmem_info);
384 EXPORT_SYMBOL(cpm_dpdump);
386 void *cpm_dpram_addr(unsigned long offset)
388 return (void *)(dpram_vbase + offset);
390 EXPORT_SYMBOL(cpm_dpram_addr);
392 uint cpm_dpram_phys(u8* addr)
394 return (dpram_pbase + (uint)(addr - dpram_vbase));
396 EXPORT_SYMBOL(cpm_dpram_addr);