arch/powerpc/sysdev/mpic.c

   1 /*
   2  *  arch/powerpc/kernel/mpic.c
   3  *
   4  *  Driver for interrupt controllers following the OpenPIC standard, the
   5  *  common implementation beeing IBM's MPIC. This driver also can deal
   6  *  with various broken implementations of this HW.
   7  *
   8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General Public
  11  *  License.  See the file COPYING in the main directory of this archive
  12  *  for more details.
  13  */
  14
  15 #undef DEBUG
  16 #undef DEBUG_IPI
  17 #undef DEBUG_IRQ
  18 #undef DEBUG_LOW
  19
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/irq.h>
  24 #include <linux/smp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29
  30 #include <asm/ptrace.h>
  31 #include <asm/signal.h>
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/irq.h>
  35 #include <asm/machdep.h>
  36 #include <asm/mpic.h>
  37 #include <asm/smp.h>
  38
  39 #ifdef DEBUG
  40 #define DBG(fmt...) printk(fmt)
  41 #else
  42 #define DBG(fmt...)
  43 #endif
  44
  45 static struct mpic *mpics;
  46 static struct mpic *mpic_primary;
  47 static DEFINE_SPINLOCK(mpic_lock);
  48
  49 #ifdef CONFIG_PPC32     /* XXX for now */
  50 #ifdef CONFIG_IRQ_ALL_CPUS
  51 #define distribute_irqs (1)
  52 #else
  53 #define distribute_irqs (0)
  54 #endif
  55 #endif
  56
  57 #ifdef CONFIG_MPIC_WEIRD
  58 static u32 mpic_infos[][MPIC_IDX_END] = {
  59         [0] = { /* Original OpenPIC compatible MPIC */
  60                 MPIC_GREG_BASE,
  61                 MPIC_GREG_FEATURE_0,
  62                 MPIC_GREG_GLOBAL_CONF_0,
  63                 MPIC_GREG_VENDOR_ID,
  64                 MPIC_GREG_IPI_VECTOR_PRI_0,
  65                 MPIC_GREG_IPI_STRIDE,
  66                 MPIC_GREG_SPURIOUS,
  67                 MPIC_GREG_TIMER_FREQ,
  68
  69                 MPIC_TIMER_BASE,
  70                 MPIC_TIMER_STRIDE,
  71                 MPIC_TIMER_CURRENT_CNT,
  72                 MPIC_TIMER_BASE_CNT,
  73                 MPIC_TIMER_VECTOR_PRI,
  74                 MPIC_TIMER_DESTINATION,
  75
  76                 MPIC_CPU_BASE,
  77                 MPIC_CPU_STRIDE,
  78                 MPIC_CPU_IPI_DISPATCH_0,
  79                 MPIC_CPU_IPI_DISPATCH_STRIDE,
  80                 MPIC_CPU_CURRENT_TASK_PRI,
  81                 MPIC_CPU_WHOAMI,
  82                 MPIC_CPU_INTACK,
  83                 MPIC_CPU_EOI,
  84
  85                 MPIC_IRQ_BASE,
  86                 MPIC_IRQ_STRIDE,
  87                 MPIC_IRQ_VECTOR_PRI,
  88                 MPIC_VECPRI_VECTOR_MASK,
  89                 MPIC_VECPRI_POLARITY_POSITIVE,
  90                 MPIC_VECPRI_POLARITY_NEGATIVE,
  91                 MPIC_VECPRI_SENSE_LEVEL,
  92                 MPIC_VECPRI_SENSE_EDGE,
  93                 MPIC_VECPRI_POLARITY_MASK,
  94                 MPIC_VECPRI_SENSE_MASK,
  95                 MPIC_IRQ_DESTINATION
  96         },
  97         [1] = { /* Tsi108/109 PIC */
  98                 TSI108_GREG_BASE,
  99                 TSI108_GREG_FEATURE_0,
 100                 TSI108_GREG_GLOBAL_CONF_0,
 101                 TSI108_GREG_VENDOR_ID,
 102                 TSI108_GREG_IPI_VECTOR_PRI_0,
 103                 TSI108_GREG_IPI_STRIDE,
 104                 TSI108_GREG_SPURIOUS,
 105                 TSI108_GREG_TIMER_FREQ,
 106
 107                 TSI108_TIMER_BASE,
 108                 TSI108_TIMER_STRIDE,
 109                 TSI108_TIMER_CURRENT_CNT,
 110                 TSI108_TIMER_BASE_CNT,
 111                 TSI108_TIMER_VECTOR_PRI,
 112                 TSI108_TIMER_DESTINATION,
 113
 114                 TSI108_CPU_BASE,
 115                 TSI108_CPU_STRIDE,
 116                 TSI108_CPU_IPI_DISPATCH_0,
 117                 TSI108_CPU_IPI_DISPATCH_STRIDE,
 118                 TSI108_CPU_CURRENT_TASK_PRI,
 119                 TSI108_CPU_WHOAMI,
 120                 TSI108_CPU_INTACK,
 121                 TSI108_CPU_EOI,
 122
 123                 TSI108_IRQ_BASE,
 124                 TSI108_IRQ_STRIDE,
 125                 TSI108_IRQ_VECTOR_PRI,
 126                 TSI108_VECPRI_VECTOR_MASK,
 127                 TSI108_VECPRI_POLARITY_POSITIVE,
 128                 TSI108_VECPRI_POLARITY_NEGATIVE,
 129                 TSI108_VECPRI_SENSE_LEVEL,
 130                 TSI108_VECPRI_SENSE_EDGE,
 131                 TSI108_VECPRI_POLARITY_MASK,
 132                 TSI108_VECPRI_SENSE_MASK,
 133                 TSI108_IRQ_DESTINATION
 134         },
 135 };
 136
 137 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 138
 139 #else /* CONFIG_MPIC_WEIRD */
 140
 141 #define MPIC_INFO(name) MPIC_##name
 142
 143 #endif /* CONFIG_MPIC_WEIRD */
 144
 145 /*
 146  * Register accessor functions
 147  */
 148
 149
 150 static inline u32 _mpic_read(enum mpic_reg_type type,
 151                              struct mpic_reg_bank *rb,
 152                              unsigned int reg)
 153 {
 154         switch(type) {
 155 #ifdef CONFIG_PPC_DCR
 156         case mpic_access_dcr:
 157                 return dcr_read(rb->dhost,
 158                                 rb->dbase + reg + rb->doff);
 159 #endif
 160         case mpic_access_mmio_be:
 161                 return in_be32(rb->base + (reg >> 2));
 162         case mpic_access_mmio_le:
 163         default:
 164                 return in_le32(rb->base + (reg >> 2));
 165         }
 166 }
 167
 168 static inline void _mpic_write(enum mpic_reg_type type,
 169                                struct mpic_reg_bank *rb,
 170                                unsigned int reg, u32 value)
 171 {
 172         switch(type) {
 173 #ifdef CONFIG_PPC_DCR
 174         case mpic_access_dcr:
 175                 return dcr_write(rb->dhost,
 176                                  rb->dbase + reg + rb->doff, value);
 177 #endif
 178         case mpic_access_mmio_be:
 179                 return out_be32(rb->base + (reg >> 2), value);
 180         case mpic_access_mmio_le:
 181         default:
 182                 return out_le32(rb->base + (reg >> 2), value);
 183         }
 184 }
 185
 186 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 187 {
 188         enum mpic_reg_type type = mpic->reg_type;
 189         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 190                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 191
 192         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 193                 type = mpic_access_mmio_be;
 194         return _mpic_read(type, &mpic->gregs, offset);
 195 }
 196
 197 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 198 {
 199         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 200                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 201
 202         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 203 }
 204
 205 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 206 {
 207         unsigned int cpu = 0;
 208
 209         if (mpic->flags & MPIC_PRIMARY)
 210                 cpu = hard_smp_processor_id();
 211         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 212 }
 213
 214 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 215 {
 216         unsigned int cpu = 0;
 217
 218         if (mpic->flags & MPIC_PRIMARY)
 219                 cpu = hard_smp_processor_id();
 220
 221         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 222 }
 223
 224 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 225 {
 226         unsigned int    isu = src_no >> mpic->isu_shift;
 227         unsigned int    idx = src_no & mpic->isu_mask;
 228
 229         return _mpic_read(mpic->reg_type, &mpic->isus[isu],
 230                           reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 231 }
 232
 233 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 234                                    unsigned int reg, u32 value)
 235 {
 236         unsigned int    isu = src_no >> mpic->isu_shift;
 237         unsigned int    idx = src_no & mpic->isu_mask;
 238
 239         _mpic_write(mpic->reg_type, &mpic->isus[isu],
 240                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 241 }
 242
 243 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 244 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 245 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 246 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 247 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 248 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 249 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 250 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 251
 252
 253 /*
 254  * Low level utility functions
 255  */
 256
 257
 258 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
 259                            struct mpic_reg_bank *rb, unsigned int offset,
 260                            unsigned int size)
 261 {
 262         rb->base = ioremap(phys_addr + offset, size);
 263         BUG_ON(rb->base == NULL);
 264 }
 265
 266 #ifdef CONFIG_PPC_DCR
 267 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
 268                           unsigned int offset, unsigned int size)
 269 {
 270         rb->dbase = mpic->dcr_base;
 271         rb->doff = offset;
 272         rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size);
 273         BUG_ON(!DCR_MAP_OK(rb->dhost));
 274 }
 275
 276 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
 277                             struct mpic_reg_bank *rb, unsigned int offset,
 278                             unsigned int size)
 279 {
 280         if (mpic->flags & MPIC_USES_DCR)
 281                 _mpic_map_dcr(mpic, rb, offset, size);
 282         else
 283                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 284 }
 285 #else /* CONFIG_PPC_DCR */
 286 #define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
 287 #endif /* !CONFIG_PPC_DCR */
 288
 289
 290
 291 /* Check if we have one of those nice broken MPICs with a flipped endian on
 292  * reads from IPI registers
 293  */
 294 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 295 {
 296         u32 r;
 297
 298         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 299         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 300
 301         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 302                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 303                 mpic->flags |= MPIC_BROKEN_IPI;
 304         }
 305 }
 306
 307 #ifdef CONFIG_MPIC_U3_HT_IRQS
 308
 309 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 310  * to force the edge setting on the MPIC and do the ack workaround.
 311  */
 312 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 313 {
 314         if (source >= 128 || !mpic->fixups)
 315                 return 0;
 316         return mpic->fixups[source].base != NULL;
 317 }
 318
 319
 320 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 321 {
 322         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 323
 324         if (fixup->applebase) {
 325                 unsigned int soff = (fixup->index >> 3) & ~3;
 326                 unsigned int mask = 1U << (fixup->index & 0x1f);
 327                 writel(mask, fixup->applebase + soff);
 328         } else {
 329                 spin_lock(&mpic->fixup_lock);
 330                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 331                 writel(fixup->data, fixup->base + 4);
 332                 spin_unlock(&mpic->fixup_lock);
 333         }
 334 }
 335
 336 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 337                                       unsigned int irqflags)
 338 {
 339         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 340         unsigned long flags;
 341         u32 tmp;
 342
 343         if (fixup->base == NULL)
 344                 return;
 345
 346         DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
 347             source, irqflags, fixup->index);
 348         spin_lock_irqsave(&mpic->fixup_lock, flags);
 349         /* Enable and configure */
 350         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 351         tmp = readl(fixup->base + 4);
 352         tmp &= ~(0x23U);
 353         if (irqflags & IRQ_LEVEL)
 354                 tmp |= 0x22;
 355         writel(tmp, fixup->base + 4);
 356         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 357
 358 #ifdef CONFIG_PM
 359         /* use the lowest bit inverted to the actual HW,
 360          * set if this fixup was enabled, clear otherwise */
 361         mpic->save_data[source].fixup_data = tmp | 1;
 362 #endif
 363 }
 364
 365 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
 366                                        unsigned int irqflags)
 367 {
 368         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 369         unsigned long flags;
 370         u32 tmp;
 371
 372         if (fixup->base == NULL)
 373                 return;
 374
 375         DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
 376
 377         /* Disable */
 378         spin_lock_irqsave(&mpic->fixup_lock, flags);
 379         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 380         tmp = readl(fixup->base + 4);
 381         tmp |= 1;
 382         writel(tmp, fixup->base + 4);
 383         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 384
 385 #ifdef CONFIG_PM
 386         /* use the lowest bit inverted to the actual HW,
 387          * set if this fixup was enabled, clear otherwise */
 388         mpic->save_data[source].fixup_data = tmp & ~1;
 389 #endif
 390 }
 391
 392 #ifdef CONFIG_PCI_MSI
 393 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 394                                     unsigned int devfn)
 395 {
 396         u8 __iomem *base;
 397         u8 pos, flags;
 398         u64 addr = 0;
 399
 400         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 401              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 402                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 403                 if (id == PCI_CAP_ID_HT) {
 404                         id = readb(devbase + pos + 3);
 405                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 406                                 break;
 407                 }
 408         }
 409
 410         if (pos == 0)
 411                 return;
 412
 413         base = devbase + pos;
 414
 415         flags = readb(base + HT_MSI_FLAGS);
 416         if (!(flags & HT_MSI_FLAGS_FIXED)) {
 417                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 418                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 419         }
 420
 421         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
 422                 PCI_SLOT(devfn), PCI_FUNC(devfn),
 423                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 424
 425         if (!(flags & HT_MSI_FLAGS_ENABLE))
 426                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 427 }
 428 #else
 429 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 430                                     unsigned int devfn)
 431 {
 432         return;
 433 }
 434 #endif
 435
 436 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 437                                     unsigned int devfn, u32 vdid)
 438 {
 439         int i, irq, n;
 440         u8 __iomem *base;
 441         u32 tmp;
 442         u8 pos;
 443
 444         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 445              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 446                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 447                 if (id == PCI_CAP_ID_HT) {
 448                         id = readb(devbase + pos + 3);
 449                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 450                                 break;
 451                 }
 452         }
 453         if (pos == 0)
 454                 return;
 455
 456         base = devbase + pos;
 457         writeb(0x01, base + 2);
 458         n = (readl(base + 4) >> 16) & 0xff;
 459
 460         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 461                " has %d irqs\n",
 462                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 463
 464         for (i = 0; i <= n; i++) {
 465                 writeb(0x10 + 2 * i, base + 2);
 466                 tmp = readl(base + 4);
 467                 irq = (tmp >> 16) & 0xff;
 468                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 469                 /* mask it , will be unmasked later */
 470                 tmp |= 0x1;
 471                 writel(tmp, base + 4);
 472                 mpic->fixups[irq].index = i;
 473                 mpic->fixups[irq].base = base;
 474                 /* Apple HT PIC has a non-standard way of doing EOIs */
 475                 if ((vdid & 0xffff) == 0x106b)
 476                         mpic->fixups[irq].applebase = devbase + 0x60;
 477                 else
 478                         mpic->fixups[irq].applebase = NULL;
 479                 writeb(0x11 + 2 * i, base + 2);
 480                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 481         }
 482 }
 483
 484
 485 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 486 {
 487         unsigned int devfn;
 488         u8 __iomem *cfgspace;
 489
 490         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 491
 492         /* Allocate fixups array */
 493         mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
 494         BUG_ON(mpic->fixups == NULL);
 495         memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
 496
 497         /* Init spinlock */
 498         spin_lock_init(&mpic->fixup_lock);
 499
 500         /* Map U3 config space. We assume all IO-APICs are on the primary bus
 501          * so we only need to map 64kB.
 502          */
 503         cfgspace = ioremap(0xf2000000, 0x10000);
 504         BUG_ON(cfgspace == NULL);
 505
 506         /* Now we scan all slots. We do a very quick scan, we read the header
 507          * type, vendor ID and device ID only, that's plenty enough
 508          */
 509         for (devfn = 0; devfn < 0x100; devfn++) {
 510                 u8 __iomem *devbase = cfgspace + (devfn << 8);
 511                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 512                 u32 l = readl(devbase + PCI_VENDOR_ID);
 513                 u16 s;
 514
 515                 DBG("devfn %x, l: %x\n", devfn, l);
 516
 517                 /* If no device, skip */
 518                 if (l == 0xffffffff || l == 0x00000000 ||
 519                     l == 0x0000ffff || l == 0xffff0000)
 520                         goto next;
 521                 /* Check if is supports capability lists */
 522                 s = readw(devbase + PCI_STATUS);
 523                 if (!(s & PCI_STATUS_CAP_LIST))
 524                         goto next;
 525
 526                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
 527                 mpic_scan_ht_msi(mpic, devbase, devfn);
 528
 529         next:
 530                 /* next device, if function 0 */
 531                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 532                         devfn += 7;
 533         }
 534 }
 535
 536 #else /* CONFIG_MPIC_U3_HT_IRQS */
 537
 538 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 539 {
 540         return 0;
 541 }
 542
 543 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 544 {
 545 }
 546
 547 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 548
 549
 550 #define mpic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 551
 552 /* Find an mpic associated with a given linux interrupt */
 553 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
 554 {
 555         unsigned int src = mpic_irq_to_hw(irq);
 556         struct mpic *mpic;
 557
 558         if (irq < NUM_ISA_INTERRUPTS)
 559                 return NULL;
 560
 561         mpic = irq_desc[irq].chip_data;
 562
 563         if (is_ipi)
 564                 *is_ipi = (src >= mpic->ipi_vecs[0] &&
 565                            src <= mpic->ipi_vecs[3]);
 566
 567         return mpic;
 568 }
 569
 570 /* Convert a cpu mask from logical to physical cpu numbers. */
 571 static inline u32 mpic_physmask(u32 cpumask)
 572 {
 573         int i;
 574         u32 mask = 0;
 575
 576         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 577                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 578         return mask;
 579 }
 580
 581 #ifdef CONFIG_SMP
 582 /* Get the mpic structure from the IPI number */
 583 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
 584 {
 585         return irq_desc[ipi].chip_data;
 586 }
 587 #endif
 588
 589 /* Get the mpic structure from the irq number */
 590 static inline struct mpic * mpic_from_irq(unsigned int irq)
 591 {
 592         return irq_desc[irq].chip_data;
 593 }
 594
 595 /* Send an EOI */
 596 static inline void mpic_eoi(struct mpic *mpic)
 597 {
 598         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 599         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 600 }
 601
 602 #ifdef CONFIG_SMP
 603 static irqreturn_t mpic_ipi_action(int irq, void *dev_id)
 604 {
 605         struct mpic *mpic;
 606
 607         mpic = mpic_find(irq, NULL);
 608         smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]);
 609
 610         return IRQ_HANDLED;
 611 }
 612 #endif /* CONFIG_SMP */
 613
 614 /*
 615  * Linux descriptor level callbacks
 616  */
 617
 618
 619 static void mpic_unmask_irq(unsigned int irq)
 620 {
 621         unsigned int loops = 100000;
 622         struct mpic *mpic = mpic_from_irq(irq);
 623         unsigned int src = mpic_irq_to_hw(irq);
 624
 625         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 626
 627         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 628                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 629                        ~MPIC_VECPRI_MASK);
 630         /* make sure mask gets to controller before we return to user */
 631         do {
 632                 if (!loops--) {
 633                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 634                         break;
 635                 }
 636         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 637 }
 638
 639 static void mpic_mask_irq(unsigned int irq)
 640 {
 641         unsigned int loops = 100000;
 642         struct mpic *mpic = mpic_from_irq(irq);
 643         unsigned int src = mpic_irq_to_hw(irq);
 644
 645         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 646
 647         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 648                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 649                        MPIC_VECPRI_MASK);
 650
 651         /* make sure mask gets to controller before we return to user */
 652         do {
 653                 if (!loops--) {
 654                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 655                         break;
 656                 }
 657         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 658 }
 659
 660 static void mpic_end_irq(unsigned int irq)
 661 {
 662         struct mpic *mpic = mpic_from_irq(irq);
 663
 664 #ifdef DEBUG_IRQ
 665         DBG("%s: end_irq: %d\n", mpic->name, irq);
 666 #endif
 667         /* We always EOI on end_irq() even for edge interrupts since that
 668          * should only lower the priority, the MPIC should have properly
 669          * latched another edge interrupt coming in anyway
 670          */
 671
 672         mpic_eoi(mpic);
 673 }
 674
 675 #ifdef CONFIG_MPIC_U3_HT_IRQS
 676
 677 static void mpic_unmask_ht_irq(unsigned int irq)
 678 {
 679         struct mpic *mpic = mpic_from_irq(irq);
 680         unsigned int src = mpic_irq_to_hw(irq);
 681
 682         mpic_unmask_irq(irq);
 683
 684         if (irq_desc[irq].status & IRQ_LEVEL)
 685                 mpic_ht_end_irq(mpic, src);
 686 }
 687
 688 static unsigned int mpic_startup_ht_irq(unsigned int irq)
 689 {
 690         struct mpic *mpic = mpic_from_irq(irq);
 691         unsigned int src = mpic_irq_to_hw(irq);
 692
 693         mpic_unmask_irq(irq);
 694         mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
 695
 696         return 0;
 697 }
 698
 699 static void mpic_shutdown_ht_irq(unsigned int irq)
 700 {
 701         struct mpic *mpic = mpic_from_irq(irq);
 702         unsigned int src = mpic_irq_to_hw(irq);
 703
 704         mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
 705         mpic_mask_irq(irq);
 706 }
 707
 708 static void mpic_end_ht_irq(unsigned int irq)
 709 {
 710         struct mpic *mpic = mpic_from_irq(irq);
 711         unsigned int src = mpic_irq_to_hw(irq);
 712
 713 #ifdef DEBUG_IRQ
 714         DBG("%s: end_irq: %d\n", mpic->name, irq);
 715 #endif
 716         /* We always EOI on end_irq() even for edge interrupts since that
 717          * should only lower the priority, the MPIC should have properly
 718          * latched another edge interrupt coming in anyway
 719          */
 720
 721         if (irq_desc[irq].status & IRQ_LEVEL)
 722                 mpic_ht_end_irq(mpic, src);
 723         mpic_eoi(mpic);
 724 }
 725 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 726
 727 #ifdef CONFIG_SMP
 728
 729 static void mpic_unmask_ipi(unsigned int irq)
 730 {
 731         struct mpic *mpic = mpic_from_ipi(irq);
 732         unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
 733
 734         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
 735         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 736 }
 737
 738 static void mpic_mask_ipi(unsigned int irq)
 739 {
 740         /* NEVER disable an IPI... that's just plain wrong! */
 741 }
 742
 743 static void mpic_end_ipi(unsigned int irq)
 744 {
 745         struct mpic *mpic = mpic_from_ipi(irq);
 746
 747         /*
 748          * IPIs are marked IRQ_PER_CPU. This has the side effect of
 749          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 750          * applying to them. We EOI them late to avoid re-entering.
 751          * We mark IPI's with IRQF_DISABLED as they must run with
 752          * irqs disabled.
 753          */
 754         mpic_eoi(mpic);
 755 }
 756
 757 #endif /* CONFIG_SMP */
 758
 759 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
 760 {
 761         struct mpic *mpic = mpic_from_irq(irq);
 762         unsigned int src = mpic_irq_to_hw(irq);
 763
 764         cpumask_t tmp;
 765
 766         cpus_and(tmp, cpumask, cpu_online_map);
 767
 768         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 769                        mpic_physmask(cpus_addr(tmp)[0]));
 770 }
 771
 772 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 773 {
 774         /* Now convert sense value */
 775         switch(type & IRQ_TYPE_SENSE_MASK) {
 776         case IRQ_TYPE_EDGE_RISING:
 777                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 778                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 779         case IRQ_TYPE_EDGE_FALLING:
 780         case IRQ_TYPE_EDGE_BOTH:
 781                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 782                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 783         case IRQ_TYPE_LEVEL_HIGH:
 784                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 785                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 786         case IRQ_TYPE_LEVEL_LOW:
 787         default:
 788                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 789                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 790         }
 791 }
 792
 793 static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
 794 {
 795         struct mpic *mpic = mpic_from_irq(virq);
 796         unsigned int src = mpic_irq_to_hw(virq);
 797         struct irq_desc *desc = get_irq_desc(virq);
 798         unsigned int vecpri, vold, vnew;
 799
 800         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 801             mpic, virq, src, flow_type);
 802
 803         if (src >= mpic->irq_count)
 804                 return -EINVAL;
 805
 806         if (flow_type == IRQ_TYPE_NONE)
 807                 if (mpic->senses && src < mpic->senses_count)
 808                         flow_type = mpic->senses[src];
 809         if (flow_type == IRQ_TYPE_NONE)
 810                 flow_type = IRQ_TYPE_LEVEL_LOW;
 811
 812         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 813         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 814         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 815                 desc->status |= IRQ_LEVEL;
 816
 817         if (mpic_is_ht_interrupt(mpic, src))
 818                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 819                         MPIC_VECPRI_SENSE_EDGE;
 820         else
 821                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 822
 823         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 824         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 825                         MPIC_INFO(VECPRI_SENSE_MASK));
 826         vnew |= vecpri;
 827         if (vold != vnew)
 828                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 829
 830         return 0;
 831 }
 832
 833 static struct irq_chip mpic_irq_chip = {
 834         .mask           = mpic_mask_irq,
 835         .unmask         = mpic_unmask_irq,
 836         .eoi            = mpic_end_irq,
 837         .set_type       = mpic_set_irq_type,
 838 };
 839
 840 #ifdef CONFIG_SMP
 841 static struct irq_chip mpic_ipi_chip = {
 842         .mask           = mpic_mask_ipi,
 843         .unmask         = mpic_unmask_ipi,
 844         .eoi            = mpic_end_ipi,
 845 };
 846 #endif /* CONFIG_SMP */
 847
 848 #ifdef CONFIG_MPIC_U3_HT_IRQS
 849 static struct irq_chip mpic_irq_ht_chip = {
 850         .startup        = mpic_startup_ht_irq,
 851         .shutdown       = mpic_shutdown_ht_irq,
 852         .mask           = mpic_mask_irq,
 853         .unmask         = mpic_unmask_ht_irq,
 854         .eoi            = mpic_end_ht_irq,
 855         .set_type       = mpic_set_irq_type,
 856 };
 857 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 858
 859
 860 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 861 {
 862         struct mpic *mpic = h->host_data;
 863
 864         /* Exact match, unless mpic node is NULL */
 865         return mpic->of_node == NULL || mpic->of_node == node;
 866 }
 867
 868 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 869                          irq_hw_number_t hw)
 870 {
 871         struct mpic *mpic = h->host_data;
 872         struct irq_chip *chip;
 873
 874         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 875
 876         if (hw == mpic->spurious_vec)
 877                 return -EINVAL;
 878
 879 #ifdef CONFIG_SMP
 880         else if (hw >= mpic->ipi_vecs[0]) {
 881                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 882
 883                 DBG("mpic: mapping as IPI\n");
 884                 set_irq_chip_data(virq, mpic);
 885                 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
 886                                          handle_percpu_irq);
 887                 return 0;
 888         }
 889 #endif /* CONFIG_SMP */
 890
 891         if (hw >= mpic->irq_count)
 892                 return -EINVAL;
 893
 894         /* Default chip */
 895         chip = &mpic->hc_irq;
 896
 897 #ifdef CONFIG_MPIC_U3_HT_IRQS
 898         /* Check for HT interrupts, override vecpri */
 899         if (mpic_is_ht_interrupt(mpic, hw))
 900                 chip = &mpic->hc_ht_irq;
 901 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 902
 903         DBG("mpic: mapping to irq chip @%p\n", chip);
 904
 905         set_irq_chip_data(virq, mpic);
 906         set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
 907
 908         /* Set default irq type */
 909         set_irq_type(virq, IRQ_TYPE_NONE);
 910
 911         return 0;
 912 }
 913
 914 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
 915                            u32 *intspec, unsigned int intsize,
 916                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 917
 918 {
 919         static unsigned char map_mpic_senses[4] = {
 920                 IRQ_TYPE_EDGE_RISING,
 921                 IRQ_TYPE_LEVEL_LOW,
 922                 IRQ_TYPE_LEVEL_HIGH,
 923                 IRQ_TYPE_EDGE_FALLING,
 924         };
 925
 926         *out_hwirq = intspec[0];
 927         if (intsize > 1) {
 928                 u32 mask = 0x3;
 929
 930                 /* Apple invented a new race of encoding on machines with
 931                  * an HT APIC. They encode, among others, the index within
 932                  * the HT APIC. We don't care about it here since thankfully,
 933                  * it appears that they have the APIC already properly
 934                  * configured, and thus our current fixup code that reads the
 935                  * APIC config works fine. However, we still need to mask out
 936                  * bits in the specifier to make sure we only get bit 0 which
 937                  * is the level/edge bit (the only sense bit exposed by Apple),
 938                  * as their bit 1 means something else.
 939                  */
 940                 if (machine_is(powermac))
 941                         mask = 0x1;
 942                 *out_flags = map_mpic_senses[intspec[1] & mask];
 943         } else
 944                 *out_flags = IRQ_TYPE_NONE;
 945
 946         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
 947             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
 948
 949         return 0;
 950 }
 951
 952 static struct irq_host_ops mpic_host_ops = {
 953         .match = mpic_host_match,
 954         .map = mpic_host_map,
 955         .xlate = mpic_host_xlate,
 956 };
 957
 958 /*
 959  * Exported functions
 960  */
 961
 962 struct mpic * __init mpic_alloc(struct device_node *node,
 963                                 phys_addr_t phys_addr,
 964                                 unsigned int flags,
 965                                 unsigned int isu_size,
 966                                 unsigned int irq_count,
 967                                 const char *name)
 968 {
 969         struct mpic     *mpic;
 970         u32             reg;
 971         const char      *vers;
 972         int             i;
 973         int             intvec_top;
 974         u64             paddr = phys_addr;
 975
 976         mpic = alloc_bootmem(sizeof(struct mpic));
 977         if (mpic == NULL)
 978                 return NULL;
 979
 980         memset(mpic, 0, sizeof(struct mpic));
 981         mpic->name = name;
 982         mpic->of_node = of_node_get(node);
 983
 984         mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, isu_size,
 985                                        &mpic_host_ops,
 986                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
 987         if (mpic->irqhost == NULL) {
 988                 of_node_put(node);
 989                 return NULL;
 990         }
 991
 992         mpic->irqhost->host_data = mpic;
 993         mpic->hc_irq = mpic_irq_chip;
 994         mpic->hc_irq.typename = name;
 995         if (flags & MPIC_PRIMARY)
 996                 mpic->hc_irq.set_affinity = mpic_set_affinity;
 997 #ifdef CONFIG_MPIC_U3_HT_IRQS
 998         mpic->hc_ht_irq = mpic_irq_ht_chip;
 999         mpic->hc_ht_irq.typename = name;
1000         if (flags & MPIC_PRIMARY)
1001                 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1002 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1003
1004 #ifdef CONFIG_SMP
1005         mpic->hc_ipi = mpic_ipi_chip;
1006         mpic->hc_ipi.typename = name;
1007 #endif /* CONFIG_SMP */
1008
1009         mpic->flags = flags;
1010         mpic->isu_size = isu_size;
1011         mpic->irq_count = irq_count;
1012         mpic->num_sources = 0; /* so far */
1013
1014         if (flags & MPIC_LARGE_VECTORS)
1015                 intvec_top = 2047;
1016         else
1017                 intvec_top = 255;
1018
1019         mpic->timer_vecs[0] = intvec_top - 8;
1020         mpic->timer_vecs[1] = intvec_top - 7;
1021         mpic->timer_vecs[2] = intvec_top - 6;
1022         mpic->timer_vecs[3] = intvec_top - 5;
1023         mpic->ipi_vecs[0]   = intvec_top - 4;
1024         mpic->ipi_vecs[1]   = intvec_top - 3;
1025         mpic->ipi_vecs[2]   = intvec_top - 2;
1026         mpic->ipi_vecs[3]   = intvec_top - 1;
1027         mpic->spurious_vec  = intvec_top;
1028
1029         /* Check for "big-endian" in device-tree */
1030         if (node && of_get_property(node, "big-endian", NULL) != NULL)
1031                 mpic->flags |= MPIC_BIG_ENDIAN;
1032
1033
1034 #ifdef CONFIG_MPIC_WEIRD
1035         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1036 #endif
1037
1038         /* default register type */
1039         mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1040                 mpic_access_mmio_be : mpic_access_mmio_le;
1041
1042         /* If no physical address is passed in, a device-node is mandatory */
1043         BUG_ON(paddr == 0 && node == NULL);
1044
1045         /* If no physical address passed in, check if it's dcr based */
1046         if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL)
1047                 mpic->flags |= MPIC_USES_DCR;
1048
1049 #ifdef CONFIG_PPC_DCR
1050         if (mpic->flags & MPIC_USES_DCR) {
1051                 const u32 *dbasep;
1052                 dbasep = of_get_property(node, "dcr-reg", NULL);
1053                 BUG_ON(dbasep == NULL);
1054                 mpic->dcr_base = *dbasep;
1055                 mpic->reg_type = mpic_access_dcr;
1056         }
1057 #else
1058         BUG_ON (mpic->flags & MPIC_USES_DCR);
1059 #endif /* CONFIG_PPC_DCR */
1060
1061         /* If the MPIC is not DCR based, and no physical address was passed
1062          * in, try to obtain one
1063          */
1064         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1065                 const u32 *reg;
1066                 reg = of_get_property(node, "reg", NULL);
1067                 BUG_ON(reg == NULL);
1068                 paddr = of_translate_address(node, reg);
1069                 BUG_ON(paddr == OF_BAD_ADDR);
1070         }
1071
1072         /* Map the global registers */
1073         mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1074         mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1075
1076         /* Reset */
1077         if (flags & MPIC_WANTS_RESET) {
1078                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1079                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1080                            | MPIC_GREG_GCONF_RESET);
1081                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1082                        & MPIC_GREG_GCONF_RESET)
1083                         mb();
1084         }
1085
1086         /* Read feature register, calculate num CPUs and, for non-ISU
1087          * MPICs, num sources as well. On ISU MPICs, sources are counted
1088          * as ISUs are added
1089          */
1090         reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1091         mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1092                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1093         if (isu_size == 0)
1094                 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1095                                      >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1096
1097         /* Map the per-CPU registers */
1098         for (i = 0; i < mpic->num_cpus; i++) {
1099                 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1100                          MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1101                          0x1000);
1102         }
1103
1104         /* Initialize main ISU if none provided */
1105         if (mpic->isu_size == 0) {
1106                 mpic->isu_size = mpic->num_sources;
1107                 mpic_map(mpic, paddr, &mpic->isus[0],
1108                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1109         }
1110         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1111         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1112
1113         /* Display version */
1114         switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
1115         case 1:
1116                 vers = "1.0";
1117                 break;
1118         case 2:
1119                 vers = "1.2";
1120                 break;
1121         case 3:
1122                 vers = "1.3";
1123                 break;
1124         default:
1125                 vers = "<unknown>";
1126                 break;
1127         }
1128         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1129                " max %d CPUs\n",
1130                name, vers, (unsigned long long)paddr, mpic->num_cpus);
1131         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1132                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1133
1134         mpic->next = mpics;
1135         mpics = mpic;
1136
1137         if (flags & MPIC_PRIMARY) {
1138                 mpic_primary = mpic;
1139                 irq_set_default_host(mpic->irqhost);
1140         }
1141
1142         return mpic;
1143 }
1144
1145 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1146                             phys_addr_t paddr)
1147 {
1148         unsigned int isu_first = isu_num * mpic->isu_size;
1149
1150         BUG_ON(isu_num >= MPIC_MAX_ISU);
1151
1152         mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1153                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1154         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1155                 mpic->num_sources = isu_first + mpic->isu_size;
1156 }
1157
1158 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1159 {
1160         mpic->senses = senses;
1161         mpic->senses_count = count;
1162 }
1163
1164 void __init mpic_init(struct mpic *mpic)
1165 {
1166         int i;
1167
1168         BUG_ON(mpic->num_sources == 0);
1169
1170         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1171
1172         /* Set current processor priority to max */
1173         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1174
1175         /* Initialize timers: just disable them all */
1176         for (i = 0; i < 4; i++) {
1177                 mpic_write(mpic->tmregs,
1178                            i * MPIC_INFO(TIMER_STRIDE) +
1179                            MPIC_INFO(TIMER_DESTINATION), 0);
1180                 mpic_write(mpic->tmregs,
1181                            i * MPIC_INFO(TIMER_STRIDE) +
1182                            MPIC_INFO(TIMER_VECTOR_PRI),
1183                            MPIC_VECPRI_MASK |
1184                            (mpic->timer_vecs[0] + i));
1185         }
1186
1187         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1188         mpic_test_broken_ipi(mpic);
1189         for (i = 0; i < 4; i++) {
1190                 mpic_ipi_write(i,
1191                                MPIC_VECPRI_MASK |
1192                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1193                                (mpic->ipi_vecs[0] + i));
1194         }
1195
1196         /* Initialize interrupt sources */
1197         if (mpic->irq_count == 0)
1198                 mpic->irq_count = mpic->num_sources;
1199
1200         /* Do the HT PIC fixups on U3 broken mpic */
1201         DBG("MPIC flags: %x\n", mpic->flags);
1202         if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY))
1203                 mpic_scan_ht_pics(mpic);
1204
1205         for (i = 0; i < mpic->num_sources; i++) {
1206                 /* start with vector = source number, and masked */
1207                 u32 vecpri = MPIC_VECPRI_MASK | i |
1208                         (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1209
1210                 /* init hw */
1211                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1212                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1213                                1 << hard_smp_processor_id());
1214         }
1215
1216         /* Init spurious vector */
1217         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1218
1219         /* Disable 8259 passthrough, if supported */
1220         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1221                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1222                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1223                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1224
1225         /* Set current processor priority to 0 */
1226         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1227
1228 #ifdef CONFIG_PM
1229         /* allocate memory to save mpic state */
1230         mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1231         BUG_ON(mpic->save_data == NULL);
1232 #endif
1233 }
1234
1235 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1236 {
1237         u32 v;
1238
1239         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1240         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1241         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1242         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1243 }
1244
1245 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1246 {
1247         unsigned long flags;
1248         u32 v;
1249
1250         spin_lock_irqsave(&mpic_lock, flags);
1251         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1252         if (enable)
1253                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1254         else
1255                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1256         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1257         spin_unlock_irqrestore(&mpic_lock, flags);
1258 }
1259
1260 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1261 {
1262         int is_ipi;
1263         struct mpic *mpic = mpic_find(irq, &is_ipi);
1264         unsigned int src = mpic_irq_to_hw(irq);
1265         unsigned long flags;
1266         u32 reg;
1267
1268         spin_lock_irqsave(&mpic_lock, flags);
1269         if (is_ipi) {
1270                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1271                         ~MPIC_VECPRI_PRIORITY_MASK;
1272                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1273                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1274         } else {
1275                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1276                         & ~MPIC_VECPRI_PRIORITY_MASK;
1277                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1278                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1279         }
1280         spin_unlock_irqrestore(&mpic_lock, flags);
1281 }
1282
1283 unsigned int mpic_irq_get_priority(unsigned int irq)
1284 {
1285         int is_ipi;
1286         struct mpic *mpic = mpic_find(irq, &is_ipi);
1287         unsigned int src = mpic_irq_to_hw(irq);
1288         unsigned long flags;
1289         u32 reg;
1290
1291         spin_lock_irqsave(&mpic_lock, flags);
1292         if (is_ipi)
1293                 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1294         else
1295                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1296         spin_unlock_irqrestore(&mpic_lock, flags);
1297         return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1298 }
1299
1300 void mpic_setup_this_cpu(void)
1301 {
1302 #ifdef CONFIG_SMP
1303         struct mpic *mpic = mpic_primary;
1304         unsigned long flags;
1305         u32 msk = 1 << hard_smp_processor_id();
1306         unsigned int i;
1307
1308         BUG_ON(mpic == NULL);
1309
1310         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1311
1312         spin_lock_irqsave(&mpic_lock, flags);
1313
1314         /* let the mpic know we want intrs. default affinity is 0xffffffff
1315          * until changed via /proc. That's how it's done on x86. If we want
1316          * it differently, then we should make sure we also change the default
1317          * values of irq_desc[].affinity in irq.c.
1318          */
1319         if (distribute_irqs) {
1320                 for (i = 0; i < mpic->num_sources ; i++)
1321                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1322                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1323         }
1324
1325         /* Set current processor priority to 0 */
1326         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1327
1328         spin_unlock_irqrestore(&mpic_lock, flags);
1329 #endif /* CONFIG_SMP */
1330 }
1331
1332 int mpic_cpu_get_priority(void)
1333 {
1334         struct mpic *mpic = mpic_primary;
1335
1336         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1337 }
1338
1339 void mpic_cpu_set_priority(int prio)
1340 {
1341         struct mpic *mpic = mpic_primary;
1342
1343         prio &= MPIC_CPU_TASKPRI_MASK;
1344         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1345 }
1346
1347 /*
1348  * XXX: someone who knows mpic should check this.
1349  * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1350  * or can we reset the mpic in the new kernel?
1351  */
1352 void mpic_teardown_this_cpu(int secondary)
1353 {
1354         struct mpic *mpic = mpic_primary;
1355         unsigned long flags;
1356         u32 msk = 1 << hard_smp_processor_id();
1357         unsigned int i;
1358
1359         BUG_ON(mpic == NULL);
1360
1361         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1362         spin_lock_irqsave(&mpic_lock, flags);
1363
1364         /* let the mpic know we don't want intrs.  */
1365         for (i = 0; i < mpic->num_sources ; i++)
1366                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1367                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1368
1369         /* Set current processor priority to max */
1370         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1371
1372         spin_unlock_irqrestore(&mpic_lock, flags);
1373 }
1374
1375
1376 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1377 {
1378         struct mpic *mpic = mpic_primary;
1379
1380         BUG_ON(mpic == NULL);
1381
1382 #ifdef DEBUG_IPI
1383         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1384 #endif
1385
1386         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1387                        ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1388                        mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1389 }
1390
1391 unsigned int mpic_get_one_irq(struct mpic *mpic)
1392 {
1393         u32 src;
1394
1395         src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1396 #ifdef DEBUG_LOW
1397         DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1398 #endif
1399         if (unlikely(src == mpic->spurious_vec)) {
1400                 if (mpic->flags & MPIC_SPV_EOI)
1401                         mpic_eoi(mpic);
1402                 return NO_IRQ;
1403         }
1404         return irq_linear_revmap(mpic->irqhost, src);
1405 }
1406
1407 unsigned int mpic_get_irq(void)
1408 {
1409         struct mpic *mpic = mpic_primary;
1410
1411         BUG_ON(mpic == NULL);
1412
1413         return mpic_get_one_irq(mpic);
1414 }
1415
1416
1417 #ifdef CONFIG_SMP
1418 void mpic_request_ipis(void)
1419 {
1420         struct mpic *mpic = mpic_primary;
1421         int i;
1422         static char *ipi_names[] = {
1423                 "IPI0 (call function)",
1424                 "IPI1 (reschedule)",
1425                 "IPI2 (unused)",
1426                 "IPI3 (debugger break)",
1427         };
1428         BUG_ON(mpic == NULL);
1429
1430         printk(KERN_INFO "mpic: requesting IPIs ... \n");
1431
1432         for (i = 0; i < 4; i++) {
1433                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1434                                                        mpic->ipi_vecs[0] + i);
1435                 if (vipi == NO_IRQ) {
1436                         printk(KERN_ERR "Failed to map IPI %d\n", i);
1437                         break;
1438                 }
1439                 request_irq(vipi, mpic_ipi_action, IRQF_DISABLED|IRQF_PERCPU,
1440                             ipi_names[i], mpic);
1441         }
1442 }
1443
1444 void smp_mpic_message_pass(int target, int msg)
1445 {
1446         /* make sure we're sending something that translates to an IPI */
1447         if ((unsigned int)msg > 3) {
1448                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1449                        smp_processor_id(), msg);
1450                 return;
1451         }
1452         switch (target) {
1453         case MSG_ALL:
1454                 mpic_send_ipi(msg, 0xffffffff);
1455                 break;
1456         case MSG_ALL_BUT_SELF:
1457                 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1458                 break;
1459         default:
1460                 mpic_send_ipi(msg, 1 << target);
1461                 break;
1462         }
1463 }
1464
1465 int __init smp_mpic_probe(void)
1466 {
1467         int nr_cpus;
1468
1469         DBG("smp_mpic_probe()...\n");
1470
1471         nr_cpus = cpus_weight(cpu_possible_map);
1472
1473         DBG("nr_cpus: %d\n", nr_cpus);
1474
1475         if (nr_cpus > 1)
1476                 mpic_request_ipis();
1477
1478         return nr_cpus;
1479 }
1480
1481 void __devinit smp_mpic_setup_cpu(int cpu)
1482 {
1483         mpic_setup_this_cpu();
1484 }
1485 #endif /* CONFIG_SMP */
1486
1487 #ifdef CONFIG_PM
1488 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1489 {
1490         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1491         int i;
1492
1493         for (i = 0; i < mpic->num_sources; i++) {
1494                 mpic->save_data[i].vecprio =
1495                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1496                 mpic->save_data[i].dest =
1497                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1498         }
1499
1500         return 0;
1501 }
1502
1503 static int mpic_resume(struct sys_device *dev)
1504 {
1505         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1506         int i;
1507
1508         for (i = 0; i < mpic->num_sources; i++) {
1509                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1510                                mpic->save_data[i].vecprio);
1511                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1512                                mpic->save_data[i].dest);
1513
1514 #ifdef CONFIG_MPIC_U3_HT_IRQS
1515         {
1516                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1517
1518                 if (fixup->base) {
1519                         /* we use the lowest bit in an inverted meaning */
1520                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1521                                 continue;
1522
1523                         /* Enable and configure */
1524                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1525
1526                         writel(mpic->save_data[i].fixup_data & ~1,
1527                                fixup->base + 4);
1528                 }
1529         }
1530 #endif
1531         } /* end for loop */
1532
1533         return 0;
1534 }
1535 #endif
1536
1537 static struct sysdev_class mpic_sysclass = {
1538 #ifdef CONFIG_PM
1539         .resume = mpic_resume,
1540         .suspend = mpic_suspend,
1541 #endif
1542         set_kset_name("mpic"),
1543 };
1544
1545 static int mpic_init_sys(void)
1546 {
1547         struct mpic *mpic = mpics;
1548         int error, id = 0;
1549
1550         error = sysdev_class_register(&mpic_sysclass);
1551
1552         while (mpic && !error) {
1553                 mpic->sysdev.cls = &mpic_sysclass;
1554                 mpic->sysdev.id = id++;
1555                 error = sysdev_register(&mpic->sysdev);
1556                 mpic = mpic->next;
1557         }
1558         return error;
1559 }
1560
1561 device_initcall(mpic_init_sys);