2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
15 #include <linux/config.h>
16 #include <linux/sys.h>
17 #include <asm/unistd.h>
18 #include <asm/errno.h>
19 #include <asm/processor.h>
21 #include <asm/cache.h>
22 #include <asm/cputable.h>
24 #include <asm/ppc_asm.h>
25 #include <asm/thread_info.h>
26 #include <asm/asm-offsets.h>
39 * Returns (address we're running at) - (address we were linked at)
40 * for use before the text and data are mapped to KERNELBASE.
53 * add_reloc_offset(x) returns x + reloc_offset().
55 _GLOBAL(add_reloc_offset)
67 * sub_reloc_offset(x) returns x - reloc_offset().
69 _GLOBAL(sub_reloc_offset)
81 * reloc_got2 runs through the .got2 section adding an offset
86 lis r7,__got2_start@ha
87 addi r7,r7,__got2_start@l
89 addi r8,r8,__got2_end@l
110 * called with r3 = data offset and r4 = CPU number
113 _GLOBAL(identify_cpu)
114 addis r8,r3,cpu_specs@ha
115 addi r8,r8,cpu_specs@l
118 lwz r5,CPU_SPEC_PVR_MASK(r8)
120 lwz r6,CPU_SPEC_PVR_VALUE(r8)
123 addi r8,r8,CPU_SPEC_ENTRY_SIZE
126 addis r6,r3,cur_cpu_spec@ha
127 addi r6,r6,cur_cpu_spec@l
134 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
135 * and writes nop's over sections of code that don't apply for this cpu.
136 * r3 = data offset (not changed)
138 _GLOBAL(do_cpu_ftr_fixups)
139 /* Get CPU 0 features */
140 addis r6,r3,cur_cpu_spec@ha
141 addi r6,r6,cur_cpu_spec@l
144 lwz r4,CPU_SPEC_FEATURES(r4)
146 /* Get the fixup table */
147 addis r6,r3,__start___ftr_fixup@ha
148 addi r6,r6,__start___ftr_fixup@l
149 addis r7,r3,__stop___ftr_fixup@ha
150 addi r7,r7,__stop___ftr_fixup@l
156 lwz r8,-16(r6) /* mask */
158 lwz r9,-12(r6) /* value */
161 lwz r8,-8(r6) /* section begin */
162 lwz r9,-4(r6) /* section end */
165 /* write nops over the section of code */
166 /* todo: if large section, add a branch at the start of it */
170 lis r0,0x60000000@h /* nop */
172 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
174 dcbst 0,r8 /* suboptimal, but simpler */
179 sync /* additional sync needed on g4 */
184 * call_setup_cpu - call the setup_cpu function for this cpu
185 * r3 = data offset, r24 = cpu number
187 * Setup function is called with:
190 * r5 = ptr to CPU spec (relocated)
192 _GLOBAL(call_setup_cpu)
193 addis r5,r3,cur_cpu_spec@ha
194 addi r5,r5,cur_cpu_spec@l
198 lwz r6,CPU_SPEC_SETUP(r5)
204 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
206 /* This gets called by via-pmu.c to switch the PLL selection
207 * on 750fx CPU. This function should really be moved to some
208 * other place (as most of the cpufreq code in via-pmu
210 _GLOBAL(low_choose_750fx_pll)
216 /* If switching to PLL1, disable HID0:BTIC */
227 /* Calc new HID1 value */
228 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
229 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
230 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
234 /* Store new HID1 image */
238 addis r6,r6,nap_save_hid1@ha
239 stw r4,nap_save_hid1@l(r6)
241 /* If switching to PLL0, enable HID0:BTIC */
256 _GLOBAL(low_choose_7447a_dfs)
262 /* Calc new HID1 value */
264 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
274 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
277 * complement mask on the msr then "or" some values on.
278 * _nmask_and_or_msr(nmask, value_to_or)
280 _GLOBAL(_nmask_and_or_msr)
281 mfmsr r0 /* Get current msr */
282 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
283 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
284 SYNC /* Some chip revs have problems here... */
285 mtmsr r0 /* Update machine state */
294 #if defined(CONFIG_40x)
295 sync /* Flush to memory before changing mapping */
297 isync /* Flush shadow TLB */
298 #elif defined(CONFIG_44x)
302 /* Load high watermark */
303 lis r4,tlb_44x_hwater@ha
304 lwz r5,tlb_44x_hwater@l(r4)
306 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
312 #elif defined(CONFIG_FSL_BOOKE)
313 /* Invalidate all entries in TLB0 */
316 /* Invalidate all entries in TLB1 */
319 /* Invalidate all entries in TLB2 */
322 /* Invalidate all entries in TLB3 */
328 #endif /* CONFIG_SMP */
329 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
330 #if defined(CONFIG_SMP)
336 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
337 rlwinm r0,r0,0,28,26 /* clear DR */
341 lis r9,mmu_hash_lock@h
342 ori r9,r9,mmu_hash_lock@l
354 stw r0,0(r9) /* clear mmu_hash_lock */
358 #else /* CONFIG_SMP */
362 #endif /* CONFIG_SMP */
363 #endif /* ! defined(CONFIG_40x) */
367 * Flush MMU TLB for a particular address
370 #if defined(CONFIG_40x)
374 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
375 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
377 tlbwe r3, r3, TLB_TAG
380 #elif defined(CONFIG_44x)
382 mfspr r5,SPRN_PID /* Get PID */
383 rlwimi r4,r5,0,24,31 /* Set TID */
389 /* There are only 64 TLB entries, so r3 < 64,
390 * which means bit 22, is clear. Since 22 is
391 * the V bit in the TLB_PAGEID, loading this
392 * value will invalidate the TLB entry.
394 tlbwe r3, r3, PPC44x_TLB_PAGEID
397 #elif defined(CONFIG_FSL_BOOKE)
398 rlwinm r4, r3, 0, 0, 19
399 ori r5, r4, 0x08 /* TLBSEL = 1 */
400 ori r6, r4, 0x10 /* TLBSEL = 2 */
401 ori r7, r4, 0x18 /* TLBSEL = 3 */
407 #if defined(CONFIG_SMP)
409 #endif /* CONFIG_SMP */
410 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
411 #if defined(CONFIG_SMP)
417 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
418 rlwinm r0,r0,0,28,26 /* clear DR */
422 lis r9,mmu_hash_lock@h
423 ori r9,r9,mmu_hash_lock@l
435 stw r0,0(r9) /* clear mmu_hash_lock */
439 #else /* CONFIG_SMP */
442 #endif /* CONFIG_SMP */
443 #endif /* ! CONFIG_40x */
447 * Flush instruction cache.
448 * This is a no-op on the 601.
450 _GLOBAL(flush_instruction_cache)
451 #if defined(CONFIG_8xx)
454 mtspr SPRN_IC_CST, r5
455 #elif defined(CONFIG_4xx)
467 #elif CONFIG_FSL_BOOKE
470 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
471 /* msync; isync recommended here */
475 END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
477 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
481 rlwinm r3,r3,16,16,31
483 beqlr /* for 601, do nothing */
484 /* 603/604 processor - use invalidate-all bit in HID0 */
488 #endif /* CONFIG_8xx/4xx */
493 * Write any modified data cache blocks out to memory
494 * and invalidate the corresponding instruction cache blocks.
495 * This is a no-op on the 601.
497 * flush_icache_range(unsigned long start, unsigned long stop)
499 _GLOBAL(flush_icache_range)
501 blr /* for 601, do nothing */
502 END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
503 li r5,L1_CACHE_LINE_SIZE-1
507 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
512 addi r3,r3,L1_CACHE_LINE_SIZE
514 sync /* wait for dcbst's to get to ram */
517 addi r6,r6,L1_CACHE_LINE_SIZE
519 sync /* additional sync needed on g4 */
523 * Write any modified data cache blocks out to memory.
524 * Does not invalidate the corresponding cache lines (especially for
525 * any corresponding instruction cache).
527 * clean_dcache_range(unsigned long start, unsigned long stop)
529 _GLOBAL(clean_dcache_range)
530 li r5,L1_CACHE_LINE_SIZE-1
534 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
539 addi r3,r3,L1_CACHE_LINE_SIZE
541 sync /* wait for dcbst's to get to ram */
545 * Write any modified data cache blocks out to memory and invalidate them.
546 * Does not invalidate the corresponding instruction cache blocks.
548 * flush_dcache_range(unsigned long start, unsigned long stop)
550 _GLOBAL(flush_dcache_range)
551 li r5,L1_CACHE_LINE_SIZE-1
555 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
560 addi r3,r3,L1_CACHE_LINE_SIZE
562 sync /* wait for dcbst's to get to ram */
566 * Like above, but invalidate the D-cache. This is used by the 8xx
567 * to invalidate the cache so the PPC core doesn't get stale data
568 * from the CPM (no cache snooping here :-).
570 * invalidate_dcache_range(unsigned long start, unsigned long stop)
572 _GLOBAL(invalidate_dcache_range)
573 li r5,L1_CACHE_LINE_SIZE-1
577 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE
582 addi r3,r3,L1_CACHE_LINE_SIZE
584 sync /* wait for dcbi's to get to ram */
587 #ifdef CONFIG_NOT_COHERENT_CACHE
589 * 40x cores have 8K or 16K dcache and 32 byte line size.
590 * 44x has a 32K dcache and 32 byte line size.
591 * 8xx has 1, 2, 4, 8K variants.
592 * For now, cover the worst case of the 44x.
593 * Must be called with external interrupts disabled.
595 #define CACHE_NWAYS 64
596 #define CACHE_NLINES 16
598 _GLOBAL(flush_dcache_all)
599 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
602 1: lwz r3, 0(r5) /* Load one word from every line */
603 addi r5, r5, L1_CACHE_LINE_SIZE
606 #endif /* CONFIG_NOT_COHERENT_CACHE */
609 * Flush a particular page from the data cache to RAM.
610 * Note: this is necessary because the instruction cache does *not*
611 * snoop from the data cache.
612 * This is a no-op on the 601 which has a unified cache.
614 * void __flush_dcache_icache(void *page)
616 _GLOBAL(__flush_dcache_icache)
618 blr /* for 601, do nothing */
619 END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
620 rlwinm r3,r3,0,0,19 /* Get page base address */
621 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
624 0: dcbst 0,r3 /* Write line to ram */
625 addi r3,r3,L1_CACHE_LINE_SIZE
630 addi r6,r6,L1_CACHE_LINE_SIZE
637 * Flush a particular page from the data cache to RAM, identified
638 * by its physical address. We turn off the MMU so we can just use
639 * the physical address (this may be a highmem page without a kernel
642 * void __flush_dcache_icache_phys(unsigned long physaddr)
644 _GLOBAL(__flush_dcache_icache_phys)
646 blr /* for 601, do nothing */
647 END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
649 rlwinm r0,r10,0,28,26 /* clear DR */
652 rlwinm r3,r3,0,0,19 /* Get page base address */
653 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
656 0: dcbst 0,r3 /* Write line to ram */
657 addi r3,r3,L1_CACHE_LINE_SIZE
662 addi r6,r6,L1_CACHE_LINE_SIZE
665 mtmsr r10 /* restore DR */
670 * Clear pages using the dcbz instruction, which doesn't cause any
671 * memory traffic (except to write out any cache lines which get
672 * displaced). This only works on cacheable memory.
674 * void clear_pages(void *page, int order) ;
677 li r0,4096/L1_CACHE_LINE_SIZE
689 addi r3,r3,L1_CACHE_LINE_SIZE
694 * Copy a whole page. We use the dcbz instruction on the destination
695 * to reduce memory traffic (it eliminates the unnecessary reads of
696 * the destination into cache). This requires that the destination
699 #define COPY_16_BYTES \
714 /* don't use prefetch on 8xx */
715 li r0,4096/L1_CACHE_LINE_SIZE
721 #else /* not 8xx, we can prefetch */
724 #if MAX_COPY_PREFETCH > 1
725 li r0,MAX_COPY_PREFETCH
729 addi r11,r11,L1_CACHE_LINE_SIZE
731 #else /* MAX_COPY_PREFETCH == 1 */
733 li r11,L1_CACHE_LINE_SIZE+4
734 #endif /* MAX_COPY_PREFETCH */
735 li r0,4096/L1_CACHE_LINE_SIZE - MAX_COPY_PREFETCH
743 #if L1_CACHE_LINE_SIZE >= 32
745 #if L1_CACHE_LINE_SIZE >= 64
748 #if L1_CACHE_LINE_SIZE >= 128
758 crnot 4*cr0+eq,4*cr0+eq
759 li r0,MAX_COPY_PREFETCH
762 #endif /* CONFIG_8xx */
765 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
766 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
768 _GLOBAL(atomic_clear_mask)
775 _GLOBAL(atomic_set_mask)
784 * I/O string operations
786 * insb(port, buf, len)
787 * outsb(port, buf, len)
788 * insw(port, buf, len)
789 * outsw(port, buf, len)
790 * insl(port, buf, len)
791 * outsl(port, buf, len)
792 * insw_ns(port, buf, len)
793 * outsw_ns(port, buf, len)
794 * insl_ns(port, buf, len)
795 * outsl_ns(port, buf, len)
797 * The *_ns versions don't do byte-swapping.
865 _GLOBAL(__ide_mm_insw)
877 _GLOBAL(__ide_mm_outsw)
889 _GLOBAL(__ide_mm_insl)
901 _GLOBAL(__ide_mm_outsl)
914 * Extended precision shifts.
916 * Updated to be valid for shift counts from 0 to 63 inclusive.
919 * R3/R4 has 64 bit value
923 * ashrdi3: arithmetic right shift (sign propagation)
924 * lshrdi3: logical right shift
925 * ashldi3: left shift
929 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
930 addi r7,r5,32 # could be xori, or addi with -32
931 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
932 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
933 sraw r7,r3,r7 # t2 = MSW >> (count-32)
934 or r4,r4,r6 # LSW |= t1
935 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
936 sraw r3,r3,r5 # MSW = MSW >> count
937 or r4,r4,r7 # LSW |= t2
942 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
943 addi r7,r5,32 # could be xori, or addi with -32
944 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
945 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
946 or r3,r3,r6 # MSW |= t1
947 slw r4,r4,r5 # LSW = LSW << count
948 or r3,r3,r7 # MSW |= t2
953 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
954 addi r7,r5,32 # could be xori, or addi with -32
955 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
956 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
957 or r4,r4,r6 # LSW |= t1
958 srw r3,r3,r5 # MSW = MSW >> count
959 or r4,r4,r7 # LSW |= t2
969 mr r3,r1 /* Close enough */
973 * These are used in the alignment trap handler when emulating
974 * single-precision loads and stores.
975 * We restore and save the fpscr so the task gets the same result
976 * and exceptions as if the cpu had performed the load or store.
979 #ifdef CONFIG_PPC_FPU
981 lfd 0,-4(r5) /* load up fpscr value */
985 mffs 0 /* save new fpscr value */
990 lfd 0,-4(r5) /* load up fpscr value */
994 mffs 0 /* save new fpscr value */
1000 * Create a kernel thread
1001 * kernel_thread(fn, arg, flags)
1003 _GLOBAL(kernel_thread)
1007 mr r30,r3 /* function */
1008 mr r31,r4 /* argument */
1009 ori r3,r5,CLONE_VM /* flags */
1010 oris r3,r3,CLONE_UNTRACED>>16
1011 li r4,0 /* new sp (unused) */
1014 cmpwi 0,r3,0 /* parent or child? */
1015 bne 1f /* return if parent */
1016 li r0,0 /* make top-level stack frame */
1018 mtlr r30 /* fn addr in lr */
1019 mr r3,r31 /* load arg and call fn */
1022 li r0,__NR_exit /* exit if function returns */
1031 * This routine is just here to keep GCC happy - sigh...
1036 #define SYSCALL(name) \
1038 li r0,__NR_##name; \
1042 stw r3,errno@l(r4); \
1048 /* Why isn't this a) automatic, b) written in 'C'? */
1051 _GLOBAL(sys_call_table)
1052 .long sys_restart_syscall /* 0 */
1057 .long sys_open /* 5 */
1062 .long sys_unlink /* 10 */
1067 .long sys_chmod /* 15 */
1069 .long sys_ni_syscall /* old break syscall holder */
1072 .long sys_getpid /* 20 */
1077 .long sys_stime /* 25 */
1082 .long sys_utime /* 30 */
1083 .long sys_ni_syscall /* old stty syscall holder */
1084 .long sys_ni_syscall /* old gtty syscall holder */
1087 .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
1092 .long sys_rmdir /* 40 */
1096 .long sys_ni_syscall /* old prof syscall holder */
1097 .long sys_brk /* 45 */
1102 .long sys_getegid /* 50 */
1104 .long sys_umount /* recycled never used phys() */
1105 .long sys_ni_syscall /* old lock syscall holder */
1107 .long sys_fcntl /* 55 */
1108 .long sys_ni_syscall /* old mpx syscall holder */
1110 .long sys_ni_syscall /* old ulimit syscall holder */
1112 .long sys_umask /* 60 */
1117 .long sys_getpgrp /* 65 */
1122 .long sys_setreuid /* 70 */
1124 .long ppc_sigsuspend
1125 .long sys_sigpending
1126 .long sys_sethostname
1127 .long sys_setrlimit /* 75 */
1128 .long sys_old_getrlimit
1130 .long sys_gettimeofday
1131 .long sys_settimeofday
1132 .long sys_getgroups /* 80 */
1137 .long sys_readlink /* 85 */
1142 .long sys_mmap /* 90 */
1147 .long sys_fchown /* 95 */
1148 .long sys_getpriority
1149 .long sys_setpriority
1150 .long sys_ni_syscall /* old profil syscall holder */
1152 .long sys_fstatfs /* 100 */
1153 .long sys_ni_syscall
1154 .long sys_socketcall
1157 .long sys_getitimer /* 105 */
1162 .long sys_ni_syscall /* 110 */
1164 .long sys_ni_syscall /* old 'idle' syscall */
1165 .long sys_ni_syscall
1167 .long sys_swapoff /* 115 */
1172 .long ppc_clone /* 120 */
1173 .long sys_setdomainname
1175 .long sys_ni_syscall
1177 .long sys_mprotect /* 125 */
1178 .long sys_sigprocmask
1179 .long sys_ni_syscall /* old sys_create_module */
1180 .long sys_init_module
1181 .long sys_delete_module
1182 .long sys_ni_syscall /* old sys_get_kernel_syms */ /* 130 */
1187 .long sys_sysfs /* 135 */
1188 .long sys_personality
1189 .long sys_ni_syscall /* for afs_syscall */
1192 .long sys_llseek /* 140 */
1197 .long sys_readv /* 145 */
1202 .long sys_mlock /* 150 */
1205 .long sys_munlockall
1206 .long sys_sched_setparam
1207 .long sys_sched_getparam /* 155 */
1208 .long sys_sched_setscheduler
1209 .long sys_sched_getscheduler
1210 .long sys_sched_yield
1211 .long sys_sched_get_priority_max
1212 .long sys_sched_get_priority_min /* 160 */
1213 .long sys_sched_rr_get_interval
1217 .long sys_getresuid /* 165 */
1218 .long sys_ni_syscall /* old sys_query_module */
1220 .long sys_nfsservctl
1222 .long sys_getresgid /* 170 */
1224 .long sys_rt_sigreturn
1225 .long sys_rt_sigaction
1226 .long sys_rt_sigprocmask
1227 .long sys_rt_sigpending /* 175 */
1228 .long sys_rt_sigtimedwait
1229 .long sys_rt_sigqueueinfo
1230 .long ppc_rt_sigsuspend
1232 .long sys_pwrite64 /* 180 */
1237 .long sys_sigaltstack /* 185 */
1239 .long sys_ni_syscall /* streams1 */
1240 .long sys_ni_syscall /* streams2 */
1242 .long sys_getrlimit /* 190 */
1245 .long sys_truncate64
1246 .long sys_ftruncate64
1247 .long sys_stat64 /* 195 */
1250 .long sys_pciconfig_read
1251 .long sys_pciconfig_write
1252 .long sys_pciconfig_iobase /* 200 */
1253 .long sys_ni_syscall /* 201 - reserved - MacOnLinux - new */
1254 .long sys_getdents64
1255 .long sys_pivot_root
1257 .long sys_madvise /* 205 */
1262 .long sys_lsetxattr /* 210 */
1267 .long sys_listxattr /* 215 */
1268 .long sys_llistxattr
1269 .long sys_flistxattr
1270 .long sys_removexattr
1271 .long sys_lremovexattr
1272 .long sys_fremovexattr /* 220 */
1274 .long sys_sched_setaffinity
1275 .long sys_sched_getaffinity
1276 .long sys_ni_syscall
1277 .long sys_ni_syscall /* 225 - reserved for Tux */
1278 .long sys_sendfile64
1280 .long sys_io_destroy
1281 .long sys_io_getevents
1282 .long sys_io_submit /* 230 */
1284 .long sys_set_tid_address
1286 .long sys_exit_group
1287 .long sys_lookup_dcookie /* 235 */
1288 .long sys_epoll_create
1290 .long sys_epoll_wait
1291 .long sys_remap_file_pages
1292 .long sys_timer_create /* 240 */
1293 .long sys_timer_settime
1294 .long sys_timer_gettime
1295 .long sys_timer_getoverrun
1296 .long sys_timer_delete
1297 .long sys_clock_settime /* 245 */
1298 .long sys_clock_gettime
1299 .long sys_clock_getres
1300 .long sys_clock_nanosleep
1301 .long ppc_swapcontext
1302 .long sys_tgkill /* 250 */
1306 .long ppc_fadvise64_64
1307 .long sys_ni_syscall /* 255 - rtas (used on ppc64) */
1308 .long sys_debug_setcontext
1309 .long sys_ni_syscall /* 257 reserved for vserver */
1310 .long sys_ni_syscall /* 258 reserved for new sys_remap_file_pages */
1311 .long sys_ni_syscall /* 259 reserved for new sys_mbind */
1312 .long sys_ni_syscall /* 260 reserved for new sys_get_mempolicy */
1313 .long sys_ni_syscall /* 261 reserved for new sys_set_mempolicy */
1316 .long sys_mq_timedsend
1317 .long sys_mq_timedreceive /* 265 */
1319 .long sys_mq_getsetattr
1320 .long sys_kexec_load
1322 .long sys_request_key /* 270 */
1325 .long sys_ioprio_set
1326 .long sys_ioprio_get
1327 .long sys_inotify_init /* 275 */
1328 .long sys_inotify_add_watch
1329 .long sys_inotify_rm_watch