2 * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
4 * Dale Farnsworth <dale@farnsworth.org>
5 * Mark A. Greer <mgreer@mvista.com>
6 * Nicolas DET <nd@bplan-gmbh.de>
7 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
8 * And anyone else who helped me on this.
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/platform_device.h>
15 #include <linux/mv643xx.h>
16 #include <linux/pci.h>
18 #define PEGASOS2_MARVELL_REGBASE (0xf1000000)
19 #define PEGASOS2_MARVELL_REGSIZE (0x00004000)
20 #define PEGASOS2_SRAM_BASE (0xf2000000)
21 #define PEGASOS2_SRAM_SIZE (256*1024)
23 #define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE)
24 #define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) )
27 #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
28 #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
32 static struct resource mv643xx_eth_shared_resources[] = {
34 .name = "ethernet shared base",
35 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
36 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
37 MV643XX_ETH_SHARED_REGS_SIZE - 1,
38 .flags = IORESOURCE_MEM,
42 static struct platform_device mv643xx_eth_shared_device = {
43 .name = MV643XX_ETH_SHARED_NAME,
45 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
46 .resource = mv643xx_eth_shared_resources,
49 static struct resource mv643xx_eth0_resources[] = {
54 .flags = IORESOURCE_IRQ,
59 static struct mv643xx_eth_platform_data eth0_pd = {
60 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
61 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
62 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
64 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
65 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
66 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
69 static struct platform_device eth0_device = {
70 .name = MV643XX_ETH_NAME,
72 .num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
73 .resource = mv643xx_eth0_resources,
75 .platform_data = ð0_pd,
79 static struct resource mv643xx_eth1_resources[] = {
84 .flags = IORESOURCE_IRQ,
88 static struct mv643xx_eth_platform_data eth1_pd = {
89 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1,
90 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
91 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
93 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE,
94 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
95 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
98 static struct platform_device eth1_device = {
99 .name = MV643XX_ETH_NAME,
101 .num_resources = ARRAY_SIZE(mv643xx_eth1_resources),
102 .resource = mv643xx_eth1_resources,
104 .platform_data = ð1_pd,
108 static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
109 &mv643xx_eth_shared_device,
116 #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
117 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
119 static void __iomem *mv643xx_reg_base;
121 static int Enable_SRAM(void)
125 if (mv643xx_reg_base == NULL)
126 mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
127 PEGASOS2_MARVELL_REGSIZE);
129 if (mv643xx_reg_base == NULL)
133 printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
134 (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
137 MV_WRITE(MV64340_SRAM_CONFIG, 0);
139 MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
141 MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
143 MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
146 ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
147 MV_WRITE(MV643XX_ETH_BAR_4, ALong);
149 MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
151 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
153 MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
156 printk("Pegasos II/Marvell MV64361: register unmapped\n");
157 printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
160 iounmap(mv643xx_reg_base);
161 mv643xx_reg_base = NULL;
169 int mv643xx_eth_add_pds(void)
172 static struct pci_device_id pci_marvell_mv64360[] = {
173 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
178 printk("Pegasos II/Marvell MV64361: init\n");
181 if (pci_dev_present(pci_marvell_mv64360)) {
182 ret = platform_add_devices(mv643xx_eth_pd_devs,
183 ARRAY_SIZE(mv643xx_eth_pd_devs));
185 if ( Enable_SRAM() < 0)
187 eth0_pd.tx_sram_addr = 0;
188 eth0_pd.tx_sram_size = 0;
189 eth0_pd.rx_sram_addr = 0;
190 eth0_pd.rx_sram_size = 0;
192 eth1_pd.tx_sram_addr = 0;
193 eth1_pd.tx_sram_size = 0;
194 eth1_pd.rx_sram_addr = 0;
195 eth1_pd.rx_sram_size = 0;
198 printk("Pegasos II/Marvell MV64361: Can't enable the "
205 printk("Pegasos II/Marvell MV64361: init is over\n");
211 device_initcall(mv643xx_eth_add_pds);