2 * arch/s390/kernel/head64.S
4 * Copyright (C) IBM Corp. 1999,2006
6 * Author(s): Hartmut Penner <hp@de.ibm.com>
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>
8 * Rob van der Heij <rvdhei@iae.nl>
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
14 # startup-code at 0x10000, running in absolute addressing mode
15 # this is called either by the ipl loader or directly by PSW restart
16 # or linload or SALIPL
19 startup:basr %r13,0 # get base
20 .LPG0: l %r13,0f-.LPG0(%r13)
22 0: .long startup_continue
25 # params at 10400 (setup.h)
29 .quad 0 # INITRD_START
33 .byte "root=/dev/ram0 ro"
39 basr %r13,0 # get base
40 .LPG1: sll %r13,1 # remove high order bit
42 lhi %r1,1 # mode 1 = esame
43 mvi __LC_AR_MODE_ID,1 # set esame flag
44 slr %r0,%r0 # set cpuid to zero
45 sigp %r1,%r0,0x12 # switch to esame mode
46 sam64 # switch to 64 bit mode
47 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
48 lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
49 # move IPL device to lowcore
50 mvc __LC_IPLDEV(4),IPL_DEVICE+4-PARMAREA(%r12)
54 larl %r15,init_thread_union
55 lg %r14,__TI_task(%r15) # cache current in lowcore
57 aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
58 stg %r15,__LC_KERNEL_STACK # set end of kernel stack
60 xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear backchain
62 brasl %r14,ipl_save_parameters
66 larl %r2,__bss_start # start of bss segment
67 larl %r3,_end # end of bss segment
68 sgr %r3,%r2 # length of bss
70 sgr %r5,%r5 # set src,length and pad to zero
71 mvcle %r2,%r4,0 # clear mem
72 jo .-4 # branch back, if not finish
73 # set program check new psw mask
74 mvc __LC_PGM_NEW_PSW(8),.Lpcmsk-.LPG1(%r13)
75 larl %r1,.Lslowmemdetect # set program check address
76 stg %r1,__LC_PGM_NEW_PSW+8
78 diag %r0,%r1,0x260 # get memory size of virtual machine
79 cgr %r0,%r1 # different? -> old detection routine
81 aghi %r1,1 # size is one more than end
83 stg %r1,8(%r2) # store size of chunk
86 l %r2,.Lrcp-.LPG1(%r13) # Read SCP forced command word
88 stosm .Lpmask-.LPG1(%r13),0x01 # authorize ext interrupts
90 stctg %r0,%r0,.Lcr-.LPG1(%r13) # get cr0
91 la %r1,0x200 # set bit 22
92 og %r1,.Lcr-.LPG1(%r13) # or old cr0 with r1
93 stg %r1,.Lcr-.LPG1(%r13)
94 lctlg %r0,%r0,.Lcr-.LPG1(%r13) # load modified cr0
96 mvc __LC_EXT_NEW_PSW(8),.Lpcmsk-.LPG1(%r13) # set postcall psw
98 stg %r1,__LC_EXT_NEW_PSW+8 # set handler
100 larl %r4,.Lsccb # %r4 is our index for sccb stuff
101 lgr %r1,%r4 # our sccb
102 .insn rre,0xb2200000,%r2,%r1 # service call
104 srl %r1,28 # get cc code
107 be .Lfchunk-.LPG1(%r13) # leave
109 be .Lservicecall-.LPG1(%r13)
110 lpswe .Lwaitsclp-.LPG1(%r13)
112 lh %r1,.Lsccbr-.Lsccb(%r4)
113 chi %r1,0x10 # 0x0010 is the sucess code
114 je .Lprocsccb # let's process the sccb
116 bne .Lfchunk-.LPG1(%r13) # unhandled error code
117 c %r2,.Lrcp-.LPG1(%r13) # Did we try Read SCP forced
118 bne .Lfchunk-.LPG1(%r13) # if no, give up
119 l %r2,.Lrcp2-.LPG1(%r13) # try with Read SCP
120 b .Lservicecall-.LPG1(%r13)
123 icm %r1,3,.Lscpincr1-.Lsccb(%r4) # use this one if != 0
125 lg %r1,.Lscpincr2-.Lsccb(%r4) # otherwise use this one
127 xr %r3,%r3 # same logic
128 ic %r3,.Lscpa1-.Lsccb(%r4)
131 l %r3,.Lscpa2-.Lsccb(%r4)
133 mlgr %r2,%r1 # mem in MB on 128-bit
134 l %r1,.Lonemb-.LPG1(%r13)
135 mlgr %r2,%r1 # mem size in bytes in %r3
136 b .Lfchunk-.LPG1(%r13)
143 .quad 0x00 # place holder for cr0
145 .quad 0x0102000180000000,.Lsclph
147 .int 0x00120001 # Read SCP forced code
149 .int 0x00020001 # Read SCP code
156 # find memory chunks.
158 larl %r9,memory_chunk # skip tprot loop if diag260
159 lg %r9,8(%r9) # memory detection was successful
163 lgr %r9,%r3 # end of mem
164 larl %r1,.Lchkmem # set program check address
165 stg %r1,__LC_PGM_NEW_PSW+8
166 la %r1,1 # test in increments of 128KB
168 larl %r3,memory_chunk
169 slgr %r4,%r4 # set start of chunk to zero
170 slgr %r5,%r5 # set end of chunk to zero
171 slr %r6,%r6 # set access code to zero
172 la %r10,MEMORY_CHUNKS # number of chunks
174 tprot 0(%r5),0 # test protection of first byte
177 clr %r6,%r7 # compare cc with last access code
179 lghi %r8,0 # no program checks
182 algr %r5,%r1 # add 128KB to end of chunk
183 # no need to check here,
184 brc 12,.Lloop # this is the same chunk
185 .Lchkmem: # > 16EB or tprot got a program check
186 lghi %r8,1 # set program check flag
188 clgr %r4,%r5 # chunk size > 0?
190 stg %r4,0(%r3) # store start address of chunk
193 stg %r0,8(%r3) # store size of chunk
194 st %r6,20(%r3) # store type of chunk
196 ahi %r10,-1 # update chunk number
198 lr %r6,%r7 # set access code to last cc
199 # we got an exception or we're starting a new
200 # chunk , we must check if we should
201 # still try to find valid memory (if we detected
202 # the amount of available storage), and if we
209 clgr %r0, %r9 # did we detect memory?
210 je .Ldonemem # if not, leave
211 chi %r10, 0 # do we have chunks left?
214 chi %r8,1 # program check ?
216 lgr %r4,%r5 # potential new chunk
217 algr %r5,%r1 # add 128KB to end of chunk
220 algr %r5,%r1 # add 128KB to end of chunk
221 lgr %r4,%r5 # potential new chunk
223 clgr %r5,%r9 # should we go on?
227 larl %r12,machine_flags
229 # find out if we are running under VM
231 stidp __LC_CPUID # store cpuid
232 tm __LC_CPUID,0xff # running under VM ?
234 oi 7(%r12),1 # set VM flag
235 0: lh %r0,__LC_CPUID+4 # get cpu version
236 chi %r0,0x7490 # running on a P/390 ?
238 oi 7(%r12),4 # set P/390 flag
242 # find out if we have the MVPG instruction
244 la %r1,0f-.LPG1(%r13) # set program check address
245 stg %r1,__LC_PGM_NEW_PSW+8
249 mvpg %r1,%r2 # test MVPG instruction
250 oi 7(%r12),16 # set MVPG flag
254 # find out if the diag 0x44 works in 64 bit mode
256 la %r1,0f-.LPG1(%r13) # set program check address
257 stg %r1,__LC_PGM_NEW_PSW+8
258 diag 0,0,0x44 # test diag 0x44
259 oi 7(%r12),32 # set diag44 flag
263 # find out if we have the IDTE instruction
265 la %r1,0f-.LPG1(%r13) # set program check address
266 stg %r1,__LC_PGM_NEW_PSW+8
267 .long 0xb2b10000 # store facility list
268 tm 0xc8,0x08 # check bit for clearing-by-ASCE
273 oi 7(%r12),0x80 # set IDTE flag
277 # find out if the diag 0x9c is available
279 la %r1,0f-.LPG1(%r13) # set program check address
280 stg %r1,__LC_PGM_NEW_PSW+8
281 stap __LC_CPUID+4 # store cpu address
283 diag %r1,0,0x9c # test diag 0x9c
284 oi 6(%r12),1 # set diag9c flag
288 # find out if we have the MVCOS instruction
290 la %r1,0f-.LPG1(%r13) # set program check address
291 stg %r1,__LC_PGM_NEW_PSW+8
292 .short 0xc800 # mvcos 0(%r0),0(%r0),%r0
295 0: tm 0x8f,0x13 # special-operation exception?
296 bno 1f-.LPG1(%r13) # if yes, MVCOS is present
297 oi 6(%r12),2 # set MVCOS flag
300 lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
301 # virtual and never return ...
303 .Lentry:.quad 0x0000000180000000,_stext
304 .Lctl: .quad 0x04b50002 # cr0: various things
305 .quad 0 # cr1: primary space segment table
306 .quad .Lduct # cr2: dispatchable unit control table
307 .quad 0 # cr3: instruction authorization
308 .quad 0 # cr4: instruction authorization
309 .quad 0xffffffffffffffff # cr5: primary-aste origin
310 .quad 0 # cr6: I/O interrupts
311 .quad 0 # cr7: secondary space segment table
312 .quad 0 # cr8: access registers translation
313 .quad 0 # cr9: tracing off
314 .quad 0 # cr10: tracing off
315 .quad 0 # cr11: tracing off
316 .quad 0 # cr12: tracing off
317 .quad 0 # cr13: home space segment table
318 .quad 0xc0000000 # cr14: machine check handling off
319 .quad 0 # cr15: linkage stack operations
320 .Lduct: .long 0,0,0,0,0,0,0,0
321 .long 0,0,0,0,0,0,0,0
322 .Lpcmsk:.quad 0x0000000180000000
323 .L4malign:.quad 0xffffffffffc00000
324 .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
325 .Lnop: .long 0x07000700
343 .globl s390_readinfo_sccb
346 .hword 0x1000 # length, one page
348 .byte 0x80 # variable response bit set
350 .hword 0x00 # response code
363 #ifdef CONFIG_SHARED_KERNEL
368 # startup-code, running in absolute addressing mode
371 _stext: basr %r13,0 # get base
373 # check control registers
374 stctg %c0,%c15,0(%r15)
375 oi 6(%r15),0x40 # enable sigp emergency signal
376 oi 4(%r15),0x10 # switch on low address proctection
377 lctlg %c0,%c15,0(%r15)
379 lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
380 brasl %r14,start_kernel # go to C code
382 # We returned from start_kernel ?!? PANIK
385 lpswe .Ldw-.(%r13) # load disabled wait psw
388 .Ldw: .quad 0x0002000180000000,0x0000000000000000
389 .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0