arch/sparc64/kernel/irq.c

   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/sbus.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44
  45 #ifdef CONFIG_SMP
  46 static void distribute_irqs(void);
  47 #endif
  48
  49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  50  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  51  * delivered.  We must translate this into a non-vector IRQ so we can
  52  * set the softint on this cpu.
  53  *
  54  * To make processing these packets efficient and race free we use
  55  * an array of irq buckets below.  The interrupt vector handler in
  56  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  57  * The IVEC handler does not need to act atomically, the PIL dispatch
  58  * code uses CAS to get an atomic snapshot of the list and clear it
  59  * at the same time.
  60  */
  61
  62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  63
  64 /* This has to be in the main kernel image, it cannot be
  65  * turned into per-cpu data.  The reason is that the main
  66  * kernel image is locked into the TLB and this structure
  67  * is accessed from the vectored interrupt trap handler.  If
  68  * access to this structure takes a TLB miss it could cause
  69  * the 5-level sparc v9 trap stack to overflow.
  70  */
  71 struct irq_work_struct {
  72         unsigned int    irq_worklists[16];
  73 };
  74 struct irq_work_struct __irq_work[NR_CPUS];
  75 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  76
  77 static struct irqaction *irq_action[NR_IRQS+1];
  78
  79 /* This only synchronizes entities which modify IRQ handler
  80  * state and some selected user-level spots that want to
  81  * read things in the table.  IRQ handler processing orders
  82  * its' accesses such that no locking is needed.
  83  */
  84 static DEFINE_SPINLOCK(irq_action_lock);
  85
  86 static void register_irq_proc (unsigned int irq);
  87
  88 /*
  89  * Upper 2b of irqaction->flags holds the ino.
  90  * irqaction->mask holds the smp affinity information.
  91  */
  92 #define put_ino_in_irqaction(action, irq) \
  93         action->flags &= 0xffffffffffffUL; \
  94         if (__bucket(irq) == &pil0_dummy_bucket) \
  95                 action->flags |= 0xdeadUL << 48;  \
  96         else \
  97                 action->flags |= __irq_ino(irq) << 48;
  98 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  99
 100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 101 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 102
 103 int show_interrupts(struct seq_file *p, void *v)
 104 {
 105         unsigned long flags;
 106         int i = *(loff_t *) v;
 107         struct irqaction *action;
 108 #ifdef CONFIG_SMP
 109         int j;
 110 #endif
 111
 112         spin_lock_irqsave(&irq_action_lock, flags);
 113         if (i <= NR_IRQS) {
 114                 if (!(action = *(i + irq_action)))
 115                         goto out_unlock;
 116                 seq_printf(p, "%3d: ", i);
 117 #ifndef CONFIG_SMP
 118                 seq_printf(p, "%10u ", kstat_irqs(i));
 119 #else
 120                 for (j = 0; j < NR_CPUS; j++) {
 121                         if (!cpu_online(j))
 122                                 continue;
 123                         seq_printf(p, "%10u ",
 124                                    kstat_cpu(j).irqs[i]);
 125                 }
 126 #endif
 127                 seq_printf(p, " %s:%lx", action->name,
 128                            get_ino_in_irqaction(action));
 129                 for (action = action->next; action; action = action->next) {
 130                         seq_printf(p, ", %s:%lx", action->name,
 131                                    get_ino_in_irqaction(action));
 132                 }
 133                 seq_putc(p, '\n');
 134         }
 135 out_unlock:
 136         spin_unlock_irqrestore(&irq_action_lock, flags);
 137
 138         return 0;
 139 }
 140
 141 extern unsigned long real_hard_smp_processor_id(void);
 142
 143 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 144 {
 145         unsigned int tid;
 146
 147         if (this_is_starfire) {
 148                 tid = starfire_translate(imap, cpuid);
 149                 tid <<= IMAP_TID_SHIFT;
 150                 tid &= IMAP_TID_UPA;
 151         } else {
 152                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 153                         unsigned long ver;
 154
 155                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 156                         if ((ver >> 32UL) == __JALAPENO_ID ||
 157                             (ver >> 32UL) == __SERRANO_ID) {
 158                                 tid = cpuid << IMAP_TID_SHIFT;
 159                                 tid &= IMAP_TID_JBUS;
 160                         } else {
 161                                 unsigned int a = cpuid & 0x1f;
 162                                 unsigned int n = (cpuid >> 5) & 0x1f;
 163
 164                                 tid = ((a << IMAP_AID_SHIFT) |
 165                                        (n << IMAP_NID_SHIFT));
 166                                 tid &= (IMAP_AID_SAFARI |
 167                                         IMAP_NID_SAFARI);;
 168                         }
 169                 } else {
 170                         tid = cpuid << IMAP_TID_SHIFT;
 171                         tid &= IMAP_TID_UPA;
 172                 }
 173         }
 174
 175         return tid;
 176 }
 177
 178 /* Now these are always passed a true fully specified sun4u INO. */
 179 void enable_irq(unsigned int irq)
 180 {
 181         struct ino_bucket *bucket = __bucket(irq);
 182         unsigned long imap, cpuid;
 183
 184         imap = bucket->imap;
 185         if (imap == 0UL)
 186                 return;
 187
 188         preempt_disable();
 189
 190         /* This gets the physical processor ID, even on uniprocessor,
 191          * so we can always program the interrupt target correctly.
 192          */
 193         cpuid = real_hard_smp_processor_id();
 194
 195         if (tlb_type == hypervisor) {
 196                 unsigned int ino = __irq_ino(irq);
 197                 int err;
 198
 199                 err = sun4v_intr_settarget(ino, cpuid);
 200                 if (err != HV_EOK)
 201                         printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
 202                                ino, cpuid, err);
 203                 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 204                 if (err != HV_EOK)
 205                         printk("sun4v_intr_setenabled(%x): err(%d)\n",
 206                                ino, err);
 207         } else {
 208                 unsigned int tid = sun4u_compute_tid(imap, cpuid);
 209
 210                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 211                  * of this SYSIO's preconfigured IGN in the SYSIO Control
 212                  * Register, the hardware just mirrors that value here.
 213                  * However for Graphics and UPA Slave devices the full
 214                  * IMAP_INR field can be set by the programmer here.
 215                  *
 216                  * Things like FFB can now be handled via the new IRQ
 217                  * mechanism.
 218                  */
 219                 upa_writel(tid | IMAP_VALID, imap);
 220         }
 221
 222         preempt_enable();
 223 }
 224
 225 /* This now gets passed true ino's as well. */
 226 void disable_irq(unsigned int irq)
 227 {
 228         struct ino_bucket *bucket = __bucket(irq);
 229         unsigned long imap;
 230
 231         imap = bucket->imap;
 232         if (imap != 0UL) {
 233                 if (tlb_type == hypervisor) {
 234                         unsigned int ino = __irq_ino(irq);
 235                         int err;
 236
 237                         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 238                         if (err != HV_EOK)
 239                                 printk("sun4v_intr_setenabled(%x): "
 240                                        "err(%d)\n", ino, err);
 241                 } else {
 242                         u32 tmp;
 243
 244                         /* NOTE: We do not want to futz with the IRQ clear registers
 245                          *       and move the state to IDLE, the SCSI code does call
 246                          *       disable_irq() to assure atomicity in the queue cmd
 247                          *       SCSI adapter driver code.  Thus we'd lose interrupts.
 248                          */
 249                         tmp = upa_readl(imap);
 250                         tmp &= ~IMAP_VALID;
 251                         upa_writel(tmp, imap);
 252                 }
 253         }
 254 }
 255
 256 /* The timer is the one "weird" interrupt which is generated by
 257  * the CPU %tick register and not by some normal vectored interrupt
 258  * source.  To handle this special case, we use this dummy INO bucket.
 259  */
 260 static struct irq_desc pil0_dummy_desc;
 261 static struct ino_bucket pil0_dummy_bucket = {
 262         .irq_info       =       &pil0_dummy_desc,
 263 };
 264
 265 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 266                             unsigned long iclr, unsigned long imap,
 267                             struct ino_bucket *bucket)
 268 {
 269         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 270                     "(%d:%d:%016lx:%016lx), halting...\n",
 271                     ino, bucket->pil, bucket->iclr, bucket->imap,
 272                     pil, inofixup, iclr, imap);
 273         prom_halt();
 274 }
 275
 276 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 277 {
 278         struct ino_bucket *bucket;
 279         int ino;
 280
 281         if (pil == 0) {
 282                 if (iclr != 0UL || imap != 0UL) {
 283                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 284                                     iclr, imap);
 285                         prom_halt();
 286                 }
 287                 return __irq(&pil0_dummy_bucket);
 288         }
 289
 290         BUG_ON(tlb_type == hypervisor);
 291
 292         /* RULE: Both must be specified in all other cases. */
 293         if (iclr == 0UL || imap == 0UL) {
 294                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 295                             pil, inofixup, iclr, imap);
 296                 prom_halt();
 297         }
 298
 299         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 300         if (ino > NUM_IVECS) {
 301                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 302                             ino, pil, inofixup, iclr, imap);
 303                 prom_halt();
 304         }
 305
 306         bucket = &ivector_table[ino];
 307         if (bucket->flags & IBF_ACTIVE)
 308                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 309                                 ino, pil, inofixup, iclr, imap, bucket);
 310
 311         if (bucket->irq_info) {
 312                 if (bucket->imap != imap || bucket->iclr != iclr)
 313                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 314                                         ino, pil, inofixup, iclr, imap, bucket);
 315
 316                 goto out;
 317         }
 318
 319         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 320         if (!bucket->irq_info) {
 321                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 322                 prom_halt();
 323         }
 324         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 325
 326         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 327          * the pending flag.
 328          */
 329         bucket->imap  = imap;
 330         bucket->iclr  = iclr;
 331         bucket->pil   = pil;
 332         bucket->flags = 0;
 333
 334 out:
 335         return __irq(bucket);
 336 }
 337
 338 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
 339 {
 340         struct ino_bucket *bucket;
 341         unsigned long sysino;
 342
 343         sysino = sun4v_devino_to_sysino(devhandle, devino);
 344
 345         bucket = &ivector_table[sysino];
 346
 347         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 348          * is done by hypervisor calls on sun4v platforms, not by direct
 349          * register accesses.
 350          *
 351          * But we need to make them look unique for the disable_irq() logic
 352          * in free_irq().
 353          */
 354         bucket->imap = ~0UL - sysino;
 355         bucket->iclr = ~0UL - sysino;
 356
 357         bucket->pil = pil;
 358         bucket->flags = flags;
 359
 360         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 361         if (!bucket->irq_info) {
 362                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 363                 prom_halt();
 364         }
 365         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 366
 367         return __irq(bucket);
 368 }
 369
 370 static void atomic_bucket_insert(struct ino_bucket *bucket)
 371 {
 372         unsigned long pstate;
 373         unsigned int *ent;
 374
 375         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 376         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 377                              : : "r" (pstate), "i" (PSTATE_IE));
 378         ent = irq_work(smp_processor_id(), bucket->pil);
 379         bucket->irq_chain = *ent;
 380         *ent = __irq(bucket);
 381         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 382 }
 383
 384 static int check_irq_sharing(int pil, unsigned long irqflags)
 385 {
 386         struct irqaction *action, *tmp;
 387
 388         action = *(irq_action + pil);
 389         if (action) {
 390                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 391                         for (tmp = action; tmp->next; tmp = tmp->next)
 392                                 ;
 393                 } else {
 394                         return -EBUSY;
 395                 }
 396         }
 397         return 0;
 398 }
 399
 400 static void append_irq_action(int pil, struct irqaction *action)
 401 {
 402         struct irqaction **pp = irq_action + pil;
 403
 404         while (*pp)
 405                 pp = &((*pp)->next);
 406         *pp = action;
 407 }
 408
 409 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 410 {
 411         struct irq_desc *desc = bucket->irq_info;
 412         int max_irq, i;
 413
 414         max_irq = 1;
 415         if (bucket->flags & IBF_PCI)
 416                 max_irq = MAX_IRQ_DESC_ACTION;
 417         for (i = 0; i < max_irq; i++) {
 418                 struct irqaction *p = &desc->action[i];
 419                 u32 mask = (1 << i);
 420
 421                 if (desc->action_active_mask & mask)
 422                         continue;
 423
 424                 desc->action_active_mask |= mask;
 425                 return p;
 426         }
 427         return NULL;
 428 }
 429
 430 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 431                 unsigned long irqflags, const char *name, void *dev_id)
 432 {
 433         struct irqaction *action;
 434         struct ino_bucket *bucket = __bucket(irq);
 435         unsigned long flags;
 436         int pending = 0;
 437
 438         if (unlikely(!handler))
 439                 return -EINVAL;
 440
 441         if (unlikely(!bucket->irq_info))
 442                 return -ENODEV;
 443
 444         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 445                 /*
 446                  * This function might sleep, we want to call it first,
 447                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 448                  * random driver's kmalloc will fail, but it is safe.
 449                  * If already initialized, random driver will not reinit.
 450                  * Yes, this might clear the entropy pool if the wrong
 451                  * driver is attempted to be loaded, without actually
 452                  * installing a new handler, but is this really a problem,
 453                  * only the sysadmin is able to do this.
 454                  */
 455                 rand_initialize_irq(irq);
 456         }
 457
 458         spin_lock_irqsave(&irq_action_lock, flags);
 459
 460         if (check_irq_sharing(bucket->pil, irqflags)) {
 461                 spin_unlock_irqrestore(&irq_action_lock, flags);
 462                 return -EBUSY;
 463         }
 464
 465         action = get_action_slot(bucket);
 466         if (!action) {
 467                 spin_unlock_irqrestore(&irq_action_lock, flags);
 468                 return -ENOMEM;
 469         }
 470
 471         bucket->flags |= IBF_ACTIVE;
 472         pending = 0;
 473         if (bucket != &pil0_dummy_bucket) {
 474                 pending = bucket->pending;
 475                 if (pending)
 476                         bucket->pending = 0;
 477         }
 478
 479         action->handler = handler;
 480         action->flags = irqflags;
 481         action->name = name;
 482         action->next = NULL;
 483         action->dev_id = dev_id;
 484         put_ino_in_irqaction(action, irq);
 485         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 486
 487         append_irq_action(bucket->pil, action);
 488
 489         enable_irq(irq);
 490
 491         /* We ate the IVEC already, this makes sure it does not get lost. */
 492         if (pending) {
 493                 atomic_bucket_insert(bucket);
 494                 set_softint(1 << bucket->pil);
 495         }
 496
 497         spin_unlock_irqrestore(&irq_action_lock, flags);
 498
 499         if (bucket != &pil0_dummy_bucket)
 500                 register_irq_proc(__irq_ino(irq));
 501
 502 #ifdef CONFIG_SMP
 503         distribute_irqs();
 504 #endif
 505         return 0;
 506 }
 507
 508 EXPORT_SYMBOL(request_irq);
 509
 510 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 511 {
 512         struct ino_bucket *bucket = __bucket(irq);
 513         struct irqaction *action, **pp;
 514
 515         pp = irq_action + bucket->pil;
 516         action = *pp;
 517         if (unlikely(!action))
 518                 return NULL;
 519
 520         if (unlikely(!action->handler)) {
 521                 printk("Freeing free IRQ %d\n", bucket->pil);
 522                 return NULL;
 523         }
 524
 525         while (action && action->dev_id != dev_id) {
 526                 pp = &action->next;
 527                 action = *pp;
 528         }
 529
 530         if (likely(action))
 531                 *pp = action->next;
 532
 533         return action;
 534 }
 535
 536 void free_irq(unsigned int irq, void *dev_id)
 537 {
 538         struct irqaction *action;
 539         struct ino_bucket *bucket;
 540         unsigned long flags;
 541
 542         spin_lock_irqsave(&irq_action_lock, flags);
 543
 544         action = unlink_irq_action(irq, dev_id);
 545
 546         spin_unlock_irqrestore(&irq_action_lock, flags);
 547
 548         if (unlikely(!action))
 549                 return;
 550
 551         synchronize_irq(irq);
 552
 553         spin_lock_irqsave(&irq_action_lock, flags);
 554
 555         bucket = __bucket(irq);
 556         if (bucket != &pil0_dummy_bucket) {
 557                 struct irq_desc *desc = bucket->irq_info;
 558                 int ent, i;
 559
 560                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 561                         struct irqaction *p = &desc->action[i];
 562
 563                         if (p == action) {
 564                                 desc->action_active_mask &= ~(1 << i);
 565                                 break;
 566                         }
 567                 }
 568
 569                 if (!desc->action_active_mask) {
 570                         unsigned long imap = bucket->imap;
 571
 572                         /* This unique interrupt source is now inactive. */
 573                         bucket->flags &= ~IBF_ACTIVE;
 574
 575                         /* See if any other buckets share this bucket's IMAP
 576                          * and are still active.
 577                          */
 578                         for (ent = 0; ent < NUM_IVECS; ent++) {
 579                                 struct ino_bucket *bp = &ivector_table[ent];
 580                                 if (bp != bucket        &&
 581                                     bp->imap == imap    &&
 582                                     (bp->flags & IBF_ACTIVE) != 0)
 583                                         break;
 584                         }
 585
 586                         /* Only disable when no other sub-irq levels of
 587                          * the same IMAP are active.
 588                          */
 589                         if (ent == NUM_IVECS)
 590                                 disable_irq(irq);
 591                 }
 592         }
 593
 594         spin_unlock_irqrestore(&irq_action_lock, flags);
 595 }
 596
 597 EXPORT_SYMBOL(free_irq);
 598
 599 #ifdef CONFIG_SMP
 600 void synchronize_irq(unsigned int irq)
 601 {
 602         struct ino_bucket *bucket = __bucket(irq);
 603
 604 #if 0
 605         /* The following is how I wish I could implement this.
 606          * Unfortunately the ICLR registers are read-only, you can
 607          * only write ICLR_foo values to them.  To get the current
 608          * IRQ status you would need to get at the IRQ diag registers
 609          * in the PCI/SBUS controller and the layout of those vary
 610          * from one controller to the next, sigh... -DaveM
 611          */
 612         unsigned long iclr = bucket->iclr;
 613
 614         while (1) {
 615                 u32 tmp = upa_readl(iclr);
 616
 617                 if (tmp == ICLR_TRANSMIT ||
 618                     tmp == ICLR_PENDING) {
 619                         cpu_relax();
 620                         continue;
 621                 }
 622                 break;
 623         }
 624 #else
 625         /* So we have to do this with a INPROGRESS bit just like x86.  */
 626         while (bucket->flags & IBF_INPROGRESS)
 627                 cpu_relax();
 628 #endif
 629 }
 630 #endif /* CONFIG_SMP */
 631
 632 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 633 {
 634         struct irq_desc *desc = bp->irq_info;
 635         unsigned char flags = bp->flags;
 636         u32 action_mask, i;
 637         int random;
 638
 639         bp->flags |= IBF_INPROGRESS;
 640
 641         if (unlikely(!(flags & IBF_ACTIVE))) {
 642                 bp->pending = 1;
 643                 goto out;
 644         }
 645
 646         if (desc->pre_handler)
 647                 desc->pre_handler(bp,
 648                                   desc->pre_handler_arg1,
 649                                   desc->pre_handler_arg2);
 650
 651         action_mask = desc->action_active_mask;
 652         random = 0;
 653         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 654                 struct irqaction *p = &desc->action[i];
 655                 u32 mask = (1 << i);
 656
 657                 if (!(action_mask & mask))
 658                         continue;
 659
 660                 action_mask &= ~mask;
 661
 662                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 663                         random |= p->flags;
 664
 665                 if (!action_mask)
 666                         break;
 667         }
 668         if (bp->pil != 0) {
 669                 if (tlb_type == hypervisor) {
 670                         unsigned int ino = __irq_ino(bp);
 671                         int err;
 672
 673                         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 674                         if (err != HV_EOK)
 675                                 printk("sun4v_intr_setstate(%x): "
 676                                        "err(%d)\n", ino, err);
 677                 } else {
 678                         upa_writel(ICLR_IDLE, bp->iclr);
 679                 }
 680
 681                 /* Test and add entropy */
 682                 if (random & SA_SAMPLE_RANDOM)
 683                         add_interrupt_randomness(irq);
 684         }
 685 out:
 686         bp->flags &= ~IBF_INPROGRESS;
 687 }
 688
 689 void handler_irq(int irq, struct pt_regs *regs)
 690 {
 691         struct ino_bucket *bp;
 692         int cpu = smp_processor_id();
 693
 694 #ifndef CONFIG_SMP
 695         /*
 696          * Check for TICK_INT on level 14 softint.
 697          */
 698         {
 699                 unsigned long clr_mask = 1 << irq;
 700                 unsigned long tick_mask = tick_ops->softint_mask;
 701
 702                 if ((irq == 14) && (get_softint() & tick_mask)) {
 703                         irq = 0;
 704                         clr_mask = tick_mask;
 705                 }
 706                 clear_softint(clr_mask);
 707         }
 708 #else
 709         clear_softint(1 << irq);
 710 #endif
 711
 712         irq_enter();
 713         kstat_this_cpu.irqs[irq]++;
 714
 715         /* Sliiiick... */
 716 #ifndef CONFIG_SMP
 717         bp = ((irq != 0) ?
 718               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 719               &pil0_dummy_bucket);
 720 #else
 721         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 722 #endif
 723         while (bp) {
 724                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 725
 726                 bp->irq_chain = 0;
 727                 process_bucket(irq, bp, regs);
 728                 bp = nbp;
 729         }
 730         irq_exit();
 731 }
 732
 733 #ifdef CONFIG_BLK_DEV_FD
 734 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 735
 736 /* XXX No easy way to include asm/floppy.h XXX */
 737 extern unsigned char *pdma_vaddr;
 738 extern unsigned long pdma_size;
 739 extern volatile int doing_pdma;
 740 extern unsigned long fdc_status;
 741
 742 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 743 {
 744         if (likely(doing_pdma)) {
 745                 void __iomem *stat = (void __iomem *) fdc_status;
 746                 unsigned char *vaddr = pdma_vaddr;
 747                 unsigned long size = pdma_size;
 748                 u8 val;
 749
 750                 while (size) {
 751                         val = readb(stat);
 752                         if (unlikely(!(val & 0x80))) {
 753                                 pdma_vaddr = vaddr;
 754                                 pdma_size = size;
 755                                 return IRQ_HANDLED;
 756                         }
 757                         if (unlikely(!(val & 0x20))) {
 758                                 pdma_vaddr = vaddr;
 759                                 pdma_size = size;
 760                                 doing_pdma = 0;
 761                                 goto main_interrupt;
 762                         }
 763                         if (val & 0x40) {
 764                                 /* read */
 765                                 *vaddr++ = readb(stat + 1);
 766                         } else {
 767                                 unsigned char data = *vaddr++;
 768
 769                                 /* write */
 770                                 writeb(data, stat + 1);
 771                         }
 772                         size--;
 773                 }
 774
 775                 pdma_vaddr = vaddr;
 776                 pdma_size = size;
 777
 778                 /* Send Terminal Count pulse to floppy controller. */
 779                 val = readb(auxio_register);
 780                 val |= AUXIO_AUX1_FTCNT;
 781                 writeb(val, auxio_register);
 782                 val &= ~AUXIO_AUX1_FTCNT;
 783                 writeb(val, auxio_register);
 784
 785                 doing_pdma = 0;
 786         }
 787
 788 main_interrupt:
 789         return floppy_interrupt(irq, dev_cookie, regs);
 790 }
 791 EXPORT_SYMBOL(sparc_floppy_irq);
 792 #endif
 793
 794 /* We really don't need these at all on the Sparc.  We only have
 795  * stubs here because they are exported to modules.
 796  */
 797 unsigned long probe_irq_on(void)
 798 {
 799         return 0;
 800 }
 801
 802 EXPORT_SYMBOL(probe_irq_on);
 803
 804 int probe_irq_off(unsigned long mask)
 805 {
 806         return 0;
 807 }
 808
 809 EXPORT_SYMBOL(probe_irq_off);
 810
 811 #ifdef CONFIG_SMP
 812 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 813 {
 814         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 815
 816         while (!cpu_online(goal_cpu)) {
 817                 if (++goal_cpu >= NR_CPUS)
 818                         goal_cpu = 0;
 819         }
 820
 821         if (tlb_type == hypervisor) {
 822                 unsigned int ino = __irq_ino(bucket);
 823
 824                 sun4v_intr_settarget(ino, goal_cpu);
 825                 sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 826         } else {
 827                 unsigned long imap = bucket->imap;
 828                 unsigned int tid = sun4u_compute_tid(imap, goal_cpu);
 829
 830                 upa_writel(tid | IMAP_VALID, imap);
 831         }
 832
 833         do {
 834                 if (++goal_cpu >= NR_CPUS)
 835                         goal_cpu = 0;
 836         } while (!cpu_online(goal_cpu));
 837
 838         return goal_cpu;
 839 }
 840
 841 /* Called from request_irq. */
 842 static void distribute_irqs(void)
 843 {
 844         unsigned long flags;
 845         int cpu, level;
 846
 847         spin_lock_irqsave(&irq_action_lock, flags);
 848         cpu = 0;
 849
 850         /*
 851          * Skip the timer at [0], and very rare error/power intrs at [15].
 852          * Also level [12], it causes problems on Ex000 systems.
 853          */
 854         for (level = 1; level < NR_IRQS; level++) {
 855                 struct irqaction *p = irq_action[level];
 856
 857                 if (level == 12)
 858                         continue;
 859
 860                 while(p) {
 861                         cpu = retarget_one_irq(p, cpu);
 862                         p = p->next;
 863                 }
 864         }
 865         spin_unlock_irqrestore(&irq_action_lock, flags);
 866 }
 867 #endif
 868
 869 struct sun5_timer {
 870         u64     count0;
 871         u64     limit0;
 872         u64     count1;
 873         u64     limit1;
 874 };
 875
 876 static struct sun5_timer *prom_timers;
 877 static u64 prom_limit0, prom_limit1;
 878
 879 static void map_prom_timers(void)
 880 {
 881         unsigned int addr[3];
 882         int tnode, err;
 883
 884         /* PROM timer node hangs out in the top level of device siblings... */
 885         tnode = prom_finddevice("/counter-timer");
 886
 887         /* Assume if node is not present, PROM uses different tick mechanism
 888          * which we should not care about.
 889          */
 890         if (tnode == 0 || tnode == -1) {
 891                 prom_timers = (struct sun5_timer *) 0;
 892                 return;
 893         }
 894
 895         /* If PROM is really using this, it must be mapped by him. */
 896         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 897         if (err == -1) {
 898                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 899                 prom_timers = (struct sun5_timer *) 0;
 900                 return;
 901         }
 902         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 903 }
 904
 905 static void kill_prom_timer(void)
 906 {
 907         if (!prom_timers)
 908                 return;
 909
 910         /* Save them away for later. */
 911         prom_limit0 = prom_timers->limit0;
 912         prom_limit1 = prom_timers->limit1;
 913
 914         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 915          * We turn both off here just to be paranoid.
 916          */
 917         prom_timers->limit0 = 0;
 918         prom_timers->limit1 = 0;
 919
 920         /* Wheee, eat the interrupt packet too... */
 921         __asm__ __volatile__(
 922 "       mov     0x40, %%g2\n"
 923 "       ldxa    [%%g0] %0, %%g1\n"
 924 "       ldxa    [%%g2] %1, %%g1\n"
 925 "       stxa    %%g0, [%%g0] %0\n"
 926 "       membar  #Sync\n"
 927         : /* no outputs */
 928         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 929         : "g1", "g2");
 930 }
 931
 932 void init_irqwork_curcpu(void)
 933 {
 934         int cpu = hard_smp_processor_id();
 935
 936         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 937 }
 938
 939 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
 940 {
 941         unsigned long num_entries = 128;
 942         unsigned long status;
 943
 944         status = sun4v_cpu_qconf(type, paddr, num_entries);
 945         if (status != HV_EOK) {
 946                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 947                             "err %lu\n", type, paddr, num_entries, status);
 948                 prom_halt();
 949         }
 950 }
 951
 952 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
 953 {
 954         struct trap_per_cpu *tb = &trap_block[this_cpu];
 955
 956         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 957         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 958         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 959         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 960 }
 961
 962 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
 963 {
 964         void *page;
 965
 966         if (use_bootmem)
 967                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 968         else
 969                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 970
 971         if (!page) {
 972                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 973                 prom_halt();
 974         }
 975
 976         *pa_ptr = __pa(page);
 977 }
 978
 979 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
 980 {
 981         void *page;
 982
 983         if (use_bootmem)
 984                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 985         else
 986                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 987
 988         if (!page) {
 989                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 990                 prom_halt();
 991         }
 992
 993         *pa_ptr = __pa(page);
 994 }
 995
 996 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
 997 {
 998 #ifdef CONFIG_SMP
 999         void *page;
1000
1001         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1002
1003         if (use_bootmem)
1004                 page = alloc_bootmem_low_pages(PAGE_SIZE);
1005         else
1006                 page = (void *) get_zeroed_page(GFP_ATOMIC);
1007
1008         if (!page) {
1009                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1010                 prom_halt();
1011         }
1012
1013         tb->cpu_mondo_block_pa = __pa(page);
1014         tb->cpu_list_pa = __pa(page + 64);
1015 #endif
1016 }
1017
1018 /* Allocate and register the mondo and error queues for this cpu.  */
1019 void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
1020 {
1021         struct trap_per_cpu *tb = &trap_block[cpu];
1022
1023         if (alloc) {
1024                 alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
1025                 alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
1026                 alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
1027                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
1028                 alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
1029                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
1030
1031                 init_cpu_send_mondo_info(tb, use_bootmem);
1032         }
1033
1034         if (load) {
1035                 if (cpu != hard_smp_processor_id()) {
1036                         prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1037                                     cpu, hard_smp_processor_id());
1038                         prom_halt();
1039                 }
1040                 sun4v_register_mondo_queues(cpu);
1041         }
1042 }
1043
1044 /* Only invoked on boot processor. */
1045 void __init init_IRQ(void)
1046 {
1047         map_prom_timers();
1048         kill_prom_timer();
1049         memset(&ivector_table[0], 0, sizeof(ivector_table));
1050
1051         if (tlb_type == hypervisor)
1052                 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1053
1054         /* We need to clear any IRQ's pending in the soft interrupt
1055          * registers, a spurious one could be left around from the
1056          * PROM timer which we just disabled.
1057          */
1058         clear_softint(get_softint());
1059
1060         /* Now that ivector table is initialized, it is safe
1061          * to receive IRQ vector traps.  We will normally take
1062          * one or two right now, in case some device PROM used
1063          * to boot us wants to speak to us.  We just ignore them.
1064          */
1065         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1066                              "or        %%g1, %0, %%g1\n\t"
1067                              "wrpr      %%g1, 0x0, %%pstate"
1068                              : /* No outputs */
1069                              : "i" (PSTATE_IE)
1070                              : "g1");
1071 }
1072
1073 static struct proc_dir_entry * root_irq_dir;
1074 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1075
1076 #ifdef CONFIG_SMP
1077
1078 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1079                         int count, int *eof, void *data)
1080 {
1081         struct ino_bucket *bp = ivector_table + (long)data;
1082         struct irq_desc *desc = bp->irq_info;
1083         struct irqaction *ap = desc->action;
1084         cpumask_t mask;
1085         int len;
1086
1087         mask = get_smpaff_in_irqaction(ap);
1088         if (cpus_empty(mask))
1089                 mask = cpu_online_map;
1090
1091         len = cpumask_scnprintf(page, count, mask);
1092         if (count - len < 2)
1093                 return -EINVAL;
1094         len += sprintf(page + len, "\n");
1095         return len;
1096 }
1097
1098 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1099 {
1100         struct ino_bucket *bp = ivector_table + irq;
1101         struct irq_desc *desc = bp->irq_info;
1102         struct irqaction *ap = desc->action;
1103
1104         /* Users specify affinity in terms of hw cpu ids.
1105          * As soon as we do this, handler_irq() might see and take action.
1106          */
1107         put_smpaff_in_irqaction(ap, hw_aff);
1108
1109         /* Migration is simply done by the next cpu to service this
1110          * interrupt.
1111          */
1112 }
1113
1114 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1115                                         unsigned long count, void *data)
1116 {
1117         int irq = (long) data, full_count = count, err;
1118         cpumask_t new_value;
1119
1120         err = cpumask_parse(buffer, count, new_value);
1121
1122         /*
1123          * Do not allow disabling IRQs completely - it's a too easy
1124          * way to make the system unusable accidentally :-) At least
1125          * one online CPU still has to be targeted.
1126          */
1127         cpus_and(new_value, new_value, cpu_online_map);
1128         if (cpus_empty(new_value))
1129                 return -EINVAL;
1130
1131         set_intr_affinity(irq, new_value);
1132
1133         return full_count;
1134 }
1135
1136 #endif
1137
1138 #define MAX_NAMELEN 10
1139
1140 static void register_irq_proc (unsigned int irq)
1141 {
1142         char name [MAX_NAMELEN];
1143
1144         if (!root_irq_dir || irq_dir[irq])
1145                 return;
1146
1147         memset(name, 0, MAX_NAMELEN);
1148         sprintf(name, "%x", irq);
1149
1150         /* create /proc/irq/1234 */
1151         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1152
1153 #ifdef CONFIG_SMP
1154         /* XXX SMP affinity not supported on starfire yet. */
1155         if (this_is_starfire == 0) {
1156                 struct proc_dir_entry *entry;
1157
1158                 /* create /proc/irq/1234/smp_affinity */
1159                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1160
1161                 if (entry) {
1162                         entry->nlink = 1;
1163                         entry->data = (void *)(long)irq;
1164                         entry->read_proc = irq_affinity_read_proc;
1165                         entry->write_proc = irq_affinity_write_proc;
1166                 }
1167         }
1168 #endif
1169 }
1170
1171 void init_irq_proc (void)
1172 {
1173         /* create /proc/irq */
1174         root_irq_dir = proc_mkdir("irq", NULL);
1175 }
1176