1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/smp_lock.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
22 #include <asm/uaccess.h>
24 #include <asm/pgtable.h>
30 unsigned long pci_memspace_mask = 0xffffffffUL;
33 /* A "nop" PCI implementation. */
34 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
35 unsigned long off, unsigned long len,
40 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
41 unsigned long off, unsigned long len,
48 /* List of all PCI controllers found in the system. */
49 struct pci_controller_info *pci_controller_root = NULL;
51 /* Each PCI controller found gets a unique index. */
52 int pci_num_controllers = 0;
54 volatile int pci_poke_in_progress;
55 volatile int pci_poke_cpu = -1;
56 volatile int pci_poke_faulted;
58 static DEFINE_SPINLOCK(pci_poke_lock);
60 void pci_config_read8(u8 *addr, u8 *ret)
65 spin_lock_irqsave(&pci_poke_lock, flags);
66 pci_poke_cpu = smp_processor_id();
67 pci_poke_in_progress = 1;
69 __asm__ __volatile__("membar #Sync\n\t"
70 "lduba [%1] %2, %0\n\t"
73 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
75 pci_poke_in_progress = 0;
77 if (!pci_poke_faulted)
79 spin_unlock_irqrestore(&pci_poke_lock, flags);
82 void pci_config_read16(u16 *addr, u16 *ret)
87 spin_lock_irqsave(&pci_poke_lock, flags);
88 pci_poke_cpu = smp_processor_id();
89 pci_poke_in_progress = 1;
91 __asm__ __volatile__("membar #Sync\n\t"
92 "lduha [%1] %2, %0\n\t"
95 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
97 pci_poke_in_progress = 0;
99 if (!pci_poke_faulted)
101 spin_unlock_irqrestore(&pci_poke_lock, flags);
104 void pci_config_read32(u32 *addr, u32 *ret)
109 spin_lock_irqsave(&pci_poke_lock, flags);
110 pci_poke_cpu = smp_processor_id();
111 pci_poke_in_progress = 1;
112 pci_poke_faulted = 0;
113 __asm__ __volatile__("membar #Sync\n\t"
114 "lduwa [%1] %2, %0\n\t"
117 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
119 pci_poke_in_progress = 0;
121 if (!pci_poke_faulted)
123 spin_unlock_irqrestore(&pci_poke_lock, flags);
126 void pci_config_write8(u8 *addr, u8 val)
130 spin_lock_irqsave(&pci_poke_lock, flags);
131 pci_poke_cpu = smp_processor_id();
132 pci_poke_in_progress = 1;
133 pci_poke_faulted = 0;
134 __asm__ __volatile__("membar #Sync\n\t"
135 "stba %0, [%1] %2\n\t"
138 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
140 pci_poke_in_progress = 0;
142 spin_unlock_irqrestore(&pci_poke_lock, flags);
145 void pci_config_write16(u16 *addr, u16 val)
149 spin_lock_irqsave(&pci_poke_lock, flags);
150 pci_poke_cpu = smp_processor_id();
151 pci_poke_in_progress = 1;
152 pci_poke_faulted = 0;
153 __asm__ __volatile__("membar #Sync\n\t"
154 "stha %0, [%1] %2\n\t"
157 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
159 pci_poke_in_progress = 0;
161 spin_unlock_irqrestore(&pci_poke_lock, flags);
164 void pci_config_write32(u32 *addr, u32 val)
168 spin_lock_irqsave(&pci_poke_lock, flags);
169 pci_poke_cpu = smp_processor_id();
170 pci_poke_in_progress = 1;
171 pci_poke_faulted = 0;
172 __asm__ __volatile__("membar #Sync\n\t"
173 "stwa %0, [%1] %2\n\t"
176 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
178 pci_poke_in_progress = 0;
180 spin_unlock_irqrestore(&pci_poke_lock, flags);
183 /* Probe for all PCI controllers in the system. */
184 extern void sabre_init(struct device_node *, const char *);
185 extern void psycho_init(struct device_node *, const char *);
186 extern void schizo_init(struct device_node *, const char *);
187 extern void schizo_plus_init(struct device_node *, const char *);
188 extern void tomatillo_init(struct device_node *, const char *);
189 extern void sun4v_pci_init(struct device_node *, const char *);
193 void (*init)(struct device_node *, const char *);
194 } pci_controller_table[] __initdata = {
195 { "SUNW,sabre", sabre_init },
196 { "pci108e,a000", sabre_init },
197 { "pci108e,a001", sabre_init },
198 { "SUNW,psycho", psycho_init },
199 { "pci108e,8000", psycho_init },
200 { "SUNW,schizo", schizo_init },
201 { "pci108e,8001", schizo_init },
202 { "SUNW,schizo+", schizo_plus_init },
203 { "pci108e,8002", schizo_plus_init },
204 { "SUNW,tomatillo", tomatillo_init },
205 { "pci108e,a801", tomatillo_init },
206 { "SUNW,sun4v-pci", sun4v_pci_init },
208 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
209 sizeof(pci_controller_table[0]))
211 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
219 pci_controller_table[i].init(dp, model_name);
227 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
231 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
232 if (!strncmp(model_name,
233 pci_controller_table[i].model_name,
241 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
243 struct device_node *dp;
246 for_each_node_by_name(dp, "pci") {
247 struct property *prop;
250 prop = of_find_property(dp, "model", &len);
252 prop = of_find_property(dp, "compatible", &len);
255 const char *model = prop->value;
258 /* Our value may be a multi-valued string in the
259 * case of some compatible properties. For sanity,
260 * only try the first one.
262 while (model[item_len] && len) {
267 if (handler(model, item_len, dp))
276 /* Is there some PCI controller in the system? */
277 int __init pcic_present(void)
279 return pci_controller_scan(pci_is_controller);
282 struct pci_iommu_ops *pci_iommu_ops;
283 EXPORT_SYMBOL(pci_iommu_ops);
285 extern struct pci_iommu_ops pci_sun4u_iommu_ops,
288 /* Find each controller in the system, attach and initialize
289 * software state structure for each and link into the
290 * pci_controller_root. Setup the controller enough such
291 * that bus scanning can be done.
293 static void __init pci_controller_probe(void)
295 if (tlb_type == hypervisor)
296 pci_iommu_ops = &pci_sun4v_iommu_ops;
298 pci_iommu_ops = &pci_sun4u_iommu_ops;
300 printk("PCI: Probing for controllers.\n");
302 pci_controller_scan(pci_controller_init);
305 static unsigned long pci_parse_of_flags(u32 addr0)
307 unsigned long flags = 0;
309 if (addr0 & 0x02000000) {
310 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
311 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
312 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
313 if (addr0 & 0x40000000)
314 flags |= IORESOURCE_PREFETCH
315 | PCI_BASE_ADDRESS_MEM_PREFETCH;
316 } else if (addr0 & 0x01000000)
317 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
321 /* The of_device layer has translated all of the assigned-address properties
322 * into physical address resources, we only have to figure out the register
325 static void pci_parse_of_addrs(struct of_device *op,
326 struct device_node *node,
329 struct resource *op_res;
333 addrs = of_get_property(node, "assigned-addresses", &proplen);
336 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
337 op_res = &op->resource[0];
338 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
339 struct resource *res;
343 flags = pci_parse_of_flags(addrs[0]);
347 printk(" start: %lx, end: %lx, i: %x\n",
348 op_res->start, op_res->end, i);
350 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
351 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
352 } else if (i == dev->rom_base_reg) {
353 res = &dev->resource[PCI_ROM_RESOURCE];
354 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
356 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
359 res->start = op_res->start;
360 res->end = op_res->end;
362 res->name = pci_name(dev);
366 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
367 struct device_node *node,
368 struct pci_bus *bus, int devfn)
370 struct dev_archdata *sd;
374 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
378 sd = &dev->dev.archdata;
379 sd->iommu = pbm->iommu;
381 sd->host_controller = pbm;
382 sd->prom_node = node;
383 sd->op = of_find_device_by_node(node);
384 sd->msi_num = 0xffffffff;
386 type = of_get_property(node, "device_type", NULL);
390 printk(" create device, devfn: %x, type: %s\n", devfn, type);
394 dev->dev.parent = bus->bridge;
395 dev->dev.bus = &pci_bus_type;
397 dev->multifunction = 0; /* maybe a lie? */
399 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
400 dev->device = of_getintprop_default(node, "device-id", 0xffff);
401 dev->subsystem_vendor =
402 of_getintprop_default(node, "subsystem-vendor-id", 0);
403 dev->subsystem_device =
404 of_getintprop_default(node, "subsystem-id", 0);
406 dev->cfg_size = pci_cfg_space_size(dev);
408 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
409 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
410 dev->class = of_getintprop_default(node, "class-code", 0);
412 printk(" class: 0x%x\n", dev->class);
414 dev->current_state = 4; /* unknown power state */
415 dev->error_state = pci_channel_io_normal;
417 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
418 /* a PCI-PCI bridge */
419 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
420 dev->rom_base_reg = PCI_ROM_ADDRESS1;
421 } else if (!strcmp(type, "cardbus")) {
422 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
424 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
425 dev->rom_base_reg = PCI_ROM_ADDRESS;
427 dev->irq = sd->op->irqs[0];
428 if (dev->irq == 0xffffffff)
429 dev->irq = PCI_IRQ_NONE;
432 pci_parse_of_addrs(sd->op, node, dev);
434 printk(" adding to system ...\n");
436 pci_device_add(dev, bus);
441 static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
442 struct device_node *node,
443 struct pci_bus *bus);
445 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
447 void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
448 struct device_node *node,
452 const u32 *busrange, *ranges;
454 struct resource *res;
458 printk("of_scan_pci_bridge(%s)\n", node->full_name);
460 /* parse bus-range property */
461 busrange = of_get_property(node, "bus-range", &len);
462 if (busrange == NULL || len != 8) {
463 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
467 ranges = of_get_property(node, "ranges", &len);
468 if (ranges == NULL) {
469 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
474 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
476 printk(KERN_ERR "Failed to create pci bus for %s\n",
481 bus->primary = dev->bus->number;
482 bus->subordinate = busrange[1];
485 /* parse ranges property */
486 /* PCI #address-cells == 3 and #size-cells == 2 always */
487 res = &dev->resource[PCI_BRIDGE_RESOURCES];
488 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
490 bus->resource[i] = res;
494 for (; len >= 32; len -= 32, ranges += 8) {
495 struct resource *root;
497 flags = pci_parse_of_flags(ranges[0]);
498 size = GET_64BIT(ranges, 6);
499 if (flags == 0 || size == 0)
501 if (flags & IORESOURCE_IO) {
502 res = bus->resource[0];
504 printk(KERN_ERR "PCI: ignoring extra I/O range"
505 " for bridge %s\n", node->full_name);
508 root = &pbm->io_space;
510 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
511 printk(KERN_ERR "PCI: too many memory ranges"
512 " for bridge %s\n", node->full_name);
515 res = bus->resource[i];
517 root = &pbm->mem_space;
520 res->start = GET_64BIT(ranges, 1);
521 res->end = res->start + size - 1;
524 /* Another way to implement this would be to add an of_device
525 * layer routine that can calculate a resource for a given
526 * range property value in a PCI device.
528 pbm->parent->resource_adjust(dev, res, root);
530 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
532 printk(" bus name: %s\n", bus->name);
534 pci_of_scan_bus(pbm, node, bus);
537 static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
538 struct device_node *node,
541 struct device_node *child;
546 printk("PCI: scan_bus[%s] bus no %d\n",
547 node->full_name, bus->number);
550 while ((child = of_get_next_child(node, child)) != NULL) {
551 printk(" * %s\n", child->full_name);
552 reg = of_get_property(child, "reg", ®len);
553 if (reg == NULL || reglen < 20)
555 devfn = (reg[0] >> 8) & 0xff;
557 /* create a new pci_dev for this device */
558 dev = of_create_pci_dev(pbm, child, bus, devfn);
561 printk("PCI: dev header type: %x\n", dev->hdr_type);
563 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
564 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
565 of_scan_pci_bridge(pbm, child, dev);
570 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
572 struct pci_dev *pdev;
573 struct device_node *dp;
575 pdev = to_pci_dev(dev);
576 dp = pdev->dev.archdata.prom_node;
578 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
581 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
583 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
588 list_for_each_entry(dev, &bus->devices, bus_list) {
589 /* we don't really care if we can create this file or
590 * not, but we need to assign the result of the call
591 * or the world will fall under alien invasion and
592 * everybody will be frozen on a spaceship ready to be
593 * eaten on alpha centauri by some green and jelly
596 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
600 struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
602 struct pci_controller_info *p = pbm->parent;
603 struct device_node *node = pbm->prom_node;
606 printk("PCI: Scanning PBM %s\n", node->full_name);
608 /* XXX parent device? XXX */
609 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
611 printk(KERN_ERR "Failed to create bus for %s\n",
615 bus->secondary = pbm->pci_first_busno;
616 bus->subordinate = pbm->pci_last_busno;
618 bus->resource[0] = &pbm->io_space;
619 bus->resource[1] = &pbm->mem_space;
621 pci_of_scan_bus(pbm, node, bus);
622 pci_bus_add_devices(bus);
623 pci_bus_register_of_sysfs(bus);
628 static void __init pci_scan_each_controller_bus(void)
630 struct pci_controller_info *p;
632 for (p = pci_controller_root; p; p = p->next)
636 extern void power_init(void);
638 static int __init pcibios_init(void)
640 pci_controller_probe();
641 if (pci_controller_root == NULL)
644 pci_scan_each_controller_bus();
653 subsys_initcall(pcibios_init);
655 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
657 struct pci_pbm_info *pbm = pbus->sysdata;
659 /* Generic PCI bus probing sets these to point at
660 * &io{port,mem}_resouce which is wrong for us.
662 pbus->resource[0] = &pbm->io_space;
663 pbus->resource[1] = &pbm->mem_space;
666 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
668 struct pci_pbm_info *pbm = pdev->bus->sysdata;
669 struct resource *root = NULL;
671 if (r->flags & IORESOURCE_IO)
672 root = &pbm->io_space;
673 if (r->flags & IORESOURCE_MEM)
674 root = &pbm->mem_space;
679 void pcibios_update_irq(struct pci_dev *pdev, int irq)
683 void pcibios_align_resource(void *data, struct resource *res,
684 resource_size_t size, resource_size_t align)
688 int pcibios_enable_device(struct pci_dev *dev, int mask)
693 pci_read_config_word(dev, PCI_COMMAND, &cmd);
696 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
697 struct resource *res = &dev->resource[i];
699 /* Only set up the requested stuff */
700 if (!(mask & (1<<i)))
703 if (res->flags & IORESOURCE_IO)
704 cmd |= PCI_COMMAND_IO;
705 if (res->flags & IORESOURCE_MEM)
706 cmd |= PCI_COMMAND_MEMORY;
710 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
712 /* Enable the appropriate bits in the PCI command register. */
713 pci_write_config_word(dev, PCI_COMMAND, cmd);
718 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
719 struct resource *res)
721 struct pci_pbm_info *pbm = pdev->bus->sysdata;
722 struct resource zero_res, *root;
726 zero_res.flags = res->flags;
728 if (res->flags & IORESOURCE_IO)
729 root = &pbm->io_space;
731 root = &pbm->mem_space;
733 pbm->parent->resource_adjust(pdev, &zero_res, root);
735 region->start = res->start - zero_res.start;
736 region->end = res->end - zero_res.start;
738 EXPORT_SYMBOL(pcibios_resource_to_bus);
740 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
741 struct pci_bus_region *region)
743 struct pci_pbm_info *pbm = pdev->bus->sysdata;
744 struct resource *root;
746 res->start = region->start;
747 res->end = region->end;
749 if (res->flags & IORESOURCE_IO)
750 root = &pbm->io_space;
752 root = &pbm->mem_space;
754 pbm->parent->resource_adjust(pdev, res, root);
756 EXPORT_SYMBOL(pcibios_bus_to_resource);
758 char * __devinit pcibios_setup(char *str)
763 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
765 /* If the user uses a host-bridge as the PCI device, he may use
766 * this to perform a raw mmap() of the I/O or MEM space behind
769 * This can be useful for execution of x86 PCI bios initialization code
770 * on a PCI card, like the xfree86 int10 stuff does.
772 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
773 enum pci_mmap_state mmap_state)
775 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
776 struct pci_controller_info *p;
777 unsigned long space_size, user_offset, user_size;
780 if (p->pbms_same_domain) {
781 unsigned long lowest, highest;
783 lowest = ~0UL; highest = 0UL;
784 if (mmap_state == pci_mmap_io) {
785 if (p->pbm_A.io_space.flags) {
786 lowest = p->pbm_A.io_space.start;
787 highest = p->pbm_A.io_space.end + 1;
789 if (p->pbm_B.io_space.flags) {
790 if (lowest > p->pbm_B.io_space.start)
791 lowest = p->pbm_B.io_space.start;
792 if (highest < p->pbm_B.io_space.end + 1)
793 highest = p->pbm_B.io_space.end + 1;
795 space_size = highest - lowest;
797 if (p->pbm_A.mem_space.flags) {
798 lowest = p->pbm_A.mem_space.start;
799 highest = p->pbm_A.mem_space.end + 1;
801 if (p->pbm_B.mem_space.flags) {
802 if (lowest > p->pbm_B.mem_space.start)
803 lowest = p->pbm_B.mem_space.start;
804 if (highest < p->pbm_B.mem_space.end + 1)
805 highest = p->pbm_B.mem_space.end + 1;
807 space_size = highest - lowest;
810 if (mmap_state == pci_mmap_io) {
811 space_size = (pbm->io_space.end -
812 pbm->io_space.start) + 1;
814 space_size = (pbm->mem_space.end -
815 pbm->mem_space.start) + 1;
819 /* Make sure the request is in range. */
820 user_offset = vma->vm_pgoff << PAGE_SHIFT;
821 user_size = vma->vm_end - vma->vm_start;
823 if (user_offset >= space_size ||
824 (user_offset + user_size) > space_size)
827 if (p->pbms_same_domain) {
828 unsigned long lowest = ~0UL;
830 if (mmap_state == pci_mmap_io) {
831 if (p->pbm_A.io_space.flags)
832 lowest = p->pbm_A.io_space.start;
833 if (p->pbm_B.io_space.flags &&
834 lowest > p->pbm_B.io_space.start)
835 lowest = p->pbm_B.io_space.start;
837 if (p->pbm_A.mem_space.flags)
838 lowest = p->pbm_A.mem_space.start;
839 if (p->pbm_B.mem_space.flags &&
840 lowest > p->pbm_B.mem_space.start)
841 lowest = p->pbm_B.mem_space.start;
843 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
845 if (mmap_state == pci_mmap_io) {
846 vma->vm_pgoff = (pbm->io_space.start +
847 user_offset) >> PAGE_SHIFT;
849 vma->vm_pgoff = (pbm->mem_space.start +
850 user_offset) >> PAGE_SHIFT;
857 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
858 * to the 32-bit pci bus offset for DEV requested by the user.
860 * Basically, the user finds the base address for his device which he wishes
861 * to mmap. They read the 32-bit value from the config space base register,
862 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
863 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
865 * Returns negative error code on failure, zero on success.
867 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
868 enum pci_mmap_state mmap_state)
870 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
871 unsigned long user32 = user_offset & pci_memspace_mask;
872 unsigned long largest_base, this_base, addr32;
875 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
876 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
878 /* Figure out which base address this is for. */
880 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
881 struct resource *rp = &dev->resource[i];
888 if (i == PCI_ROM_RESOURCE) {
889 if (mmap_state != pci_mmap_mem)
892 if ((mmap_state == pci_mmap_io &&
893 (rp->flags & IORESOURCE_IO) == 0) ||
894 (mmap_state == pci_mmap_mem &&
895 (rp->flags & IORESOURCE_MEM) == 0))
899 this_base = rp->start;
901 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
903 if (mmap_state == pci_mmap_io)
906 if (addr32 <= user32 && this_base > largest_base)
907 largest_base = this_base;
910 if (largest_base == 0UL)
913 /* Now construct the final physical address. */
914 if (mmap_state == pci_mmap_io)
915 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
917 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
922 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
925 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
926 enum pci_mmap_state mmap_state)
928 vma->vm_flags |= (VM_IO | VM_RESERVED);
931 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
934 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
935 enum pci_mmap_state mmap_state)
937 /* Our io_remap_pfn_range takes care of this, do nothing. */
940 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
941 * for this architecture. The region in the process to map is described by vm_start
942 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
943 * The pci device structure is provided so that architectures may make mapping
944 * decisions on a per-device or per-bus basis.
946 * Returns a negative error code on failure, zero on success.
948 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
949 enum pci_mmap_state mmap_state,
954 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
958 __pci_mmap_set_flags(dev, vma, mmap_state);
959 __pci_mmap_set_pgprot(dev, vma, mmap_state);
961 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
962 ret = io_remap_pfn_range(vma, vma->vm_start,
964 vma->vm_end - vma->vm_start,
972 /* Return the domain nuber for this pci bus */
974 int pci_domain_nr(struct pci_bus *pbus)
976 struct pci_pbm_info *pbm = pbus->sysdata;
979 if (pbm == NULL || pbm->parent == NULL) {
982 struct pci_controller_info *p = pbm->parent;
985 if (p->pbms_same_domain == 0)
987 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
992 EXPORT_SYMBOL(pci_domain_nr);
994 #ifdef CONFIG_PCI_MSI
995 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
997 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
998 struct pci_controller_info *p = pbm->parent;
1001 if (!pbm->msi_num || !p->setup_msi_irq)
1004 err = p->setup_msi_irq(&virt_irq, pdev, desc);
1011 void arch_teardown_msi_irq(unsigned int virt_irq)
1013 struct msi_desc *entry = get_irq_msi(virt_irq);
1014 struct pci_dev *pdev = entry->dev;
1015 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1016 struct pci_controller_info *p = pbm->parent;
1018 if (!pbm->msi_num || !p->setup_msi_irq)
1021 return p->teardown_msi_irq(virt_irq, pdev);
1023 #endif /* !(CONFIG_PCI_MSI) */
1025 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1027 return pdev->dev.archdata.prom_node;
1029 EXPORT_SYMBOL(pci_device_to_OF_node);
1031 #endif /* !(CONFIG_PCI) */