arch/sparc64/kernel/pci_fire.c

   1 /* pci_fire.c: Sun4u platform PCI-E controller support.
   2  *
   3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
   4  */
   5 #include <linux/kernel.h>
   6 #include <linux/pci.h>
   7 #include <linux/slab.h>
   8 #include <linux/init.h>
   9
  10 #include <asm/pbm.h>
  11 #include <asm/oplib.h>
  12 #include <asm/prom.h>
  13
  14 #include "pci_impl.h"
  15
  16 #define fire_read(__reg) \
  17 ({      u64 __ret; \
  18         __asm__ __volatile__("ldxa [%1] %2, %0" \
  19                              : "=r" (__ret) \
  20                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  21                              : "memory"); \
  22         __ret; \
  23 })
  24 #define fire_write(__reg, __val) \
  25         __asm__ __volatile__("stxa %0, [%1] %2" \
  26                              : /* no outputs */ \
  27                              : "r" (__val), "r" (__reg), \
  28                                "i" (ASI_PHYS_BYPASS_EC_E) \
  29                              : "memory")
  30
  31 /* Fire config space address format is nearly identical to
  32  * that of SCHIZO and PSYCHO, except that in order to accomodate
  33  * PCI-E extended config space the encoding can handle 12 bits
  34  * of register address:
  35  *
  36  *  32     28 27 20 19    15 14      12 11  2  1 0
  37  * -------------------------------------------------
  38  * |0 0 0 0 0| bus | device | function | reg | 0 0 |
  39  * -------------------------------------------------
  40  */
  41 #define FIRE_CONFIG_BASE(PBM)   ((PBM)->config_space)
  42 #define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG)     \
  43         (((unsigned long)(BUS)   << 20) |       \
  44          ((unsigned long)(DEVFN) << 12)  |      \
  45          ((unsigned long)(REG)))
  46
  47 static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm,
  48                                       unsigned char bus,
  49                                       unsigned int devfn,
  50                                       int where)
  51 {
  52         if (!pbm)
  53                 return NULL;
  54         return (void *)
  55                 (FIRE_CONFIG_BASE(pbm) |
  56                  FIRE_CONFIG_ENCODE(bus, devfn, where));
  57 }
  58
  59 /* FIRE PCI configuration space accessors. */
  60
  61 static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
  62                              int where, int size, u32 *value)
  63 {
  64         struct pci_pbm_info *pbm = bus_dev->sysdata;
  65         unsigned char bus = bus_dev->number;
  66         u32 *addr;
  67         u16 tmp16;
  68         u8 tmp8;
  69
  70         if (bus_dev == pbm->pci_bus && devfn == 0x00)
  71                 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
  72                                                     size, value);
  73         switch (size) {
  74         case 1:
  75                 *value = 0xff;
  76                 break;
  77         case 2:
  78                 *value = 0xffff;
  79                 break;
  80         case 4:
  81                 *value = 0xffffffff;
  82                 break;
  83         }
  84
  85         addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
  86         if (!addr)
  87                 return PCIBIOS_SUCCESSFUL;
  88
  89         switch (size) {
  90         case 1:
  91                 pci_config_read8((u8 *)addr, &tmp8);
  92                 *value = tmp8;
  93                 break;
  94
  95         case 2:
  96                 if (where & 0x01) {
  97                         printk("pci_read_config_word: misaligned reg [%x]\n",
  98                                where);
  99                         return PCIBIOS_SUCCESSFUL;
 100                 }
 101                 pci_config_read16((u16 *)addr, &tmp16);
 102                 *value = tmp16;
 103                 break;
 104
 105         case 4:
 106                 if (where & 0x03) {
 107                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 108                                where);
 109                         return PCIBIOS_SUCCESSFUL;
 110                 }
 111
 112                 pci_config_read32(addr, value);
 113                 break;
 114         }
 115         return PCIBIOS_SUCCESSFUL;
 116 }
 117
 118 static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 119                               int where, int size, u32 value)
 120 {
 121         struct pci_pbm_info *pbm = bus_dev->sysdata;
 122         unsigned char bus = bus_dev->number;
 123         u32 *addr;
 124
 125         if (bus_dev == pbm->pci_bus && devfn == 0x00)
 126                 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
 127                                                      size, value);
 128         addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
 129         if (!addr)
 130                 return PCIBIOS_SUCCESSFUL;
 131
 132         switch (size) {
 133         case 1:
 134                 pci_config_write8((u8 *)addr, value);
 135                 break;
 136
 137         case 2:
 138                 if (where & 0x01) {
 139                         printk("pci_write_config_word: misaligned reg [%x]\n",
 140                                where);
 141                         return PCIBIOS_SUCCESSFUL;
 142                 }
 143                 pci_config_write16((u16 *)addr, value);
 144                 break;
 145
 146         case 4:
 147                 if (where & 0x03) {
 148                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 149                                where);
 150                         return PCIBIOS_SUCCESSFUL;
 151                 }
 152
 153                 pci_config_write32(addr, value);
 154         }
 155         return PCIBIOS_SUCCESSFUL;
 156 }
 157
 158 static struct pci_ops pci_fire_ops = {
 159         .read   =       fire_read_pci_cfg,
 160         .write  =       fire_write_pci_cfg,
 161 };
 162
 163 static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
 164 {
 165         pbm->pci_bus = pci_scan_one_pbm(pbm);
 166
 167         /* XXX register error interrupt handlers XXX */
 168 }
 169
 170 #define FIRE_IOMMU_CONTROL      0x40000UL
 171 #define FIRE_IOMMU_TSBBASE      0x40008UL
 172 #define FIRE_IOMMU_FLUSH        0x40100UL
 173 #define FIRE_IOMMU_FLUSHINV     0x40100UL
 174
 175 static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
 176 {
 177         struct iommu *iommu = pbm->iommu;
 178         u32 vdma[2], dma_mask;
 179         u64 control;
 180         int tsbsize;
 181
 182         /* No virtual-dma property on these guys, use largest size.  */
 183         vdma[0] = 0xc0000000; /* base */
 184         vdma[1] = 0x40000000; /* size */
 185         dma_mask = 0xffffffff;
 186         tsbsize = 128;
 187
 188         /* Register addresses. */
 189         iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
 190         iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
 191         iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
 192         iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
 193
 194         /* We use the main control/status register of FIRE as the write
 195          * completion register.
 196          */
 197         iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
 198
 199         /*
 200          * Invalidate TLB Entries.
 201          */
 202         fire_write(iommu->iommu_flushinv, ~(u64)0);
 203
 204         pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
 205
 206         fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
 207
 208         control = fire_read(iommu->iommu_control);
 209         control |= (0x00000400 /* TSB cache snoop enable */     |
 210                     0x00000300 /* Cache mode */                 |
 211                     0x00000002 /* Bypass enable */              |
 212                     0x00000001 /* Translation enable */);
 213         fire_write(iommu->iommu_control, control);
 214 }
 215
 216 /* Based at pbm->controller_regs */
 217 #define FIRE_PARITY_CONTROL     0x470010UL
 218 #define  FIRE_PARITY_ENAB       0x8000000000000000UL
 219 #define FIRE_FATAL_RESET_CTL    0x471028UL
 220 #define  FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
 221 #define  FIRE_FATAL_RESET_MB    0x0000000002000000UL
 222 #define  FIRE_FATAL_RESET_CPE   0x0000000000008000UL
 223 #define  FIRE_FATAL_RESET_APE   0x0000000000004000UL
 224 #define  FIRE_FATAL_RESET_PIO   0x0000000000000040UL
 225 #define  FIRE_FATAL_RESET_JW    0x0000000000000004UL
 226 #define  FIRE_FATAL_RESET_JI    0x0000000000000002UL
 227 #define  FIRE_FATAL_RESET_JR    0x0000000000000001UL
 228 #define FIRE_CORE_INTR_ENABLE   0x471800UL
 229
 230 /* Based at pbm->pbm_regs */
 231 #define FIRE_TLU_CTRL           0x80000UL
 232 #define  FIRE_TLU_CTRL_TIM      0x00000000da000000UL
 233 #define  FIRE_TLU_CTRL_QDET     0x0000000000000100UL
 234 #define  FIRE_TLU_CTRL_CFG      0x0000000000000001UL
 235 #define FIRE_TLU_DEV_CTRL       0x90008UL
 236 #define FIRE_TLU_LINK_CTRL      0x90020UL
 237 #define FIRE_TLU_LINK_CTRL_CLK  0x0000000000000040UL
 238 #define FIRE_LPU_RESET          0xe2008UL
 239 #define FIRE_LPU_LLCFG          0xe2200UL
 240 #define  FIRE_LPU_LLCFG_VC0     0x0000000000000100UL
 241 #define FIRE_LPU_FCTRL_UCTRL    0xe2240UL
 242 #define  FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
 243 #define  FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
 244 #define FIRE_LPU_TXL_FIFOP      0xe2430UL
 245 #define FIRE_LPU_LTSSM_CFG2     0xe2788UL
 246 #define FIRE_LPU_LTSSM_CFG3     0xe2790UL
 247 #define FIRE_LPU_LTSSM_CFG4     0xe2798UL
 248 #define FIRE_LPU_LTSSM_CFG5     0xe27a0UL
 249 #define FIRE_DMC_IENAB          0x31800UL
 250 #define FIRE_DMC_DBG_SEL_A      0x53000UL
 251 #define FIRE_DMC_DBG_SEL_B      0x53008UL
 252 #define FIRE_PEC_IENAB          0x51800UL
 253
 254 static void pci_fire_hw_init(struct pci_pbm_info *pbm)
 255 {
 256         u64 val;
 257
 258         fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
 259                    FIRE_PARITY_ENAB);
 260
 261         fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
 262                    (FIRE_FATAL_RESET_SPARE |
 263                     FIRE_FATAL_RESET_MB |
 264                     FIRE_FATAL_RESET_CPE |
 265                     FIRE_FATAL_RESET_APE |
 266                     FIRE_FATAL_RESET_PIO |
 267                     FIRE_FATAL_RESET_JW |
 268                     FIRE_FATAL_RESET_JI |
 269                     FIRE_FATAL_RESET_JR));
 270
 271         fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
 272
 273         val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
 274         val |= (FIRE_TLU_CTRL_TIM |
 275                 FIRE_TLU_CTRL_QDET |
 276                 FIRE_TLU_CTRL_CFG);
 277         fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
 278         fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
 279         fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
 280                    FIRE_TLU_LINK_CTRL_CLK);
 281
 282         fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
 283         fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
 284                    FIRE_LPU_LLCFG_VC0);
 285         fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
 286                    (FIRE_LPU_FCTRL_UCTRL_N |
 287                     FIRE_LPU_FCTRL_UCTRL_P));
 288         fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
 289                    ((0xffff << 16) | (0x0000 << 0)));
 290         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
 291         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
 292         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
 293                    (2 << 16) | (140 << 8));
 294         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
 295
 296         fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
 297         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
 298         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
 299
 300         fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
 301 }
 302
 303 static void pci_fire_pbm_init(struct pci_controller_info *p,
 304                               struct device_node *dp, u32 portid)
 305 {
 306         const struct linux_prom64_registers *regs;
 307         struct pci_pbm_info *pbm;
 308
 309         if ((portid & 1) == 0)
 310                 pbm = &p->pbm_A;
 311         else
 312                 pbm = &p->pbm_B;
 313
 314         pbm->next = pci_pbm_root;
 315         pci_pbm_root = pbm;
 316
 317         pbm->scan_bus = pci_fire_scan_bus;
 318
 319         pbm->portid = portid;
 320         pbm->parent = p;
 321         pbm->prom_node = dp;
 322         pbm->name = dp->full_name;
 323
 324         regs = of_get_property(dp, "reg", NULL);
 325         pbm->pbm_regs = regs[0].phys_addr;
 326         pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
 327
 328         printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
 329
 330         pci_determine_mem_io_space(pbm);
 331
 332         pci_get_pbm_props(pbm);
 333
 334         pci_fire_hw_init(pbm);
 335         pci_fire_pbm_iommu_init(pbm);
 336 }
 337
 338 static inline int portid_compare(u32 x, u32 y)
 339 {
 340         if (x == (y ^ 1))
 341                 return 1;
 342         return 0;
 343 }
 344
 345 void fire_pci_init(struct device_node *dp, const char *model_name)
 346 {
 347         struct pci_controller_info *p;
 348         u32 portid = of_getintprop_default(dp, "portid", 0xff);
 349         struct iommu *iommu;
 350         struct pci_pbm_info *pbm;
 351
 352         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
 353                 if (portid_compare(pbm->portid, portid)) {
 354                         pci_fire_pbm_init(pbm->parent, dp, portid);
 355                         return;
 356                 }
 357         }
 358
 359         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
 360         if (!p)
 361                 goto fatal_memory_error;
 362
 363         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
 364         if (!iommu)
 365                 goto fatal_memory_error;
 366
 367         p->pbm_A.iommu = iommu;
 368
 369         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
 370         if (!iommu)
 371                 goto fatal_memory_error;
 372
 373         p->pbm_B.iommu = iommu;
 374
 375         p->index = pci_num_controllers++;
 376
 377         /* XXX MSI support XXX */
 378         p->pci_ops = &pci_fire_ops;
 379
 380         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
 381          * for memory space.
 382          */
 383         pci_memspace_mask = 0x7fffffffUL;
 384
 385         pci_fire_pbm_init(p, dp, portid);
 386         return;
 387
 388 fatal_memory_error:
 389         prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
 390         prom_halt();
 391 }