arch/sparc64/kernel/pci_sabre.c

   1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
   2  * pci_sabre.c: Sabre specific PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <asm/apb.h>
  17 #include <asm/pbm.h>
  18 #include <asm/iommu.h>
  19 #include <asm/irq.h>
  20 #include <asm/smp.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23
  24 #include "pci_impl.h"
  25 #include "iommu_common.h"
  26
  27 /* All SABRE registers are 64-bits.  The following accessor
  28  * routines are how they are accessed.  The REG parameter
  29  * is a physical address.
  30  */
  31 #define sabre_read(__reg) \
  32 ({      u64 __ret; \
  33         __asm__ __volatile__("ldxa [%1] %2, %0" \
  34                              : "=r" (__ret) \
  35                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  36                              : "memory"); \
  37         __ret; \
  38 })
  39 #define sabre_write(__reg, __val) \
  40         __asm__ __volatile__("stxa %0, [%1] %2" \
  41                              : /* no outputs */ \
  42                              : "r" (__val), "r" (__reg), \
  43                                "i" (ASI_PHYS_BYPASS_EC_E) \
  44                              : "memory")
  45
  46 /* SABRE PCI controller register offsets and definitions. */
  47 #define SABRE_UE_AFSR           0x0030UL
  48 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  49 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  50 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  51 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  52 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  53 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  54 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  55 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  56 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  57 #define SABRE_UECE_AFAR         0x0038UL
  58 #define SABRE_CE_AFSR           0x0040UL
  59 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  60 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  61 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  62 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  63 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  64 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  65 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  66 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  67 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  68 #define SABRE_IOMMU_CONTROL     0x0200UL
  69 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  70 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  71 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  72 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  73 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  74 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  75 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  76 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  77 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  78 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  79 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  80 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  81 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  82 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  83 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  84 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  85 #define SABRE_IOMMU_TSBBASE     0x0208UL
  86 #define SABRE_IOMMU_FLUSH       0x0210UL
  87 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  88 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  89 #define SABRE_IMAP_SCSI         0x1000UL
  90 #define SABRE_IMAP_ETH          0x1008UL
  91 #define SABRE_IMAP_BPP          0x1010UL
  92 #define SABRE_IMAP_AU_REC       0x1018UL
  93 #define SABRE_IMAP_AU_PLAY      0x1020UL
  94 #define SABRE_IMAP_PFAIL        0x1028UL
  95 #define SABRE_IMAP_KMS          0x1030UL
  96 #define SABRE_IMAP_FLPY         0x1038UL
  97 #define SABRE_IMAP_SHW          0x1040UL
  98 #define SABRE_IMAP_KBD          0x1048UL
  99 #define SABRE_IMAP_MS           0x1050UL
 100 #define SABRE_IMAP_SER          0x1058UL
 101 #define SABRE_IMAP_UE           0x1070UL
 102 #define SABRE_IMAP_CE           0x1078UL
 103 #define SABRE_IMAP_PCIERR       0x1080UL
 104 #define SABRE_IMAP_GFX          0x1098UL
 105 #define SABRE_IMAP_EUPA         0x10a0UL
 106 #define SABRE_ICLR_A_SLOT0      0x1400UL
 107 #define SABRE_ICLR_B_SLOT0      0x1480UL
 108 #define SABRE_ICLR_SCSI         0x1800UL
 109 #define SABRE_ICLR_ETH          0x1808UL
 110 #define SABRE_ICLR_BPP          0x1810UL
 111 #define SABRE_ICLR_AU_REC       0x1818UL
 112 #define SABRE_ICLR_AU_PLAY      0x1820UL
 113 #define SABRE_ICLR_PFAIL        0x1828UL
 114 #define SABRE_ICLR_KMS          0x1830UL
 115 #define SABRE_ICLR_FLPY         0x1838UL
 116 #define SABRE_ICLR_SHW          0x1840UL
 117 #define SABRE_ICLR_KBD          0x1848UL
 118 #define SABRE_ICLR_MS           0x1850UL
 119 #define SABRE_ICLR_SER          0x1858UL
 120 #define SABRE_ICLR_UE           0x1870UL
 121 #define SABRE_ICLR_CE           0x1878UL
 122 #define SABRE_ICLR_PCIERR       0x1880UL
 123 #define SABRE_WRSYNC            0x1c20UL
 124 #define SABRE_PCICTRL           0x2000UL
 125 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 126 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 127 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 128 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 129 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 130 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 131 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 132 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 133 #define SABRE_PIOAFSR           0x2010UL
 134 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 135 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 136 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 137 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 138 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 139 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 140 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 141 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 142 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 143 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 144 #define SABRE_PIOAFAR           0x2018UL
 145 #define SABRE_PCIDIAG           0x2020UL
 146 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 147 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 148 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 149 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 150 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 151 #define SABRE_PCITASR           0x2028UL
 152 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 153 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 154 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 155 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 156 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 157 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 158 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 159 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 160 #define SABRE_PIOBUF_DIAG       0x5000UL
 161 #define SABRE_DMABUF_DIAGLO     0x5100UL
 162 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 163 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 164 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 165 #define SABRE_IOMMU_VADIAG      0xa400UL
 166 #define SABRE_IOMMU_TCDIAG      0xa408UL
 167 #define SABRE_IOMMU_TAG         0xa580UL
 168 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 169 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 170 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 171 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 172 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 173 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 174 #define SABRE_IOMMU_DATA        0xa600UL
 175 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 176 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 177 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 178 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 179 #define SABRE_PCI_IRQSTATE      0xa800UL
 180 #define SABRE_OBIO_IRQSTATE     0xa808UL
 181 #define SABRE_FFBCFG            0xf000UL
 182 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 183 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 184 #define SABRE_MCCTRL0           0xf010UL
 185 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 186 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 187 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 188 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 189 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 190 #define SABRE_MCCTRL1           0xf018UL
 191 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 192 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 193 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 194 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 195 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 196 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 197 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 198 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 199 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 200 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 201 #define SABRE_RESETCTRL         0xf020UL
 202
 203 #define SABRE_CONFIGSPACE       0x001000000UL
 204 #define SABRE_IOSPACE           0x002000000UL
 205 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 206 #define SABRE_MEMSPACE          0x100000000UL
 207 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 208
 209 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
 210  * configuration space address format:
 211  *
 212  *  32             24 23 16 15    11 10       8 7   2  1 0
 213  * ---------------------------------------------------------
 214  * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
 215  * ---------------------------------------------------------
 216  */
 217 #define SABRE_CONFIG_BASE(PBM)  \
 218         ((PBM)->config_space | (1UL << 24))
 219 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG)    \
 220         (((unsigned long)(BUS)   << 16) |       \
 221          ((unsigned long)(DEVFN) << 8)  |       \
 222          ((unsigned long)(REG)))
 223
 224 static int hummingbird_p;
 225 static struct pci_bus *sabre_root_bus;
 226
 227 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
 228                                      unsigned char bus,
 229                                      unsigned int devfn,
 230                                      int where)
 231 {
 232         if (!pbm)
 233                 return NULL;
 234         return (void *)
 235                 (SABRE_CONFIG_BASE(pbm) |
 236                  SABRE_CONFIG_ENCODE(bus, devfn, where));
 237 }
 238
 239 static int sabre_out_of_range(unsigned char devfn)
 240 {
 241         if (hummingbird_p)
 242                 return 0;
 243
 244         return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
 245                 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
 246                 (PCI_SLOT(devfn) > 1));
 247 }
 248
 249 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
 250                                 unsigned char bus,
 251                                 unsigned char devfn)
 252 {
 253         if (hummingbird_p)
 254                 return 0;
 255
 256         return ((pbm->parent == 0) ||
 257                 ((pbm == &pbm->parent->pbm_A) &&
 258                  (bus == pbm->pci_first_busno) &&
 259                  PCI_SLOT(devfn) > 8));
 260 }
 261
 262 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 263                                 int where, int size, u32 *value)
 264 {
 265         struct pci_pbm_info *pbm = bus_dev->sysdata;
 266         unsigned char bus = bus_dev->number;
 267         u32 *addr;
 268         u16 tmp16;
 269         u8 tmp8;
 270
 271         switch (size) {
 272         case 1:
 273                 *value = 0xff;
 274                 break;
 275         case 2:
 276                 *value = 0xffff;
 277                 break;
 278         case 4:
 279                 *value = 0xffffffff;
 280                 break;
 281         }
 282
 283         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 284         if (!addr)
 285                 return PCIBIOS_SUCCESSFUL;
 286
 287         if (__sabre_out_of_range(pbm, bus, devfn))
 288                 return PCIBIOS_SUCCESSFUL;
 289
 290         switch (size) {
 291         case 1:
 292                 pci_config_read8((u8 *) addr, &tmp8);
 293                 *value = tmp8;
 294                 break;
 295
 296         case 2:
 297                 if (where & 0x01) {
 298                         printk("pci_read_config_word: misaligned reg [%x]\n",
 299                                where);
 300                         return PCIBIOS_SUCCESSFUL;
 301                 }
 302                 pci_config_read16((u16 *) addr, &tmp16);
 303                 *value = tmp16;
 304                 break;
 305
 306         case 4:
 307                 if (where & 0x03) {
 308                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 309                                where);
 310                         return PCIBIOS_SUCCESSFUL;
 311                 }
 312                 pci_config_read32(addr, value);
 313                 break;
 314         }
 315
 316         return PCIBIOS_SUCCESSFUL;
 317 }
 318
 319 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 320                               int where, int size, u32 *value)
 321 {
 322         if (!bus->number && sabre_out_of_range(devfn)) {
 323                 switch (size) {
 324                 case 1:
 325                         *value = 0xff;
 326                         break;
 327                 case 2:
 328                         *value = 0xffff;
 329                         break;
 330                 case 4:
 331                         *value = 0xffffffff;
 332                         break;
 333                 }
 334                 return PCIBIOS_SUCCESSFUL;
 335         }
 336
 337         if (bus->number || PCI_SLOT(devfn))
 338                 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
 339
 340         /* When accessing PCI config space of the PCI controller itself (bus
 341          * 0, device slot 0, function 0) there are restrictions.  Each
 342          * register must be accessed as it's natural size.  Thus, for example
 343          * the Vendor ID must be accessed as a 16-bit quantity.
 344          */
 345
 346         switch (size) {
 347         case 1:
 348                 if (where < 8) {
 349                         u32 tmp32;
 350                         u16 tmp16;
 351
 352                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 353                         tmp16 = (u16) tmp32;
 354                         if (where & 1)
 355                                 *value = tmp16 >> 8;
 356                         else
 357                                 *value = tmp16 & 0xff;
 358                 } else
 359                         return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
 360                 break;
 361
 362         case 2:
 363                 if (where < 8)
 364                         return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
 365                 else {
 366                         u32 tmp32;
 367                         u8 tmp8;
 368
 369                         __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
 370                         tmp8 = (u8) tmp32;
 371                         *value = tmp8;
 372                         __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
 373                         tmp8 = (u8) tmp32;
 374                         *value |= tmp8 << 8;
 375                 }
 376                 break;
 377
 378         case 4: {
 379                 u32 tmp32;
 380                 u16 tmp16;
 381
 382                 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
 383                 tmp16 = (u16) tmp32;
 384                 *value = tmp16;
 385                 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
 386                 tmp16 = (u16) tmp32;
 387                 *value |= tmp16 << 16;
 388                 break;
 389         }
 390         }
 391         return PCIBIOS_SUCCESSFUL;
 392 }
 393
 394 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 395                                  int where, int size, u32 value)
 396 {
 397         struct pci_pbm_info *pbm = bus_dev->sysdata;
 398         unsigned char bus = bus_dev->number;
 399         u32 *addr;
 400
 401         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 402         if (!addr)
 403                 return PCIBIOS_SUCCESSFUL;
 404
 405         if (__sabre_out_of_range(pbm, bus, devfn))
 406                 return PCIBIOS_SUCCESSFUL;
 407
 408         switch (size) {
 409         case 1:
 410                 pci_config_write8((u8 *) addr, value);
 411                 break;
 412
 413         case 2:
 414                 if (where & 0x01) {
 415                         printk("pci_write_config_word: misaligned reg [%x]\n",
 416                                where);
 417                         return PCIBIOS_SUCCESSFUL;
 418                 }
 419                 pci_config_write16((u16 *) addr, value);
 420                 break;
 421
 422         case 4:
 423                 if (where & 0x03) {
 424                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 425                                where);
 426                         return PCIBIOS_SUCCESSFUL;
 427                 }
 428                 pci_config_write32(addr, value);
 429                 break;
 430         }
 431
 432         return PCIBIOS_SUCCESSFUL;
 433 }
 434
 435 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 436                                int where, int size, u32 value)
 437 {
 438         if (bus->number)
 439                 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 440
 441         if (sabre_out_of_range(devfn))
 442                 return PCIBIOS_SUCCESSFUL;
 443
 444         switch (size) {
 445         case 1:
 446                 if (where < 8) {
 447                         u32 tmp32;
 448                         u16 tmp16;
 449
 450                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 451                         tmp16 = (u16) tmp32;
 452                         if (where & 1) {
 453                                 value &= 0x00ff;
 454                                 value |= tmp16 << 8;
 455                         } else {
 456                                 value &= 0xff00;
 457                                 value |= tmp16;
 458                         }
 459                         tmp32 = (u32) tmp16;
 460                         return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
 461                 } else
 462                         return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
 463                 break;
 464         case 2:
 465                 if (where < 8)
 466                         return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
 467                 else {
 468                         __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
 469                         __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
 470                 }
 471                 break;
 472         case 4:
 473                 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
 474                 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
 475                 break;
 476         }
 477         return PCIBIOS_SUCCESSFUL;
 478 }
 479
 480 static struct pci_ops sabre_ops = {
 481         .read =         sabre_read_pci_cfg,
 482         .write =        sabre_write_pci_cfg,
 483 };
 484
 485 /* SABRE error handling support. */
 486 static void sabre_check_iommu_error(struct pci_controller_info *p,
 487                                     unsigned long afsr,
 488                                     unsigned long afar)
 489 {
 490         struct pci_iommu *iommu = p->pbm_A.iommu;
 491         unsigned long iommu_tag[16];
 492         unsigned long iommu_data[16];
 493         unsigned long flags;
 494         u64 control;
 495         int i;
 496
 497         spin_lock_irqsave(&iommu->lock, flags);
 498         control = sabre_read(iommu->iommu_control);
 499         if (control & SABRE_IOMMUCTRL_ERR) {
 500                 char *type_string;
 501
 502                 /* Clear the error encountered bit.
 503                  * NOTE: On Sabre this is write 1 to clear,
 504                  *       which is different from Psycho.
 505                  */
 506                 sabre_write(iommu->iommu_control, control);
 507                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 508                 case 1:
 509                         type_string = "Invalid Error";
 510                         break;
 511                 case 3:
 512                         type_string = "ECC Error";
 513                         break;
 514                 default:
 515                         type_string = "Unknown";
 516                         break;
 517                 };
 518                 printk("SABRE%d: IOMMU Error, type[%s]\n",
 519                        p->index, type_string);
 520
 521                 /* Enter diagnostic mode and probe for error'd
 522                  * entries in the IOTLB.
 523                  */
 524                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
 525                 sabre_write(iommu->iommu_control,
 526                             (control | SABRE_IOMMUCTRL_DENAB));
 527                 for (i = 0; i < 16; i++) {
 528                         unsigned long base = p->pbm_A.controller_regs;
 529
 530                         iommu_tag[i] =
 531                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
 532                         iommu_data[i] =
 533                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
 534                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 535                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 536                 }
 537                 sabre_write(iommu->iommu_control, control);
 538
 539                 for (i = 0; i < 16; i++) {
 540                         unsigned long tag, data;
 541
 542                         tag = iommu_tag[i];
 543                         if (!(tag & SABRE_IOMMUTAG_ERR))
 544                                 continue;
 545
 546                         data = iommu_data[i];
 547                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
 548                         case 1:
 549                                 type_string = "Invalid Error";
 550                                 break;
 551                         case 3:
 552                                 type_string = "ECC Error";
 553                                 break;
 554                         default:
 555                                 type_string = "Unknown";
 556                                 break;
 557                         };
 558                         printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
 559                                p->index, i, tag, type_string,
 560                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
 561                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
 562                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
 563                         printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
 564                                p->index, i, data,
 565                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
 566                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
 567                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
 568                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
 569                 }
 570         }
 571         spin_unlock_irqrestore(&iommu->lock, flags);
 572 }
 573
 574 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
 575 {
 576         struct pci_controller_info *p = dev_id;
 577         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
 578         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 579         unsigned long afsr, afar, error_bits;
 580         int reported;
 581
 582         /* Latch uncorrectable error status. */
 583         afar = sabre_read(afar_reg);
 584         afsr = sabre_read(afsr_reg);
 585
 586         /* Clear the primary/secondary error status bits. */
 587         error_bits = afsr &
 588                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 589                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 590                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 591         if (!error_bits)
 592                 return IRQ_NONE;
 593         sabre_write(afsr_reg, error_bits);
 594
 595         /* Log the error. */
 596         printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
 597                p->index,
 598                ((error_bits & SABRE_UEAFSR_PDRD) ?
 599                 "DMA Read" :
 600                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 601                  "DMA Write" : "???")),
 602                ((error_bits & SABRE_UEAFSR_PDTE) ?
 603                 ":Translation Error" : ""));
 604         printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 605                p->index,
 606                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 607                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 608                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 609         printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
 610         printk("SABRE%d: UE Secondary errors [", p->index);
 611         reported = 0;
 612         if (afsr & SABRE_UEAFSR_SDRD) {
 613                 reported++;
 614                 printk("(DMA Read)");
 615         }
 616         if (afsr & SABRE_UEAFSR_SDWR) {
 617                 reported++;
 618                 printk("(DMA Write)");
 619         }
 620         if (afsr & SABRE_UEAFSR_SDTE) {
 621                 reported++;
 622                 printk("(Translation Error)");
 623         }
 624         if (!reported)
 625                 printk("(none)");
 626         printk("]\n");
 627
 628         /* Interrogate IOMMU for error status. */
 629         sabre_check_iommu_error(p, afsr, afar);
 630
 631         return IRQ_HANDLED;
 632 }
 633
 634 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
 635 {
 636         struct pci_controller_info *p = dev_id;
 637         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
 638         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 639         unsigned long afsr, afar, error_bits;
 640         int reported;
 641
 642         /* Latch error status. */
 643         afar = sabre_read(afar_reg);
 644         afsr = sabre_read(afsr_reg);
 645
 646         /* Clear primary/secondary error status bits. */
 647         error_bits = afsr &
 648                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 649                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 650         if (!error_bits)
 651                 return IRQ_NONE;
 652         sabre_write(afsr_reg, error_bits);
 653
 654         /* Log the error. */
 655         printk("SABRE%d: Correctable Error, primary error type[%s]\n",
 656                p->index,
 657                ((error_bits & SABRE_CEAFSR_PDRD) ?
 658                 "DMA Read" :
 659                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 660                  "DMA Write" : "???")));
 661
 662         /* XXX Use syndrome and afar to print out module string just like
 663          * XXX UDB CE trap handler does... -DaveM
 664          */
 665         printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 666                "was_block(%d)\n",
 667                p->index,
 668                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 669                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 670                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 671                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 672         printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
 673         printk("SABRE%d: CE Secondary errors [", p->index);
 674         reported = 0;
 675         if (afsr & SABRE_CEAFSR_SDRD) {
 676                 reported++;
 677                 printk("(DMA Read)");
 678         }
 679         if (afsr & SABRE_CEAFSR_SDWR) {
 680                 reported++;
 681                 printk("(DMA Write)");
 682         }
 683         if (!reported)
 684                 printk("(none)");
 685         printk("]\n");
 686
 687         return IRQ_HANDLED;
 688 }
 689
 690 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
 691 {
 692         unsigned long csr_reg, csr, csr_error_bits;
 693         irqreturn_t ret = IRQ_NONE;
 694         u16 stat;
 695
 696         csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
 697         csr = sabre_read(csr_reg);
 698         csr_error_bits =
 699                 csr & SABRE_PCICTRL_SERR;
 700         if (csr_error_bits) {
 701                 /* Clear the errors.  */
 702                 sabre_write(csr_reg, csr);
 703
 704                 /* Log 'em.  */
 705                 if (csr_error_bits & SABRE_PCICTRL_SERR)
 706                         printk("SABRE%d: PCI SERR signal asserted.\n",
 707                                p->index);
 708                 ret = IRQ_HANDLED;
 709         }
 710         pci_bus_read_config_word(sabre_root_bus, 0,
 711                                  PCI_STATUS, &stat);
 712         if (stat & (PCI_STATUS_PARITY |
 713                     PCI_STATUS_SIG_TARGET_ABORT |
 714                     PCI_STATUS_REC_TARGET_ABORT |
 715                     PCI_STATUS_REC_MASTER_ABORT |
 716                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
 717                 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
 718                        p->index, stat);
 719                 pci_bus_write_config_word(sabre_root_bus, 0,
 720                                           PCI_STATUS, 0xffff);
 721                 ret = IRQ_HANDLED;
 722         }
 723         return ret;
 724 }
 725
 726 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
 727 {
 728         struct pci_controller_info *p = dev_id;
 729         unsigned long afsr_reg, afar_reg;
 730         unsigned long afsr, afar, error_bits;
 731         int reported;
 732
 733         afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
 734         afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
 735
 736         /* Latch error status. */
 737         afar = sabre_read(afar_reg);
 738         afsr = sabre_read(afsr_reg);
 739
 740         /* Clear primary/secondary error status bits. */
 741         error_bits = afsr &
 742                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
 743                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
 744                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
 745                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
 746         if (!error_bits)
 747                 return sabre_pcierr_intr_other(p);
 748         sabre_write(afsr_reg, error_bits);
 749
 750         /* Log the error. */
 751         printk("SABRE%d: PCI Error, primary error type[%s]\n",
 752                p->index,
 753                (((error_bits & SABRE_PIOAFSR_PMA) ?
 754                  "Master Abort" :
 755                  ((error_bits & SABRE_PIOAFSR_PTA) ?
 756                   "Target Abort" :
 757                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
 758                    "Excessive Retries" :
 759                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
 760                     "Parity Error" : "???"))))));
 761         printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
 762                p->index,
 763                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
 764                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
 765         printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
 766         printk("SABRE%d: PCI Secondary errors [", p->index);
 767         reported = 0;
 768         if (afsr & SABRE_PIOAFSR_SMA) {
 769                 reported++;
 770                 printk("(Master Abort)");
 771         }
 772         if (afsr & SABRE_PIOAFSR_STA) {
 773                 reported++;
 774                 printk("(Target Abort)");
 775         }
 776         if (afsr & SABRE_PIOAFSR_SRTRY) {
 777                 reported++;
 778                 printk("(Excessive Retries)");
 779         }
 780         if (afsr & SABRE_PIOAFSR_SPERR) {
 781                 reported++;
 782                 printk("(Parity Error)");
 783         }
 784         if (!reported)
 785                 printk("(none)");
 786         printk("]\n");
 787
 788         /* For the error types shown, scan both PCI buses for devices
 789          * which have logged that error type.
 790          */
 791
 792         /* If we see a Target Abort, this could be the result of an
 793          * IOMMU translation error of some sort.  It is extremely
 794          * useful to log this information as usually it indicates
 795          * a bug in the IOMMU support code or a PCI device driver.
 796          */
 797         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
 798                 sabre_check_iommu_error(p, afsr, afar);
 799                 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 800         }
 801         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
 802                 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 803
 804         /* For excessive retries, SABRE/PBM will abort the device
 805          * and there is no way to specifically check for excessive
 806          * retries in the config space status registers.  So what
 807          * we hope is that we'll catch it via the master/target
 808          * abort events.
 809          */
 810
 811         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
 812                 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
 813
 814         return IRQ_HANDLED;
 815 }
 816
 817 static void sabre_register_error_handlers(struct pci_controller_info *p)
 818 {
 819         struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
 820         struct device_node *dp = pbm->prom_node;
 821         struct of_device *op;
 822         unsigned long base = pbm->controller_regs;
 823         u64 tmp;
 824
 825         if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
 826                 dp = dp->parent;
 827
 828         op = of_find_device_by_node(dp);
 829         if (!op)
 830                 return;
 831
 832         /* Sabre/Hummingbird IRQ property layout is:
 833          * 0: PCI ERR
 834          * 1: UE ERR
 835          * 2: CE ERR
 836          * 3: POWER FAIL
 837          */
 838         if (op->num_irqs < 4)
 839                 return;
 840
 841         /* We clear the error bits in the appropriate AFSR before
 842          * registering the handler so that we don't get spurious
 843          * interrupts.
 844          */
 845         sabre_write(base + SABRE_UE_AFSR,
 846                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 847                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 848                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
 849
 850         request_irq(op->irqs[1], sabre_ue_intr, IRQF_SHARED, "SABRE UE", p);
 851
 852         sabre_write(base + SABRE_CE_AFSR,
 853                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 854                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
 855
 856         request_irq(op->irqs[2], sabre_ce_intr, IRQF_SHARED, "SABRE CE", p);
 857         request_irq(op->irqs[0], sabre_pcierr_intr, IRQF_SHARED,
 858                     "SABRE PCIERR", p);
 859
 860         tmp = sabre_read(base + SABRE_PCICTRL);
 861         tmp |= SABRE_PCICTRL_ERREN;
 862         sabre_write(base + SABRE_PCICTRL, tmp);
 863 }
 864
 865 static void sabre_base_address_update(struct pci_dev *pdev, int resource)
 866 {
 867         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 868         struct resource *res;
 869         unsigned long base;
 870         u32 reg;
 871         int where, size, is_64bit;
 872
 873         res = &pdev->resource[resource];
 874         if (resource < 6) {
 875                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
 876         } else if (resource == PCI_ROM_RESOURCE) {
 877                 where = pdev->rom_base_reg;
 878         } else {
 879                 /* Somebody might have asked allocation of a non-standard resource */
 880                 return;
 881         }
 882
 883         is_64bit = 0;
 884         if (res->flags & IORESOURCE_IO)
 885                 base = pbm->controller_regs + SABRE_IOSPACE;
 886         else {
 887                 base = pbm->controller_regs + SABRE_MEMSPACE;
 888                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
 889                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
 890                         is_64bit = 1;
 891         }
 892
 893         size = res->end - res->start;
 894         pci_read_config_dword(pdev, where, &reg);
 895         reg = ((reg & size) |
 896                (((u32)(res->start - base)) & ~size));
 897         if (resource == PCI_ROM_RESOURCE) {
 898                 reg |= PCI_ROM_ADDRESS_ENABLE;
 899                 res->flags |= IORESOURCE_ROM_ENABLE;
 900         }
 901         pci_write_config_dword(pdev, where, reg);
 902
 903         /* This knows that the upper 32-bits of the address
 904          * must be zero.  Our PCI common layer enforces this.
 905          */
 906         if (is_64bit)
 907                 pci_write_config_dword(pdev, where + 4, 0);
 908 }
 909
 910 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
 911 {
 912         struct pci_dev *pdev;
 913
 914         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
 915                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 916                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
 917                         u16 word16;
 918
 919                         pci_read_config_word(pdev, PCI_COMMAND, &word16);
 920                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 921                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
 922                                 PCI_COMMAND_IO;
 923                         pci_write_config_word(pdev, PCI_COMMAND, word16);
 924
 925                         /* Status register bits are "write 1 to clear". */
 926                         pci_write_config_word(pdev, PCI_STATUS, 0xffff);
 927                         pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
 928
 929                         /* Use a primary/seconday latency timer value
 930                          * of 64.
 931                          */
 932                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
 933                         pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
 934
 935                         /* Enable reporting/forwarding of master aborts,
 936                          * parity, and SERR.
 937                          */
 938                         pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
 939                                               (PCI_BRIDGE_CTL_PARITY |
 940                                                PCI_BRIDGE_CTL_SERR |
 941                                                PCI_BRIDGE_CTL_MASTER_ABORT));
 942                 }
 943         }
 944 }
 945
 946 static void sabre_scan_bus(struct pci_controller_info *p)
 947 {
 948         static int once;
 949         struct pci_bus *pbus;
 950
 951         /* The APB bridge speaks to the Sabre host PCI bridge
 952          * at 66Mhz, but the front side of APB runs at 33Mhz
 953          * for both segments.
 954          */
 955         p->pbm_A.is_66mhz_capable = 0;
 956
 957         /* This driver has not been verified to handle
 958          * multiple SABREs yet, so trap this.
 959          *
 960          * Also note that the SABRE host bridge is hardwired
 961          * to live at bus 0.
 962          */
 963         if (once != 0) {
 964                 prom_printf("SABRE: Multiple controllers unsupported.\n");
 965                 prom_halt();
 966         }
 967         once++;
 968
 969         pbus = pci_scan_one_pbm(&p->pbm_A);
 970         if (!pbus)
 971                 return;
 972
 973         sabre_root_bus = pbus;
 974
 975         apb_init(p, pbus);
 976
 977         sabre_register_error_handlers(p);
 978 }
 979
 980 static void sabre_iommu_init(struct pci_controller_info *p,
 981                              int tsbsize, unsigned long dvma_offset,
 982                              u32 dma_mask)
 983 {
 984         struct pci_iommu *iommu = p->pbm_A.iommu;
 985         unsigned long i;
 986         u64 control;
 987
 988         /* Register addresses. */
 989         iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
 990         iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
 991         iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
 992         iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
 993         /* Sabre's IOMMU lacks ctx flushing. */
 994         iommu->iommu_ctxflush = 0;
 995
 996         /* Invalidate TLB Entries. */
 997         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
 998         control |= SABRE_IOMMUCTRL_DENAB;
 999         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1000
1001         for(i = 0; i < 16; i++) {
1002                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
1003                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1004         }
1005
1006         /* Leave diag mode enabled for full-flushing done
1007          * in pci_iommu.c
1008          */
1009         pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
1010
1011         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
1012                     __pa(iommu->page_table));
1013
1014         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1015         control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
1016         control |= SABRE_IOMMUCTRL_ENAB;
1017         switch(tsbsize) {
1018         case 64:
1019                 control |= SABRE_IOMMU_TSBSZ_64K;
1020                 break;
1021         case 128:
1022                 control |= SABRE_IOMMU_TSBSZ_128K;
1023                 break;
1024         default:
1025                 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1026                 prom_halt();
1027                 break;
1028         }
1029         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1030 }
1031
1032 static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp)
1033 {
1034         struct pci_pbm_info *pbm;
1035
1036         pbm = &p->pbm_A;
1037         pbm->name = dp->full_name;
1038         printk("%s: SABRE PCI Bus Module\n", pbm->name);
1039
1040         pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1041         pbm->parent = p;
1042         pbm->prom_node = dp;
1043         pbm->pci_first_slot = 1;
1044         pbm->pci_first_busno = p->pci_first_busno;
1045         pbm->pci_last_busno = p->pci_last_busno;
1046
1047         pci_determine_mem_io_space(pbm);
1048 }
1049
1050 void sabre_init(struct device_node *dp, char *model_name)
1051 {
1052         struct linux_prom64_registers *pr_regs;
1053         struct pci_controller_info *p;
1054         struct pci_iommu *iommu;
1055         int tsbsize;
1056         u32 *busrange;
1057         u32 *vdma;
1058         u32 upa_portid, dma_mask;
1059         u64 clear_irq;
1060
1061         hummingbird_p = 0;
1062         if (!strcmp(model_name, "pci108e,a001"))
1063                 hummingbird_p = 1;
1064         else if (!strcmp(model_name, "SUNW,sabre")) {
1065                 const char *compat = of_get_property(dp, "compatible", NULL);
1066                 if (compat && !strcmp(compat, "pci108e,a001"))
1067                         hummingbird_p = 1;
1068                 if (!hummingbird_p) {
1069                         struct device_node *dp;
1070
1071                         /* Of course, Sun has to encode things a thousand
1072                          * different ways, inconsistently.
1073                          */
1074                         cpu_find_by_instance(0, &dp, NULL);
1075                         if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
1076                                 hummingbird_p = 1;
1077                 }
1078         }
1079
1080         p = kzalloc(sizeof(*p), GFP_ATOMIC);
1081         if (!p) {
1082                 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1083                 prom_halt();
1084         }
1085
1086         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1087         if (!iommu) {
1088                 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1089                 prom_halt();
1090         }
1091         p->pbm_A.iommu = iommu;
1092
1093         upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1094
1095         p->next = pci_controller_root;
1096         pci_controller_root = p;
1097
1098         p->pbm_A.portid = upa_portid;
1099         p->index = pci_num_controllers++;
1100         p->pbms_same_domain = 1;
1101         p->scan_bus = sabre_scan_bus;
1102         p->base_address_update = sabre_base_address_update;
1103         p->pci_ops = &sabre_ops;
1104
1105         /*
1106          * Map in SABRE register set and report the presence of this SABRE.
1107          */
1108
1109         pr_regs = of_get_property(dp, "reg", NULL);
1110
1111         /*
1112          * First REG in property is base of entire SABRE register space.
1113          */
1114         p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1115
1116         /* Clear interrupts */
1117
1118         /* PCI first */
1119         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1120                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1121
1122         /* Then OBIO */
1123         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1124                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1125
1126         /* Error interrupts are enabled later after the bus scan. */
1127         sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1128                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
1129                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1130
1131         /* Now map in PCI config space for entire SABRE. */
1132         p->pbm_A.config_space =
1133                 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1134
1135         vdma = of_get_property(dp, "virtual-dma", NULL);
1136
1137         dma_mask = vdma[0];
1138         switch(vdma[1]) {
1139                 case 0x20000000:
1140                         dma_mask |= 0x1fffffff;
1141                         tsbsize = 64;
1142                         break;
1143                 case 0x40000000:
1144                         dma_mask |= 0x3fffffff;
1145                         tsbsize = 128;
1146                         break;
1147
1148                 case 0x80000000:
1149                         dma_mask |= 0x7fffffff;
1150                         tsbsize = 128;
1151                         break;
1152                 default:
1153                         prom_printf("SABRE: strange virtual-dma size.\n");
1154                         prom_halt();
1155         }
1156
1157         sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1158
1159         busrange = of_get_property(dp, "bus-range", NULL);
1160         p->pci_first_busno = busrange[0];
1161         p->pci_last_busno = busrange[1];
1162
1163         /*
1164          * Look for APB underneath.
1165          */
1166         sabre_pbm_init(p, dp);
1167 }