arch/sparc64/kernel/pci_sabre.c

   1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
   2  * pci_sabre.c: Sabre specific PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <asm/apb.h>
  17 #include <asm/pbm.h>
  18 #include <asm/iommu.h>
  19 #include <asm/irq.h>
  20 #include <asm/smp.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23
  24 #include "pci_impl.h"
  25 #include "iommu_common.h"
  26
  27 /* All SABRE registers are 64-bits.  The following accessor
  28  * routines are how they are accessed.  The REG parameter
  29  * is a physical address.
  30  */
  31 #define sabre_read(__reg) \
  32 ({      u64 __ret; \
  33         __asm__ __volatile__("ldxa [%1] %2, %0" \
  34                              : "=r" (__ret) \
  35                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  36                              : "memory"); \
  37         __ret; \
  38 })
  39 #define sabre_write(__reg, __val) \
  40         __asm__ __volatile__("stxa %0, [%1] %2" \
  41                              : /* no outputs */ \
  42                              : "r" (__val), "r" (__reg), \
  43                                "i" (ASI_PHYS_BYPASS_EC_E) \
  44                              : "memory")
  45
  46 /* SABRE PCI controller register offsets and definitions. */
  47 #define SABRE_UE_AFSR           0x0030UL
  48 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  49 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  50 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  51 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  52 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  53 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  54 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  55 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  56 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  57 #define SABRE_UECE_AFAR         0x0038UL
  58 #define SABRE_CE_AFSR           0x0040UL
  59 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  60 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  61 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  62 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  63 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  64 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  65 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  66 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  67 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  68 #define SABRE_IOMMU_CONTROL     0x0200UL
  69 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  70 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  71 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  72 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  73 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  74 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  75 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  76 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  77 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  78 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  79 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  80 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  81 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  82 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  83 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  84 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  85 #define SABRE_IOMMU_TSBBASE     0x0208UL
  86 #define SABRE_IOMMU_FLUSH       0x0210UL
  87 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  88 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  89 #define SABRE_IMAP_SCSI         0x1000UL
  90 #define SABRE_IMAP_ETH          0x1008UL
  91 #define SABRE_IMAP_BPP          0x1010UL
  92 #define SABRE_IMAP_AU_REC       0x1018UL
  93 #define SABRE_IMAP_AU_PLAY      0x1020UL
  94 #define SABRE_IMAP_PFAIL        0x1028UL
  95 #define SABRE_IMAP_KMS          0x1030UL
  96 #define SABRE_IMAP_FLPY         0x1038UL
  97 #define SABRE_IMAP_SHW          0x1040UL
  98 #define SABRE_IMAP_KBD          0x1048UL
  99 #define SABRE_IMAP_MS           0x1050UL
 100 #define SABRE_IMAP_SER          0x1058UL
 101 #define SABRE_IMAP_UE           0x1070UL
 102 #define SABRE_IMAP_CE           0x1078UL
 103 #define SABRE_IMAP_PCIERR       0x1080UL
 104 #define SABRE_IMAP_GFX          0x1098UL
 105 #define SABRE_IMAP_EUPA         0x10a0UL
 106 #define SABRE_ICLR_A_SLOT0      0x1400UL
 107 #define SABRE_ICLR_B_SLOT0      0x1480UL
 108 #define SABRE_ICLR_SCSI         0x1800UL
 109 #define SABRE_ICLR_ETH          0x1808UL
 110 #define SABRE_ICLR_BPP          0x1810UL
 111 #define SABRE_ICLR_AU_REC       0x1818UL
 112 #define SABRE_ICLR_AU_PLAY      0x1820UL
 113 #define SABRE_ICLR_PFAIL        0x1828UL
 114 #define SABRE_ICLR_KMS          0x1830UL
 115 #define SABRE_ICLR_FLPY         0x1838UL
 116 #define SABRE_ICLR_SHW          0x1840UL
 117 #define SABRE_ICLR_KBD          0x1848UL
 118 #define SABRE_ICLR_MS           0x1850UL
 119 #define SABRE_ICLR_SER          0x1858UL
 120 #define SABRE_ICLR_UE           0x1870UL
 121 #define SABRE_ICLR_CE           0x1878UL
 122 #define SABRE_ICLR_PCIERR       0x1880UL
 123 #define SABRE_WRSYNC            0x1c20UL
 124 #define SABRE_PCICTRL           0x2000UL
 125 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 126 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 127 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 128 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 129 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 130 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 131 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 132 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 133 #define SABRE_PIOAFSR           0x2010UL
 134 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 135 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 136 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 137 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 138 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 139 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 140 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 141 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 142 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 143 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 144 #define SABRE_PIOAFAR           0x2018UL
 145 #define SABRE_PCIDIAG           0x2020UL
 146 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 147 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 148 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 149 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 150 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 151 #define SABRE_PCITASR           0x2028UL
 152 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 153 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 154 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 155 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 156 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 157 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 158 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 159 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 160 #define SABRE_PIOBUF_DIAG       0x5000UL
 161 #define SABRE_DMABUF_DIAGLO     0x5100UL
 162 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 163 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 164 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 165 #define SABRE_IOMMU_VADIAG      0xa400UL
 166 #define SABRE_IOMMU_TCDIAG      0xa408UL
 167 #define SABRE_IOMMU_TAG         0xa580UL
 168 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 169 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 170 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 171 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 172 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 173 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 174 #define SABRE_IOMMU_DATA        0xa600UL
 175 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 176 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 177 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 178 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 179 #define SABRE_PCI_IRQSTATE      0xa800UL
 180 #define SABRE_OBIO_IRQSTATE     0xa808UL
 181 #define SABRE_FFBCFG            0xf000UL
 182 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 183 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 184 #define SABRE_MCCTRL0           0xf010UL
 185 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 186 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 187 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 188 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 189 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 190 #define SABRE_MCCTRL1           0xf018UL
 191 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 192 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 193 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 194 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 195 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 196 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 197 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 198 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 199 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 200 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 201 #define SABRE_RESETCTRL         0xf020UL
 202
 203 #define SABRE_CONFIGSPACE       0x001000000UL
 204 #define SABRE_IOSPACE           0x002000000UL
 205 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 206 #define SABRE_MEMSPACE          0x100000000UL
 207 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 208
 209 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
 210  * configuration space address format:
 211  *
 212  *  32             24 23 16 15    11 10       8 7   2  1 0
 213  * ---------------------------------------------------------
 214  * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
 215  * ---------------------------------------------------------
 216  */
 217 #define SABRE_CONFIG_BASE(PBM)  \
 218         ((PBM)->config_space | (1UL << 24))
 219 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG)    \
 220         (((unsigned long)(BUS)   << 16) |       \
 221          ((unsigned long)(DEVFN) << 8)  |       \
 222          ((unsigned long)(REG)))
 223
 224 static int hummingbird_p;
 225 static struct pci_bus *sabre_root_bus;
 226
 227 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
 228                                      unsigned char bus,
 229                                      unsigned int devfn,
 230                                      int where)
 231 {
 232         if (!pbm)
 233                 return NULL;
 234         return (void *)
 235                 (SABRE_CONFIG_BASE(pbm) |
 236                  SABRE_CONFIG_ENCODE(bus, devfn, where));
 237 }
 238
 239 static int sabre_out_of_range(unsigned char devfn)
 240 {
 241         if (hummingbird_p)
 242                 return 0;
 243
 244         return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
 245                 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
 246                 (PCI_SLOT(devfn) > 1));
 247 }
 248
 249 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
 250                                 unsigned char bus,
 251                                 unsigned char devfn)
 252 {
 253         if (hummingbird_p)
 254                 return 0;
 255
 256         return ((pbm->parent == 0) ||
 257                 ((pbm == &pbm->parent->pbm_A) &&
 258                  (bus == pbm->pci_first_busno) &&
 259                  PCI_SLOT(devfn) > 8));
 260 }
 261
 262 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 263                                 int where, int size, u32 *value)
 264 {
 265         struct pci_pbm_info *pbm = bus_dev->sysdata;
 266         unsigned char bus = bus_dev->number;
 267         u32 *addr;
 268         u16 tmp16;
 269         u8 tmp8;
 270
 271         switch (size) {
 272         case 1:
 273                 *value = 0xff;
 274                 break;
 275         case 2:
 276                 *value = 0xffff;
 277                 break;
 278         case 4:
 279                 *value = 0xffffffff;
 280                 break;
 281         }
 282
 283         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 284         if (!addr)
 285                 return PCIBIOS_SUCCESSFUL;
 286
 287         if (__sabre_out_of_range(pbm, bus, devfn))
 288                 return PCIBIOS_SUCCESSFUL;
 289
 290         switch (size) {
 291         case 1:
 292                 pci_config_read8((u8 *) addr, &tmp8);
 293                 *value = tmp8;
 294                 break;
 295
 296         case 2:
 297                 if (where & 0x01) {
 298                         printk("pci_read_config_word: misaligned reg [%x]\n",
 299                                where);
 300                         return PCIBIOS_SUCCESSFUL;
 301                 }
 302                 pci_config_read16((u16 *) addr, &tmp16);
 303                 *value = tmp16;
 304                 break;
 305
 306         case 4:
 307                 if (where & 0x03) {
 308                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 309                                where);
 310                         return PCIBIOS_SUCCESSFUL;
 311                 }
 312                 pci_config_read32(addr, value);
 313                 break;
 314         }
 315
 316         return PCIBIOS_SUCCESSFUL;
 317 }
 318
 319 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 320                               int where, int size, u32 *value)
 321 {
 322         struct pci_pbm_info *pbm = bus->sysdata;
 323
 324         if (bus == pbm->pci_bus && devfn == 0x00)
 325                 return pci_host_bridge_read_pci_cfg(bus, devfn, where,
 326                                                     size, value);
 327
 328         if (!bus->number && sabre_out_of_range(devfn)) {
 329                 switch (size) {
 330                 case 1:
 331                         *value = 0xff;
 332                         break;
 333                 case 2:
 334                         *value = 0xffff;
 335                         break;
 336                 case 4:
 337                         *value = 0xffffffff;
 338                         break;
 339                 }
 340                 return PCIBIOS_SUCCESSFUL;
 341         }
 342
 343         if (bus->number || PCI_SLOT(devfn))
 344                 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
 345
 346         /* When accessing PCI config space of the PCI controller itself (bus
 347          * 0, device slot 0, function 0) there are restrictions.  Each
 348          * register must be accessed as it's natural size.  Thus, for example
 349          * the Vendor ID must be accessed as a 16-bit quantity.
 350          */
 351
 352         switch (size) {
 353         case 1:
 354                 if (where < 8) {
 355                         u32 tmp32;
 356                         u16 tmp16;
 357
 358                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 359                         tmp16 = (u16) tmp32;
 360                         if (where & 1)
 361                                 *value = tmp16 >> 8;
 362                         else
 363                                 *value = tmp16 & 0xff;
 364                 } else
 365                         return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
 366                 break;
 367
 368         case 2:
 369                 if (where < 8)
 370                         return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
 371                 else {
 372                         u32 tmp32;
 373                         u8 tmp8;
 374
 375                         __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
 376                         tmp8 = (u8) tmp32;
 377                         *value = tmp8;
 378                         __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
 379                         tmp8 = (u8) tmp32;
 380                         *value |= tmp8 << 8;
 381                 }
 382                 break;
 383
 384         case 4: {
 385                 u32 tmp32;
 386                 u16 tmp16;
 387
 388                 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
 389                 tmp16 = (u16) tmp32;
 390                 *value = tmp16;
 391                 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
 392                 tmp16 = (u16) tmp32;
 393                 *value |= tmp16 << 16;
 394                 break;
 395         }
 396         }
 397         return PCIBIOS_SUCCESSFUL;
 398 }
 399
 400 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 401                                  int where, int size, u32 value)
 402 {
 403         struct pci_pbm_info *pbm = bus_dev->sysdata;
 404         unsigned char bus = bus_dev->number;
 405         u32 *addr;
 406
 407         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 408         if (!addr)
 409                 return PCIBIOS_SUCCESSFUL;
 410
 411         if (__sabre_out_of_range(pbm, bus, devfn))
 412                 return PCIBIOS_SUCCESSFUL;
 413
 414         switch (size) {
 415         case 1:
 416                 pci_config_write8((u8 *) addr, value);
 417                 break;
 418
 419         case 2:
 420                 if (where & 0x01) {
 421                         printk("pci_write_config_word: misaligned reg [%x]\n",
 422                                where);
 423                         return PCIBIOS_SUCCESSFUL;
 424                 }
 425                 pci_config_write16((u16 *) addr, value);
 426                 break;
 427
 428         case 4:
 429                 if (where & 0x03) {
 430                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 431                                where);
 432                         return PCIBIOS_SUCCESSFUL;
 433                 }
 434                 pci_config_write32(addr, value);
 435                 break;
 436         }
 437
 438         return PCIBIOS_SUCCESSFUL;
 439 }
 440
 441 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 442                                int where, int size, u32 value)
 443 {
 444         struct pci_pbm_info *pbm = bus->sysdata;
 445
 446         if (bus == pbm->pci_bus && devfn == 0x00)
 447                 return pci_host_bridge_write_pci_cfg(bus, devfn, where,
 448                                                      size, value);
 449
 450         if (bus->number)
 451                 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 452
 453         if (sabre_out_of_range(devfn))
 454                 return PCIBIOS_SUCCESSFUL;
 455
 456         switch (size) {
 457         case 1:
 458                 if (where < 8) {
 459                         u32 tmp32;
 460                         u16 tmp16;
 461
 462                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 463                         tmp16 = (u16) tmp32;
 464                         if (where & 1) {
 465                                 value &= 0x00ff;
 466                                 value |= tmp16 << 8;
 467                         } else {
 468                                 value &= 0xff00;
 469                                 value |= tmp16;
 470                         }
 471                         tmp32 = (u32) tmp16;
 472                         return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
 473                 } else
 474                         return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
 475                 break;
 476         case 2:
 477                 if (where < 8)
 478                         return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
 479                 else {
 480                         __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
 481                         __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
 482                 }
 483                 break;
 484         case 4:
 485                 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
 486                 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
 487                 break;
 488         }
 489         return PCIBIOS_SUCCESSFUL;
 490 }
 491
 492 static struct pci_ops sabre_ops = {
 493         .read =         sabre_read_pci_cfg,
 494         .write =        sabre_write_pci_cfg,
 495 };
 496
 497 /* SABRE error handling support. */
 498 static void sabre_check_iommu_error(struct pci_controller_info *p,
 499                                     unsigned long afsr,
 500                                     unsigned long afar)
 501 {
 502         struct pci_iommu *iommu = p->pbm_A.iommu;
 503         unsigned long iommu_tag[16];
 504         unsigned long iommu_data[16];
 505         unsigned long flags;
 506         u64 control;
 507         int i;
 508
 509         spin_lock_irqsave(&iommu->lock, flags);
 510         control = sabre_read(iommu->iommu_control);
 511         if (control & SABRE_IOMMUCTRL_ERR) {
 512                 char *type_string;
 513
 514                 /* Clear the error encountered bit.
 515                  * NOTE: On Sabre this is write 1 to clear,
 516                  *       which is different from Psycho.
 517                  */
 518                 sabre_write(iommu->iommu_control, control);
 519                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 520                 case 1:
 521                         type_string = "Invalid Error";
 522                         break;
 523                 case 3:
 524                         type_string = "ECC Error";
 525                         break;
 526                 default:
 527                         type_string = "Unknown";
 528                         break;
 529                 };
 530                 printk("SABRE%d: IOMMU Error, type[%s]\n",
 531                        p->index, type_string);
 532
 533                 /* Enter diagnostic mode and probe for error'd
 534                  * entries in the IOTLB.
 535                  */
 536                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
 537                 sabre_write(iommu->iommu_control,
 538                             (control | SABRE_IOMMUCTRL_DENAB));
 539                 for (i = 0; i < 16; i++) {
 540                         unsigned long base = p->pbm_A.controller_regs;
 541
 542                         iommu_tag[i] =
 543                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
 544                         iommu_data[i] =
 545                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
 546                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 547                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 548                 }
 549                 sabre_write(iommu->iommu_control, control);
 550
 551                 for (i = 0; i < 16; i++) {
 552                         unsigned long tag, data;
 553
 554                         tag = iommu_tag[i];
 555                         if (!(tag & SABRE_IOMMUTAG_ERR))
 556                                 continue;
 557
 558                         data = iommu_data[i];
 559                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
 560                         case 1:
 561                                 type_string = "Invalid Error";
 562                                 break;
 563                         case 3:
 564                                 type_string = "ECC Error";
 565                                 break;
 566                         default:
 567                                 type_string = "Unknown";
 568                                 break;
 569                         };
 570                         printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
 571                                p->index, i, tag, type_string,
 572                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
 573                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
 574                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
 575                         printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
 576                                p->index, i, data,
 577                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
 578                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
 579                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
 580                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
 581                 }
 582         }
 583         spin_unlock_irqrestore(&iommu->lock, flags);
 584 }
 585
 586 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
 587 {
 588         struct pci_controller_info *p = dev_id;
 589         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
 590         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 591         unsigned long afsr, afar, error_bits;
 592         int reported;
 593
 594         /* Latch uncorrectable error status. */
 595         afar = sabre_read(afar_reg);
 596         afsr = sabre_read(afsr_reg);
 597
 598         /* Clear the primary/secondary error status bits. */
 599         error_bits = afsr &
 600                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 601                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 602                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 603         if (!error_bits)
 604                 return IRQ_NONE;
 605         sabre_write(afsr_reg, error_bits);
 606
 607         /* Log the error. */
 608         printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
 609                p->index,
 610                ((error_bits & SABRE_UEAFSR_PDRD) ?
 611                 "DMA Read" :
 612                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 613                  "DMA Write" : "???")),
 614                ((error_bits & SABRE_UEAFSR_PDTE) ?
 615                 ":Translation Error" : ""));
 616         printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 617                p->index,
 618                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 619                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 620                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 621         printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
 622         printk("SABRE%d: UE Secondary errors [", p->index);
 623         reported = 0;
 624         if (afsr & SABRE_UEAFSR_SDRD) {
 625                 reported++;
 626                 printk("(DMA Read)");
 627         }
 628         if (afsr & SABRE_UEAFSR_SDWR) {
 629                 reported++;
 630                 printk("(DMA Write)");
 631         }
 632         if (afsr & SABRE_UEAFSR_SDTE) {
 633                 reported++;
 634                 printk("(Translation Error)");
 635         }
 636         if (!reported)
 637                 printk("(none)");
 638         printk("]\n");
 639
 640         /* Interrogate IOMMU for error status. */
 641         sabre_check_iommu_error(p, afsr, afar);
 642
 643         return IRQ_HANDLED;
 644 }
 645
 646 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
 647 {
 648         struct pci_controller_info *p = dev_id;
 649         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
 650         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 651         unsigned long afsr, afar, error_bits;
 652         int reported;
 653
 654         /* Latch error status. */
 655         afar = sabre_read(afar_reg);
 656         afsr = sabre_read(afsr_reg);
 657
 658         /* Clear primary/secondary error status bits. */
 659         error_bits = afsr &
 660                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 661                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 662         if (!error_bits)
 663                 return IRQ_NONE;
 664         sabre_write(afsr_reg, error_bits);
 665
 666         /* Log the error. */
 667         printk("SABRE%d: Correctable Error, primary error type[%s]\n",
 668                p->index,
 669                ((error_bits & SABRE_CEAFSR_PDRD) ?
 670                 "DMA Read" :
 671                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 672                  "DMA Write" : "???")));
 673
 674         /* XXX Use syndrome and afar to print out module string just like
 675          * XXX UDB CE trap handler does... -DaveM
 676          */
 677         printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 678                "was_block(%d)\n",
 679                p->index,
 680                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 681                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 682                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 683                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 684         printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
 685         printk("SABRE%d: CE Secondary errors [", p->index);
 686         reported = 0;
 687         if (afsr & SABRE_CEAFSR_SDRD) {
 688                 reported++;
 689                 printk("(DMA Read)");
 690         }
 691         if (afsr & SABRE_CEAFSR_SDWR) {
 692                 reported++;
 693                 printk("(DMA Write)");
 694         }
 695         if (!reported)
 696                 printk("(none)");
 697         printk("]\n");
 698
 699         return IRQ_HANDLED;
 700 }
 701
 702 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
 703 {
 704         unsigned long csr_reg, csr, csr_error_bits;
 705         irqreturn_t ret = IRQ_NONE;
 706         u16 stat;
 707
 708         csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
 709         csr = sabre_read(csr_reg);
 710         csr_error_bits =
 711                 csr & SABRE_PCICTRL_SERR;
 712         if (csr_error_bits) {
 713                 /* Clear the errors.  */
 714                 sabre_write(csr_reg, csr);
 715
 716                 /* Log 'em.  */
 717                 if (csr_error_bits & SABRE_PCICTRL_SERR)
 718                         printk("SABRE%d: PCI SERR signal asserted.\n",
 719                                p->index);
 720                 ret = IRQ_HANDLED;
 721         }
 722         pci_bus_read_config_word(sabre_root_bus, 0,
 723                                  PCI_STATUS, &stat);
 724         if (stat & (PCI_STATUS_PARITY |
 725                     PCI_STATUS_SIG_TARGET_ABORT |
 726                     PCI_STATUS_REC_TARGET_ABORT |
 727                     PCI_STATUS_REC_MASTER_ABORT |
 728                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
 729                 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
 730                        p->index, stat);
 731                 pci_bus_write_config_word(sabre_root_bus, 0,
 732                                           PCI_STATUS, 0xffff);
 733                 ret = IRQ_HANDLED;
 734         }
 735         return ret;
 736 }
 737
 738 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
 739 {
 740         struct pci_controller_info *p = dev_id;
 741         unsigned long afsr_reg, afar_reg;
 742         unsigned long afsr, afar, error_bits;
 743         int reported;
 744
 745         afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
 746         afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
 747
 748         /* Latch error status. */
 749         afar = sabre_read(afar_reg);
 750         afsr = sabre_read(afsr_reg);
 751
 752         /* Clear primary/secondary error status bits. */
 753         error_bits = afsr &
 754                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
 755                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
 756                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
 757                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
 758         if (!error_bits)
 759                 return sabre_pcierr_intr_other(p);
 760         sabre_write(afsr_reg, error_bits);
 761
 762         /* Log the error. */
 763         printk("SABRE%d: PCI Error, primary error type[%s]\n",
 764                p->index,
 765                (((error_bits & SABRE_PIOAFSR_PMA) ?
 766                  "Master Abort" :
 767                  ((error_bits & SABRE_PIOAFSR_PTA) ?
 768                   "Target Abort" :
 769                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
 770                    "Excessive Retries" :
 771                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
 772                     "Parity Error" : "???"))))));
 773         printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
 774                p->index,
 775                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
 776                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
 777         printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
 778         printk("SABRE%d: PCI Secondary errors [", p->index);
 779         reported = 0;
 780         if (afsr & SABRE_PIOAFSR_SMA) {
 781                 reported++;
 782                 printk("(Master Abort)");
 783         }
 784         if (afsr & SABRE_PIOAFSR_STA) {
 785                 reported++;
 786                 printk("(Target Abort)");
 787         }
 788         if (afsr & SABRE_PIOAFSR_SRTRY) {
 789                 reported++;
 790                 printk("(Excessive Retries)");
 791         }
 792         if (afsr & SABRE_PIOAFSR_SPERR) {
 793                 reported++;
 794                 printk("(Parity Error)");
 795         }
 796         if (!reported)
 797                 printk("(none)");
 798         printk("]\n");
 799
 800         /* For the error types shown, scan both PCI buses for devices
 801          * which have logged that error type.
 802          */
 803
 804         /* If we see a Target Abort, this could be the result of an
 805          * IOMMU translation error of some sort.  It is extremely
 806          * useful to log this information as usually it indicates
 807          * a bug in the IOMMU support code or a PCI device driver.
 808          */
 809         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
 810                 sabre_check_iommu_error(p, afsr, afar);
 811                 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 812         }
 813         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
 814                 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 815
 816         /* For excessive retries, SABRE/PBM will abort the device
 817          * and there is no way to specifically check for excessive
 818          * retries in the config space status registers.  So what
 819          * we hope is that we'll catch it via the master/target
 820          * abort events.
 821          */
 822
 823         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
 824                 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
 825
 826         return IRQ_HANDLED;
 827 }
 828
 829 static void sabre_register_error_handlers(struct pci_controller_info *p)
 830 {
 831         struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
 832         struct device_node *dp = pbm->prom_node;
 833         struct of_device *op;
 834         unsigned long base = pbm->controller_regs;
 835         u64 tmp;
 836
 837         if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
 838                 dp = dp->parent;
 839
 840         op = of_find_device_by_node(dp);
 841         if (!op)
 842                 return;
 843
 844         /* Sabre/Hummingbird IRQ property layout is:
 845          * 0: PCI ERR
 846          * 1: UE ERR
 847          * 2: CE ERR
 848          * 3: POWER FAIL
 849          */
 850         if (op->num_irqs < 4)
 851                 return;
 852
 853         /* We clear the error bits in the appropriate AFSR before
 854          * registering the handler so that we don't get spurious
 855          * interrupts.
 856          */
 857         sabre_write(base + SABRE_UE_AFSR,
 858                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 859                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 860                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
 861
 862         request_irq(op->irqs[1], sabre_ue_intr, IRQF_SHARED, "SABRE UE", p);
 863
 864         sabre_write(base + SABRE_CE_AFSR,
 865                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 866                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
 867
 868         request_irq(op->irqs[2], sabre_ce_intr, IRQF_SHARED, "SABRE CE", p);
 869         request_irq(op->irqs[0], sabre_pcierr_intr, IRQF_SHARED,
 870                     "SABRE PCIERR", p);
 871
 872         tmp = sabre_read(base + SABRE_PCICTRL);
 873         tmp |= SABRE_PCICTRL_ERREN;
 874         sabre_write(base + SABRE_PCICTRL, tmp);
 875 }
 876
 877 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
 878 {
 879         struct pci_dev *pdev;
 880
 881         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
 882                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 883                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
 884                         u16 word16;
 885
 886                         pci_read_config_word(pdev, PCI_COMMAND, &word16);
 887                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 888                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
 889                                 PCI_COMMAND_IO;
 890                         pci_write_config_word(pdev, PCI_COMMAND, word16);
 891
 892                         /* Status register bits are "write 1 to clear". */
 893                         pci_write_config_word(pdev, PCI_STATUS, 0xffff);
 894                         pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
 895
 896                         /* Use a primary/seconday latency timer value
 897                          * of 64.
 898                          */
 899                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
 900                         pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
 901
 902                         /* Enable reporting/forwarding of master aborts,
 903                          * parity, and SERR.
 904                          */
 905                         pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
 906                                               (PCI_BRIDGE_CTL_PARITY |
 907                                                PCI_BRIDGE_CTL_SERR |
 908                                                PCI_BRIDGE_CTL_MASTER_ABORT));
 909                 }
 910         }
 911 }
 912
 913 static void sabre_scan_bus(struct pci_controller_info *p)
 914 {
 915         static int once;
 916         struct pci_bus *pbus;
 917
 918         /* The APB bridge speaks to the Sabre host PCI bridge
 919          * at 66Mhz, but the front side of APB runs at 33Mhz
 920          * for both segments.
 921          */
 922         p->pbm_A.is_66mhz_capable = 0;
 923
 924         /* This driver has not been verified to handle
 925          * multiple SABREs yet, so trap this.
 926          *
 927          * Also note that the SABRE host bridge is hardwired
 928          * to live at bus 0.
 929          */
 930         if (once != 0) {
 931                 prom_printf("SABRE: Multiple controllers unsupported.\n");
 932                 prom_halt();
 933         }
 934         once++;
 935
 936         pbus = pci_scan_one_pbm(&p->pbm_A);
 937         if (!pbus)
 938                 return;
 939
 940         sabre_root_bus = pbus;
 941
 942         apb_init(p, pbus);
 943
 944         sabre_register_error_handlers(p);
 945 }
 946
 947 static void sabre_iommu_init(struct pci_controller_info *p,
 948                              int tsbsize, unsigned long dvma_offset,
 949                              u32 dma_mask)
 950 {
 951         struct pci_iommu *iommu = p->pbm_A.iommu;
 952         unsigned long i;
 953         u64 control;
 954
 955         /* Register addresses. */
 956         iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
 957         iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
 958         iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
 959         iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
 960         /* Sabre's IOMMU lacks ctx flushing. */
 961         iommu->iommu_ctxflush = 0;
 962
 963         /* Invalidate TLB Entries. */
 964         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
 965         control |= SABRE_IOMMUCTRL_DENAB;
 966         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
 967
 968         for(i = 0; i < 16; i++) {
 969                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
 970                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
 971         }
 972
 973         /* Leave diag mode enabled for full-flushing done
 974          * in pci_iommu.c
 975          */
 976         pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
 977
 978         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
 979                     __pa(iommu->page_table));
 980
 981         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
 982         control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
 983         control |= SABRE_IOMMUCTRL_ENAB;
 984         switch(tsbsize) {
 985         case 64:
 986                 control |= SABRE_IOMMU_TSBSZ_64K;
 987                 break;
 988         case 128:
 989                 control |= SABRE_IOMMU_TSBSZ_128K;
 990                 break;
 991         default:
 992                 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
 993                 prom_halt();
 994                 break;
 995         }
 996         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
 997 }
 998
 999 static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp)
1000 {
1001         struct pci_pbm_info *pbm;
1002
1003         pbm = &p->pbm_A;
1004         pbm->name = dp->full_name;
1005         printk("%s: SABRE PCI Bus Module\n", pbm->name);
1006
1007         pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1008         pbm->parent = p;
1009         pbm->prom_node = dp;
1010         pbm->pci_first_busno = p->pci_first_busno;
1011         pbm->pci_last_busno = p->pci_last_busno;
1012
1013         pci_determine_mem_io_space(pbm);
1014 }
1015
1016 void sabre_init(struct device_node *dp, char *model_name)
1017 {
1018         const struct linux_prom64_registers *pr_regs;
1019         struct pci_controller_info *p;
1020         struct pci_iommu *iommu;
1021         int tsbsize;
1022         const u32 *busrange;
1023         const u32 *vdma;
1024         u32 upa_portid, dma_mask;
1025         u64 clear_irq;
1026
1027         hummingbird_p = 0;
1028         if (!strcmp(model_name, "pci108e,a001"))
1029                 hummingbird_p = 1;
1030         else if (!strcmp(model_name, "SUNW,sabre")) {
1031                 const char *compat = of_get_property(dp, "compatible", NULL);
1032                 if (compat && !strcmp(compat, "pci108e,a001"))
1033                         hummingbird_p = 1;
1034                 if (!hummingbird_p) {
1035                         struct device_node *dp;
1036
1037                         /* Of course, Sun has to encode things a thousand
1038                          * different ways, inconsistently.
1039                          */
1040                         cpu_find_by_instance(0, &dp, NULL);
1041                         if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
1042                                 hummingbird_p = 1;
1043                 }
1044         }
1045
1046         p = kzalloc(sizeof(*p), GFP_ATOMIC);
1047         if (!p) {
1048                 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1049                 prom_halt();
1050         }
1051
1052         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1053         if (!iommu) {
1054                 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1055                 prom_halt();
1056         }
1057         p->pbm_A.iommu = iommu;
1058
1059         upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1060
1061         p->next = pci_controller_root;
1062         pci_controller_root = p;
1063
1064         p->pbm_A.portid = upa_portid;
1065         p->index = pci_num_controllers++;
1066         p->scan_bus = sabre_scan_bus;
1067         p->pci_ops = &sabre_ops;
1068
1069         /*
1070          * Map in SABRE register set and report the presence of this SABRE.
1071          */
1072
1073         pr_regs = of_get_property(dp, "reg", NULL);
1074
1075         /*
1076          * First REG in property is base of entire SABRE register space.
1077          */
1078         p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1079
1080         /* Clear interrupts */
1081
1082         /* PCI first */
1083         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1084                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1085
1086         /* Then OBIO */
1087         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1088                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1089
1090         /* Error interrupts are enabled later after the bus scan. */
1091         sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1092                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
1093                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1094
1095         /* Now map in PCI config space for entire SABRE. */
1096         p->pbm_A.config_space =
1097                 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1098
1099         vdma = of_get_property(dp, "virtual-dma", NULL);
1100
1101         dma_mask = vdma[0];
1102         switch(vdma[1]) {
1103                 case 0x20000000:
1104                         dma_mask |= 0x1fffffff;
1105                         tsbsize = 64;
1106                         break;
1107                 case 0x40000000:
1108                         dma_mask |= 0x3fffffff;
1109                         tsbsize = 128;
1110                         break;
1111
1112                 case 0x80000000:
1113                         dma_mask |= 0x7fffffff;
1114                         tsbsize = 128;
1115                         break;
1116                 default:
1117                         prom_printf("SABRE: strange virtual-dma size.\n");
1118                         prom_halt();
1119         }
1120
1121         sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1122
1123         busrange = of_get_property(dp, "bus-range", NULL);
1124         p->pci_first_busno = busrange[0];
1125         p->pci_last_busno = busrange[1];
1126
1127         /*
1128          * Look for APB underneath.
1129          */
1130         sabre_pbm_init(p, dp);
1131 }