arch/sparc64/kernel/rtrap.S

   1 /* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $
   2  * rtrap.S: Preparing for return from trap on Sparc V9.
   3  *
   4  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   5  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #include <linux/config.h>
   9
  10 #include <asm/asi.h>
  11 #include <asm/pstate.h>
  12 #include <asm/ptrace.h>
  13 #include <asm/spitfire.h>
  14 #include <asm/head.h>
  15 #include <asm/visasm.h>
  16 #include <asm/processor.h>
  17
  18 #define         RTRAP_PSTATE            (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
  19 #define         RTRAP_PSTATE_IRQOFF     (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
  20 #define         RTRAP_PSTATE_AG_IRQOFF  (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
  21
  22                 /* Register %l6 keeps track of whether we are returning
  23                  * from a system call or not.  It is cleared if we call
  24                  * do_notify_resume, and it must not be otherwise modified
  25                  * until we fully commit to returning to userspace.
  26                  */
  27
  28                 .text
  29                 .align                  32
  30 __handle_softirq:
  31                 call                    do_softirq
  32                  nop
  33                 ba,a,pt                 %xcc, __handle_softirq_continue
  34                  nop
  35 __handle_preemption:
  36                 call                    schedule
  37                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  38                 ba,pt                   %xcc, __handle_preemption_continue
  39                  wrpr                   %g0, RTRAP_PSTATE_IRQOFF, %pstate
  40
  41 __handle_user_windows:
  42                 call                    fault_in_user_windows
  43                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  44                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  45                 /* Redo sched+sig checks */
  46                 ldx                     [%g6 + TI_FLAGS], %l0
  47                 andcc                   %l0, _TIF_NEED_RESCHED, %g0
  48
  49                 be,pt                   %xcc, 1f
  50                  nop
  51                 call                    schedule
  52                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  53                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  54                 ldx                     [%g6 + TI_FLAGS], %l0
  55
  56 1:              andcc                   %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
  57                 be,pt                   %xcc, __handle_user_windows_continue
  58                  nop
  59                 mov                     %l5, %o1
  60                 mov                     %l6, %o2
  61                 add                     %sp, PTREGS_OFF, %o0
  62                 mov                     %l0, %o3
  63
  64                 call                    do_notify_resume
  65                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  66                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  67                 clr                     %l6
  68                 /* Signal delivery can modify pt_regs tstate, so we must
  69                  * reload it.
  70                  */
  71                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
  72                 sethi                   %hi(0xf << 20), %l4
  73                 and                     %l1, %l4, %l4
  74                 ba,pt                   %xcc, __handle_user_windows_continue
  75
  76                  andn                   %l1, %l4, %l1
  77 __handle_perfctrs:
  78                 call                    update_perfctrs
  79                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  80                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  81                 ldub                    [%g6 + TI_WSAVED], %o2
  82                 brz,pt                  %o2, 1f
  83                  nop
  84                 /* Redo userwin+sched+sig checks */
  85                 call                    fault_in_user_windows
  86
  87                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  88                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  89                 ldx                     [%g6 + TI_FLAGS], %l0
  90                 andcc                   %l0, _TIF_NEED_RESCHED, %g0
  91                 be,pt                   %xcc, 1f
  92
  93                  nop
  94                 call                    schedule
  95                  wrpr                   %g0, RTRAP_PSTATE, %pstate
  96                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
  97                 ldx                     [%g6 + TI_FLAGS], %l0
  98 1:              andcc                   %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
  99
 100                 be,pt                   %xcc, __handle_perfctrs_continue
 101                  sethi                  %hi(TSTATE_PEF), %o0
 102                 mov                     %l5, %o1
 103                 mov                     %l6, %o2
 104                 add                     %sp, PTREGS_OFF, %o0
 105                 mov                     %l0, %o3
 106                 call                    do_notify_resume
 107
 108                  wrpr                   %g0, RTRAP_PSTATE, %pstate
 109                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 110                 clr                     %l6
 111                 /* Signal delivery can modify pt_regs tstate, so we must
 112                  * reload it.
 113                  */
 114                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 115                 sethi                   %hi(0xf << 20), %l4
 116                 and                     %l1, %l4, %l4
 117                 andn                    %l1, %l4, %l1
 118                 ba,pt                   %xcc, __handle_perfctrs_continue
 119
 120                  sethi                  %hi(TSTATE_PEF), %o0
 121 __handle_userfpu:
 122                 rd                      %fprs, %l5
 123                 andcc                   %l5, FPRS_FEF, %g0
 124                 sethi                   %hi(TSTATE_PEF), %o0
 125                 be,a,pn                 %icc, __handle_userfpu_continue
 126                  andn                   %l1, %o0, %l1
 127                 ba,a,pt                 %xcc, __handle_userfpu_continue
 128
 129 __handle_signal:
 130                 mov                     %l5, %o1
 131                 mov                     %l6, %o2
 132                 add                     %sp, PTREGS_OFF, %o0
 133                 mov                     %l0, %o3
 134                 call                    do_notify_resume
 135                  wrpr                   %g0, RTRAP_PSTATE, %pstate
 136                 wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 137                 clr                     %l6
 138
 139                 /* Signal delivery can modify pt_regs tstate, so we must
 140                  * reload it.
 141                  */
 142                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 143                 sethi                   %hi(0xf << 20), %l4
 144                 and                     %l1, %l4, %l4
 145                 ba,pt                   %xcc, __handle_signal_continue
 146                  andn                   %l1, %l4, %l1
 147
 148                 .align                  64
 149                 .globl                  rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
 150 rtrap_irq:
 151 rtrap_clr_l6:   clr                     %l6
 152 rtrap:
 153 #ifndef CONFIG_SMP
 154                 sethi                   %hi(per_cpu____cpu_data), %l0
 155                 lduw                    [%l0 + %lo(per_cpu____cpu_data)], %l1
 156 #else
 157                 sethi                   %hi(per_cpu____cpu_data), %l0
 158                 or                      %l0, %lo(per_cpu____cpu_data), %l0
 159                 lduw                    [%l0 + %g5], %l1
 160 #endif
 161                 cmp                     %l1, 0
 162
 163                 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
 164                 bne,pn                  %icc, __handle_softirq
 165                  ldx                    [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 166 __handle_softirq_continue:
 167 rtrap_xcall:
 168                 sethi                   %hi(0xf << 20), %l4
 169                 andcc                   %l1, TSTATE_PRIV, %l3
 170                 and                     %l1, %l4, %l4
 171                 bne,pn                  %icc, to_kernel
 172                  andn                   %l1, %l4, %l1
 173
 174                 /* We must hold IRQs off and atomically test schedule+signal
 175                  * state, then hold them off all the way back to userspace.
 176                  * If we are returning to kernel, none of this matters.
 177                  *
 178                  * If we do not do this, there is a window where we would do
 179                  * the tests, later the signal/resched event arrives but we do
 180                  * not process it since we are still in kernel mode.  It would
 181                  * take until the next local IRQ before the signal/resched
 182                  * event would be handled.
 183                  *
 184                  * This also means that if we have to deal with performance
 185                  * counters or user windows, we have to redo all of these
 186                  * sched+signal checks with IRQs disabled.
 187                  */
 188 to_user:        wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
 189                 wrpr                    0, %pil
 190 __handle_preemption_continue:
 191                 ldx                     [%g6 + TI_FLAGS], %l0
 192                 sethi                   %hi(_TIF_USER_WORK_MASK), %o0
 193                 or                      %o0, %lo(_TIF_USER_WORK_MASK), %o0
 194                 andcc                   %l0, %o0, %g0
 195                 sethi                   %hi(TSTATE_PEF), %o0
 196                 be,pt                   %xcc, user_nowork
 197                  andcc                  %l1, %o0, %g0
 198                 andcc                   %l0, _TIF_NEED_RESCHED, %g0
 199                 bne,pn                  %xcc, __handle_preemption
 200                  andcc                  %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0
 201                 bne,pn                  %xcc, __handle_signal
 202 __handle_signal_continue:
 203                  ldub                   [%g6 + TI_WSAVED], %o2
 204                 brnz,pn                 %o2, __handle_user_windows
 205                  nop
 206 __handle_user_windows_continue:
 207                 ldx                     [%g6 + TI_FLAGS], %l5
 208                 andcc                   %l5, _TIF_PERFCTR, %g0
 209                 sethi                   %hi(TSTATE_PEF), %o0
 210                 bne,pn                  %xcc, __handle_perfctrs
 211 __handle_perfctrs_continue:
 212                  andcc                  %l1, %o0, %g0
 213
 214                 /* This fpdepth clear is necessary for non-syscall rtraps only */
 215 user_nowork:
 216                 bne,pn                  %xcc, __handle_userfpu
 217                  stb                    %g0, [%g6 + TI_FPDEPTH]
 218 __handle_userfpu_continue:
 219
 220 rt_continue:    ldx                     [%sp + PTREGS_OFF + PT_V9_G1], %g1
 221                 ldx                     [%sp + PTREGS_OFF + PT_V9_G2], %g2
 222
 223                 ldx                     [%sp + PTREGS_OFF + PT_V9_G3], %g3
 224                 ldx                     [%sp + PTREGS_OFF + PT_V9_G4], %g4
 225                 ldx                     [%sp + PTREGS_OFF + PT_V9_G5], %g5
 226                 brz,pt                  %l3, 1f
 227                 mov                     %g6, %l2
 228
 229                 /* Must do this before thread reg is clobbered below.  */
 230                 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
 231 1:
 232                 ldx                     [%sp + PTREGS_OFF + PT_V9_G6], %g6
 233                 ldx                     [%sp + PTREGS_OFF + PT_V9_G7], %g7
 234
 235                 /* Normal globals are restored, go to trap globals.  */
 236 661:            wrpr                    %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
 237                 .section                .gl_1insn_patch, "ax"
 238                 .word                   661b
 239                 SET_GL(1)
 240                 .previous
 241
 242                 mov                     %l2, %g6
 243
 244                 ldx                     [%sp + PTREGS_OFF + PT_V9_I0], %i0
 245                 ldx                     [%sp + PTREGS_OFF + PT_V9_I1], %i1
 246
 247                 ldx                     [%sp + PTREGS_OFF + PT_V9_I2], %i2
 248                 ldx                     [%sp + PTREGS_OFF + PT_V9_I3], %i3
 249                 ldx                     [%sp + PTREGS_OFF + PT_V9_I4], %i4
 250                 ldx                     [%sp + PTREGS_OFF + PT_V9_I5], %i5
 251                 ldx                     [%sp + PTREGS_OFF + PT_V9_I6], %i6
 252                 ldx                     [%sp + PTREGS_OFF + PT_V9_I7], %i7
 253                 ldx                     [%sp + PTREGS_OFF + PT_V9_TPC], %l2
 254                 ldx                     [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
 255
 256                 ld                      [%sp + PTREGS_OFF + PT_V9_Y], %o3
 257                 wr                      %o3, %g0, %y
 258                 srl                     %l4, 20, %l4
 259                 wrpr                    %l4, 0x0, %pil
 260                 wrpr                    %g0, 0x1, %tl
 261                 wrpr                    %l1, %g0, %tstate
 262                 wrpr                    %l2, %g0, %tpc
 263                 wrpr                    %o2, %g0, %tnpc
 264
 265                 brnz,pn                 %l3, kern_rtt
 266                  mov                    PRIMARY_CONTEXT, %l7
 267                 ldxa                    [%l7 + %l7] ASI_DMMU, %l0
 268                 sethi                   %hi(sparc64_kern_pri_nuc_bits), %l1
 269                 ldx                     [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
 270                 or                      %l0, %l1, %l0
 271                 stxa                    %l0, [%l7] ASI_DMMU
 272                 sethi                   %hi(KERNBASE), %l7
 273                 flush                   %l7
 274                 rdpr                    %wstate, %l1
 275                 rdpr                    %otherwin, %l2
 276                 srl                     %l1, 3, %l1
 277
 278                 wrpr                    %l2, %g0, %canrestore
 279                 wrpr                    %l1, %g0, %wstate
 280                 brnz,pt                 %l2, user_rtt_restore
 281                  wrpr                   %g0, %g0, %otherwin
 282
 283                 ldx                     [%g6 + TI_FLAGS], %g3
 284                 wr                      %g0, ASI_AIUP, %asi
 285                 rdpr                    %cwp, %g1
 286                 andcc                   %g3, _TIF_32BIT, %g0
 287                 sub                     %g1, 1, %g1
 288                 bne,pt                  %xcc, user_rtt_fill_32bit
 289                  wrpr                   %g1, %cwp
 290                 ba,a,pt                 %xcc, user_rtt_fill_64bit
 291
 292 user_rtt_fill_fixup:
 293                 rdpr    %cwp, %g1
 294                 add     %g1, 1, %g1
 295                 wrpr    %g1, 0x0, %cwp
 296
 297                 rdpr    %wstate, %g2
 298                 sll     %g2, 3, %g2
 299                 wrpr    %g2, 0x0, %wstate
 300
 301                 /* We know %canrestore and %otherwin are both zero.  */
 302
 303                 sethi   %hi(sparc64_kern_pri_context), %g2
 304                 ldx     [%g2 + %lo(sparc64_kern_pri_context)], %g2
 305                 mov     PRIMARY_CONTEXT, %g1
 306                 stxa    %g2, [%g1] ASI_DMMU
 307                 sethi   %hi(KERNBASE), %g1
 308                 flush   %g1
 309
 310                 or      %g4, FAULT_CODE_WINFIXUP, %g4
 311                 stb     %g4, [%g6 + TI_FAULT_CODE]
 312                 stx     %g5, [%g6 + TI_FAULT_ADDR]
 313
 314                 mov     %g6, %l1
 315                 wrpr    %g0, 0x0, %tl
 316                 wrpr    %g0, RTRAP_PSTATE, %pstate
 317
 318 661:            nop
 319                 .section                .gl_1insn_patch, "ax"
 320                 .word                   661b
 321                 SET_GL(0)
 322                 .previous
 323
 324                 mov     %l1, %g6
 325                 ldx     [%g6 + TI_TASK], %g4
 326                 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
 327                 call    do_sparc64_fault
 328                  add    %sp, PTREGS_OFF, %o0
 329                 ba,pt   %xcc, rtrap
 330                  nop
 331
 332 user_rtt_pre_restore:
 333                 add                     %g1, 1, %g1
 334                 wrpr                    %g1, 0x0, %cwp
 335
 336 user_rtt_restore:
 337                 restore
 338                 rdpr                    %canrestore, %g1
 339                 wrpr                    %g1, 0x0, %cleanwin
 340                 retry
 341                 nop
 342
 343 kern_rtt:       rdpr                    %canrestore, %g1
 344                 brz,pn                  %g1, kern_rtt_fill
 345                  nop
 346 kern_rtt_restore:
 347                 restore
 348                 retry
 349
 350 to_kernel:
 351 #ifdef CONFIG_PREEMPT
 352                 ldsw                    [%g6 + TI_PRE_COUNT], %l5
 353                 brnz                    %l5, kern_fpucheck
 354                  ldx                    [%g6 + TI_FLAGS], %l5
 355                 andcc                   %l5, _TIF_NEED_RESCHED, %g0
 356                 be,pt                   %xcc, kern_fpucheck
 357                  srl                    %l4, 20, %l5
 358                 cmp                     %l5, 0
 359                 bne,pn                  %xcc, kern_fpucheck
 360                  sethi                  %hi(PREEMPT_ACTIVE), %l6
 361                 stw                     %l6, [%g6 + TI_PRE_COUNT]
 362                 call                    schedule
 363                  nop
 364                 ba,pt                   %xcc, rtrap
 365                  stw                    %g0, [%g6 + TI_PRE_COUNT]
 366 #endif
 367 kern_fpucheck:  ldub                    [%g6 + TI_FPDEPTH], %l5
 368                 brz,pt                  %l5, rt_continue
 369                  srl                    %l5, 1, %o0
 370                 add                     %g6, TI_FPSAVED, %l6
 371                 ldub                    [%l6 + %o0], %l2
 372                 sub                     %l5, 2, %l5
 373
 374                 add                     %g6, TI_GSR, %o1
 375                 andcc                   %l2, (FPRS_FEF|FPRS_DU), %g0
 376                 be,pt                   %icc, 2f
 377                  and                    %l2, FPRS_DL, %l6
 378                 andcc                   %l2, FPRS_FEF, %g0
 379                 be,pn                   %icc, 5f
 380                  sll                    %o0, 3, %o5
 381                 rd                      %fprs, %g1
 382
 383                 wr                      %g1, FPRS_FEF, %fprs
 384                 ldx                     [%o1 + %o5], %g1
 385                 add                     %g6, TI_XFSR, %o1
 386                 sll                     %o0, 8, %o2
 387                 add                     %g6, TI_FPREGS, %o3
 388                 brz,pn                  %l6, 1f
 389                  add                    %g6, TI_FPREGS+0x40, %o4
 390
 391                 membar                  #Sync
 392                 ldda                    [%o3 + %o2] ASI_BLK_P, %f0
 393                 ldda                    [%o4 + %o2] ASI_BLK_P, %f16
 394                 membar                  #Sync
 395 1:              andcc                   %l2, FPRS_DU, %g0
 396                 be,pn                   %icc, 1f
 397                  wr                     %g1, 0, %gsr
 398                 add                     %o2, 0x80, %o2
 399                 membar                  #Sync
 400                 ldda                    [%o3 + %o2] ASI_BLK_P, %f32
 401                 ldda                    [%o4 + %o2] ASI_BLK_P, %f48
 402 1:              membar                  #Sync
 403                 ldx                     [%o1 + %o5], %fsr
 404 2:              stb                     %l5, [%g6 + TI_FPDEPTH]
 405                 ba,pt                   %xcc, rt_continue
 406                  nop
 407 5:              wr                      %g0, FPRS_FEF, %fprs
 408                 sll                     %o0, 8, %o2
 409
 410                 add                     %g6, TI_FPREGS+0x80, %o3
 411                 add                     %g6, TI_FPREGS+0xc0, %o4
 412                 membar                  #Sync
 413                 ldda                    [%o3 + %o2] ASI_BLK_P, %f32
 414                 ldda                    [%o4 + %o2] ASI_BLK_P, %f48
 415                 membar                  #Sync
 416                 wr                      %g0, FPRS_DU, %fprs
 417                 ba,pt                   %xcc, rt_continue
 418                  stb                    %l5, [%g6 + TI_FPDEPTH]