1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
16 #include <linux/hugetlb.h>
17 #include <linux/slab.h>
18 #include <linux/initrd.h>
19 #include <linux/swap.h>
20 #include <linux/pagemap.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
28 #include <asm/system.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
39 #include <asm/starfire.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
44 #include <asm/hypervisor.h>
46 extern void device_scan(void);
48 #define MAX_PHYS_ADDRESS (1UL << 42UL)
49 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50 #define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53 unsigned long kern_linear_pte_xor[2] __read_mostly;
55 /* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
61 /* A special kernel TSB for 4MB and 256MB linear mappings. */
62 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
66 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
67 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
68 static int pavail_ents __initdata;
69 static int pavail_rescan_ents __initdata;
71 static int cmp_p64(const void *a, const void *b)
73 const struct linux_prom64_registers *x = a, *y = b;
75 if (x->phys_addr > y->phys_addr)
77 if (x->phys_addr < y->phys_addr)
82 static void __init read_obp_memory(const char *property,
83 struct linux_prom64_registers *regs,
86 int node = prom_finddevice("/memory");
87 int prop_size = prom_getproplen(node, property);
90 ents = prop_size / sizeof(struct linux_prom64_registers);
91 if (ents > MAX_BANKS) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
98 ret = prom_getproperty(node, property, (char *) regs, prop_size);
100 prom_printf("Couldn't get %s property from /memory.\n");
106 /* Sanitize what we got from the firmware, by page aligning
109 for (i = 0; i < ents; i++) {
110 unsigned long base, size;
112 base = regs[i].phys_addr;
113 size = regs[i].reg_size;
116 if (base & ~PAGE_MASK) {
117 unsigned long new_base = PAGE_ALIGN(base);
119 size -= new_base - base;
120 if ((long) size < 0L)
124 regs[i].phys_addr = base;
125 regs[i].reg_size = size;
127 sort(regs, ents, sizeof(struct linux_prom64_registers),
131 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
133 /* Kernel physical address base and size in bytes. */
134 unsigned long kern_base __read_mostly;
135 unsigned long kern_size __read_mostly;
137 /* get_new_mmu_context() uses "cache + 1". */
138 DEFINE_SPINLOCK(ctx_alloc_lock);
139 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
140 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
141 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
143 /* References to special section boundaries */
144 extern char _start[], _end[];
146 /* Initial ramdisk setup */
147 extern unsigned long sparc_ramdisk_image64;
148 extern unsigned int sparc_ramdisk_image;
149 extern unsigned int sparc_ramdisk_size;
151 struct page *mem_map_zero __read_mostly;
153 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
155 unsigned long sparc64_kern_pri_context __read_mostly;
156 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
157 unsigned long sparc64_kern_sec_context __read_mostly;
161 kmem_cache_t *pgtable_cache __read_mostly;
163 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
168 void pgtable_cache_init(void)
170 pgtable_cache = kmem_cache_create("pgtable_cache",
171 PAGE_SIZE, PAGE_SIZE,
173 SLAB_MUST_HWCACHE_ALIGN,
176 if (!pgtable_cache) {
177 prom_printf("pgtable_cache_init(): Could not create!\n");
182 #ifdef CONFIG_DEBUG_DCFLUSH
183 atomic_t dcpage_flushes = ATOMIC_INIT(0);
185 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
189 inline void flush_dcache_page_impl(struct page *page)
191 BUG_ON(tlb_type == hypervisor);
192 #ifdef CONFIG_DEBUG_DCFLUSH
193 atomic_inc(&dcpage_flushes);
196 #ifdef DCACHE_ALIASING_POSSIBLE
197 __flush_dcache_page(page_address(page),
198 ((tlb_type == spitfire) &&
199 page_mapping(page) != NULL));
201 if (page_mapping(page) != NULL &&
202 tlb_type == spitfire)
203 __flush_icache_page(__pa(page_address(page)));
207 #define PG_dcache_dirty PG_arch_1
208 #define PG_dcache_cpu_shift 24UL
209 #define PG_dcache_cpu_mask (256UL - 1UL)
212 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
215 #define dcache_dirty_cpu(page) \
216 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
218 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
220 unsigned long mask = this_cpu;
221 unsigned long non_cpu_bits;
223 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
224 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
226 __asm__ __volatile__("1:\n\t"
228 "and %%g7, %1, %%g1\n\t"
229 "or %%g1, %0, %%g1\n\t"
230 "casx [%2], %%g7, %%g1\n\t"
232 "membar #StoreLoad | #StoreStore\n\t"
233 "bne,pn %%xcc, 1b\n\t"
236 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
240 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
242 unsigned long mask = (1UL << PG_dcache_dirty);
244 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
247 "srlx %%g7, %4, %%g1\n\t"
248 "and %%g1, %3, %%g1\n\t"
250 "bne,pn %%icc, 2f\n\t"
251 " andn %%g7, %1, %%g1\n\t"
252 "casx [%2], %%g7, %%g1\n\t"
254 "membar #StoreLoad | #StoreStore\n\t"
255 "bne,pn %%xcc, 1b\n\t"
259 : "r" (cpu), "r" (mask), "r" (&page->flags),
260 "i" (PG_dcache_cpu_mask),
261 "i" (PG_dcache_cpu_shift)
265 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
267 unsigned long tsb_addr = (unsigned long) ent;
269 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
270 tsb_addr = __pa(tsb_addr);
272 __tsb_insert(tsb_addr, tag, pte);
275 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
276 unsigned long _PAGE_SZBITS __read_mostly;
278 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
280 struct mm_struct *mm;
282 unsigned long tag, flags;
284 if (tlb_type != hypervisor) {
285 unsigned long pfn = pte_pfn(pte);
286 unsigned long pg_flags;
289 if (pfn_valid(pfn) &&
290 (page = pfn_to_page(pfn), page_mapping(page)) &&
291 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
292 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
294 int this_cpu = get_cpu();
296 /* This is just to optimize away some function calls
300 flush_dcache_page_impl(page);
302 smp_flush_dcache_page_impl(page, cpu);
304 clear_dcache_dirty_cpu(page, cpu);
312 spin_lock_irqsave(&mm->context.lock, flags);
314 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
315 (mm->context.tsb_nentries - 1UL)];
316 tag = (address >> 22UL);
317 tsb_insert(tsb, tag, pte_val(pte));
319 spin_unlock_irqrestore(&mm->context.lock, flags);
322 void flush_dcache_page(struct page *page)
324 struct address_space *mapping;
327 if (tlb_type == hypervisor)
330 /* Do not bother with the expensive D-cache flush if it
331 * is merely the zero page. The 'bigcore' testcase in GDB
332 * causes this case to run millions of times.
334 if (page == ZERO_PAGE(0))
337 this_cpu = get_cpu();
339 mapping = page_mapping(page);
340 if (mapping && !mapping_mapped(mapping)) {
341 int dirty = test_bit(PG_dcache_dirty, &page->flags);
343 int dirty_cpu = dcache_dirty_cpu(page);
345 if (dirty_cpu == this_cpu)
347 smp_flush_dcache_page_impl(page, dirty_cpu);
349 set_dcache_dirty(page, this_cpu);
351 /* We could delay the flush for the !page_mapping
352 * case too. But that case is for exec env/arg
353 * pages and those are %99 certainly going to get
354 * faulted into the tlb (and thus flushed) anyways.
356 flush_dcache_page_impl(page);
363 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
365 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
366 if (tlb_type == spitfire) {
369 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
370 __flush_icache_page(__get_phys(kaddr));
376 printk("Mem-info:\n");
378 printk("Free swap: %6ldkB\n",
379 nr_swap_pages << (PAGE_SHIFT-10));
380 printk("%ld pages of RAM\n", num_physpages);
381 printk("%d free pages\n", nr_free_pages());
384 void mmu_info(struct seq_file *m)
386 if (tlb_type == cheetah)
387 seq_printf(m, "MMU Type\t: Cheetah\n");
388 else if (tlb_type == cheetah_plus)
389 seq_printf(m, "MMU Type\t: Cheetah+\n");
390 else if (tlb_type == spitfire)
391 seq_printf(m, "MMU Type\t: Spitfire\n");
392 else if (tlb_type == hypervisor)
393 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
395 seq_printf(m, "MMU Type\t: ???\n");
397 #ifdef CONFIG_DEBUG_DCFLUSH
398 seq_printf(m, "DCPageFlushes\t: %d\n",
399 atomic_read(&dcpage_flushes));
401 seq_printf(m, "DCPageFlushesXC\t: %d\n",
402 atomic_read(&dcpage_flushes_xcall));
403 #endif /* CONFIG_SMP */
404 #endif /* CONFIG_DEBUG_DCFLUSH */
407 struct linux_prom_translation {
413 /* Exported for kernel TLB miss handling in ktlb.S */
414 struct linux_prom_translation prom_trans[512] __read_mostly;
415 unsigned int prom_trans_ents __read_mostly;
417 /* Exported for SMP bootup purposes. */
418 unsigned long kern_locked_tte_data;
420 /* The obp translations are saved based on 8k pagesize, since obp can
421 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
422 * HI_OBP_ADDRESS range are handled in ktlb.S.
424 static inline int in_obp_range(unsigned long vaddr)
426 return (vaddr >= LOW_OBP_ADDRESS &&
427 vaddr < HI_OBP_ADDRESS);
430 static int cmp_ptrans(const void *a, const void *b)
432 const struct linux_prom_translation *x = a, *y = b;
434 if (x->virt > y->virt)
436 if (x->virt < y->virt)
441 /* Read OBP translations property into 'prom_trans[]'. */
442 static void __init read_obp_translations(void)
444 int n, node, ents, first, last, i;
446 node = prom_finddevice("/virtual-memory");
447 n = prom_getproplen(node, "translations");
448 if (unlikely(n == 0 || n == -1)) {
449 prom_printf("prom_mappings: Couldn't get size.\n");
452 if (unlikely(n > sizeof(prom_trans))) {
453 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
457 if ((n = prom_getproperty(node, "translations",
458 (char *)&prom_trans[0],
459 sizeof(prom_trans))) == -1) {
460 prom_printf("prom_mappings: Couldn't get property.\n");
464 n = n / sizeof(struct linux_prom_translation);
468 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
471 /* Now kick out all the non-OBP entries. */
472 for (i = 0; i < ents; i++) {
473 if (in_obp_range(prom_trans[i].virt))
477 for (; i < ents; i++) {
478 if (!in_obp_range(prom_trans[i].virt))
483 for (i = 0; i < (last - first); i++) {
484 struct linux_prom_translation *src = &prom_trans[i + first];
485 struct linux_prom_translation *dest = &prom_trans[i];
489 for (; i < ents; i++) {
490 struct linux_prom_translation *dest = &prom_trans[i];
491 dest->virt = dest->size = dest->data = 0x0UL;
494 prom_trans_ents = last - first;
496 if (tlb_type == spitfire) {
497 /* Clear diag TTE bits. */
498 for (i = 0; i < prom_trans_ents; i++)
499 prom_trans[i].data &= ~0x0003fe0000000000UL;
503 static void __init hypervisor_tlb_lock(unsigned long vaddr,
507 register unsigned long func asm("%o5");
508 register unsigned long arg0 asm("%o0");
509 register unsigned long arg1 asm("%o1");
510 register unsigned long arg2 asm("%o2");
511 register unsigned long arg3 asm("%o3");
513 func = HV_FAST_MMU_MAP_PERM_ADDR;
518 __asm__ __volatile__("ta 0x80"
519 : "=&r" (func), "=&r" (arg0),
520 "=&r" (arg1), "=&r" (arg2),
522 : "0" (func), "1" (arg0), "2" (arg1),
523 "3" (arg2), "4" (arg3));
525 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
526 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
531 static unsigned long kern_large_tte(unsigned long paddr);
533 static void __init remap_kernel(void)
535 unsigned long phys_page, tte_vaddr, tte_data;
536 int tlb_ent = sparc64_highest_locked_tlbent();
538 tte_vaddr = (unsigned long) KERNBASE;
539 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
540 tte_data = kern_large_tte(phys_page);
542 kern_locked_tte_data = tte_data;
544 /* Now lock us into the TLBs via Hypervisor or OBP. */
545 if (tlb_type == hypervisor) {
546 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
547 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
549 tte_vaddr += 0x400000;
550 tte_data += 0x400000;
551 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
552 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
555 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
556 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
559 prom_dtlb_load(tlb_ent,
561 tte_vaddr + 0x400000);
562 prom_itlb_load(tlb_ent,
564 tte_vaddr + 0x400000);
566 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
568 if (tlb_type == cheetah_plus) {
569 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
570 CTX_CHEETAH_PLUS_NUC);
571 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
572 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
577 static void __init inherit_prom_mappings(void)
579 read_obp_translations();
581 /* Now fixup OBP's idea about where we really are mapped. */
582 prom_printf("Remapping the kernel... ");
584 prom_printf("done.\n");
587 void prom_world(int enter)
590 set_fs((mm_segment_t) { get_thread_current_ds() });
592 __asm__ __volatile__("flushw");
595 #ifdef DCACHE_ALIASING_POSSIBLE
596 void __flush_dcache_range(unsigned long start, unsigned long end)
600 if (tlb_type == spitfire) {
603 for (va = start; va < end; va += 32) {
604 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
608 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
611 for (va = start; va < end; va += 32)
612 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
616 "i" (ASI_DCACHE_INVALIDATE));
619 #endif /* DCACHE_ALIASING_POSSIBLE */
621 /* Caller does TLB context flushing on local CPU if necessary.
622 * The caller also ensures that CTX_VALID(mm->context) is false.
624 * We must be careful about boundary cases so that we never
625 * let the user have CTX 0 (nucleus) or we ever use a CTX
626 * version of zero (and thus NO_CONTEXT would not be caught
627 * by version mis-match tests in mmu_context.h).
629 * Always invoked with interrupts disabled.
631 void get_new_mmu_context(struct mm_struct *mm)
633 unsigned long ctx, new_ctx;
634 unsigned long orig_pgsz_bits;
638 spin_lock_irqsave(&ctx_alloc_lock, flags);
639 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
640 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
641 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
643 if (new_ctx >= (1 << CTX_NR_BITS)) {
644 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
645 if (new_ctx >= ctx) {
647 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
650 new_ctx = CTX_FIRST_VERSION;
652 /* Don't call memset, for 16 entries that's just
655 mmu_context_bmap[0] = 3;
656 mmu_context_bmap[1] = 0;
657 mmu_context_bmap[2] = 0;
658 mmu_context_bmap[3] = 0;
659 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
660 mmu_context_bmap[i + 0] = 0;
661 mmu_context_bmap[i + 1] = 0;
662 mmu_context_bmap[i + 2] = 0;
663 mmu_context_bmap[i + 3] = 0;
669 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
670 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
672 tlb_context_cache = new_ctx;
673 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
674 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
676 if (unlikely(new_version))
677 smp_new_mmu_context_version();
680 void sparc_ultra_dump_itlb(void)
684 if (tlb_type == spitfire) {
685 printk ("Contents of itlb: ");
686 for (slot = 0; slot < 14; slot++) printk (" ");
687 printk ("%2x:%016lx,%016lx\n",
689 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
690 for (slot = 1; slot < 64; slot+=3) {
691 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
693 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
695 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
697 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
699 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
700 printk ("Contents of itlb0:\n");
701 for (slot = 0; slot < 16; slot+=2) {
702 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
704 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
706 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
708 printk ("Contents of itlb2:\n");
709 for (slot = 0; slot < 128; slot+=2) {
710 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
712 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
714 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
719 void sparc_ultra_dump_dtlb(void)
723 if (tlb_type == spitfire) {
724 printk ("Contents of dtlb: ");
725 for (slot = 0; slot < 14; slot++) printk (" ");
726 printk ("%2x:%016lx,%016lx\n", 0,
727 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
728 for (slot = 1; slot < 64; slot+=3) {
729 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
731 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
733 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
735 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
737 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
738 printk ("Contents of dtlb0:\n");
739 for (slot = 0; slot < 16; slot+=2) {
740 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
742 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
744 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
746 printk ("Contents of dtlb2:\n");
747 for (slot = 0; slot < 512; slot+=2) {
748 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
750 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
752 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
754 if (tlb_type == cheetah_plus) {
755 printk ("Contents of dtlb3:\n");
756 for (slot = 0; slot < 512; slot+=2) {
757 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
759 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
761 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
767 extern unsigned long cmdline_memory_size;
769 /* Find a free area for the bootmem map, avoiding the kernel image
770 * and the initial ramdisk.
772 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
773 unsigned long end_pfn)
775 unsigned long avoid_start, avoid_end, bootmap_size;
778 bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
779 bootmap_size = ALIGN(bootmap_size, sizeof(long));
781 avoid_start = avoid_end = 0;
782 #ifdef CONFIG_BLK_DEV_INITRD
783 avoid_start = initrd_start;
784 avoid_end = PAGE_ALIGN(initrd_end);
787 #ifdef CONFIG_DEBUG_BOOTMEM
788 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
789 kern_base, PAGE_ALIGN(kern_base + kern_size),
790 avoid_start, avoid_end);
792 for (i = 0; i < pavail_ents; i++) {
793 unsigned long start, end;
795 start = pavail[i].phys_addr;
796 end = start + pavail[i].reg_size;
798 while (start < end) {
799 if (start >= kern_base &&
800 start < PAGE_ALIGN(kern_base + kern_size)) {
801 start = PAGE_ALIGN(kern_base + kern_size);
804 if (start >= avoid_start && start < avoid_end) {
809 if ((end - start) < bootmap_size)
812 if (start < kern_base &&
813 (start + bootmap_size) > kern_base) {
814 start = PAGE_ALIGN(kern_base + kern_size);
818 if (start < avoid_start &&
819 (start + bootmap_size) > avoid_start) {
824 /* OK, it doesn't overlap anything, use it. */
825 #ifdef CONFIG_DEBUG_BOOTMEM
826 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
827 start >> PAGE_SHIFT, start);
829 return start >> PAGE_SHIFT;
833 prom_printf("Cannot find free area for bootmap, aborting.\n");
837 static unsigned long __init bootmem_init(unsigned long *pages_avail,
838 unsigned long phys_base)
840 unsigned long bootmap_size, end_pfn;
841 unsigned long end_of_phys_memory = 0UL;
842 unsigned long bootmap_pfn, bytes_avail, size;
845 #ifdef CONFIG_DEBUG_BOOTMEM
846 prom_printf("bootmem_init: Scan pavail, ");
850 for (i = 0; i < pavail_ents; i++) {
851 end_of_phys_memory = pavail[i].phys_addr +
853 bytes_avail += pavail[i].reg_size;
854 if (cmdline_memory_size) {
855 if (bytes_avail > cmdline_memory_size) {
856 unsigned long slack = bytes_avail - cmdline_memory_size;
858 bytes_avail -= slack;
859 end_of_phys_memory -= slack;
861 pavail[i].reg_size -= slack;
862 if ((long)pavail[i].reg_size <= 0L) {
863 pavail[i].phys_addr = 0xdeadbeefUL;
864 pavail[i].reg_size = 0UL;
867 pavail[i+1].reg_size = 0Ul;
868 pavail[i+1].phys_addr = 0xdeadbeefUL;
876 *pages_avail = bytes_avail >> PAGE_SHIFT;
878 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
880 #ifdef CONFIG_BLK_DEV_INITRD
881 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
882 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
883 unsigned long ramdisk_image = sparc_ramdisk_image ?
884 sparc_ramdisk_image : sparc_ramdisk_image64;
885 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
886 ramdisk_image -= KERNBASE;
887 initrd_start = ramdisk_image + phys_base;
888 initrd_end = initrd_start + sparc_ramdisk_size;
889 if (initrd_end > end_of_phys_memory) {
890 printk(KERN_CRIT "initrd extends beyond end of memory "
891 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
892 initrd_end, end_of_phys_memory);
898 /* Initialize the boot-time allocator. */
899 max_pfn = max_low_pfn = end_pfn;
900 min_low_pfn = (phys_base >> PAGE_SHIFT);
902 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
904 #ifdef CONFIG_DEBUG_BOOTMEM
905 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
906 min_low_pfn, bootmap_pfn, max_low_pfn);
908 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
909 min_low_pfn, end_pfn);
911 /* Now register the available physical memory with the
914 for (i = 0; i < pavail_ents; i++) {
915 #ifdef CONFIG_DEBUG_BOOTMEM
916 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
917 i, pavail[i].phys_addr, pavail[i].reg_size);
919 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
922 #ifdef CONFIG_BLK_DEV_INITRD
924 size = initrd_end - initrd_start;
926 /* Resert the initrd image area. */
927 #ifdef CONFIG_DEBUG_BOOTMEM
928 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
929 initrd_start, initrd_end);
931 reserve_bootmem(initrd_start, size);
932 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
934 initrd_start += PAGE_OFFSET;
935 initrd_end += PAGE_OFFSET;
938 /* Reserve the kernel text/data/bss. */
939 #ifdef CONFIG_DEBUG_BOOTMEM
940 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
942 reserve_bootmem(kern_base, kern_size);
943 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
945 /* Reserve the bootmem map. We do not account for it
946 * in pages_avail because we will release that memory
947 * in free_all_bootmem.
950 #ifdef CONFIG_DEBUG_BOOTMEM
951 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
952 (bootmap_pfn << PAGE_SHIFT), size);
954 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
955 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
957 for (i = 0; i < pavail_ents; i++) {
958 unsigned long start_pfn, end_pfn;
960 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
961 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
962 #ifdef CONFIG_DEBUG_BOOTMEM
963 prom_printf("memory_present(0, %lx, %lx)\n",
966 memory_present(0, start_pfn, end_pfn);
974 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
975 static int pall_ents __initdata;
977 #ifdef CONFIG_DEBUG_PAGEALLOC
978 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
980 unsigned long vstart = PAGE_OFFSET + pstart;
981 unsigned long vend = PAGE_OFFSET + pend;
982 unsigned long alloc_bytes = 0UL;
984 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
985 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
990 while (vstart < vend) {
991 unsigned long this_end, paddr = __pa(vstart);
992 pgd_t *pgd = pgd_offset_k(vstart);
997 pud = pud_offset(pgd, vstart);
998 if (pud_none(*pud)) {
1001 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1002 alloc_bytes += PAGE_SIZE;
1003 pud_populate(&init_mm, pud, new);
1006 pmd = pmd_offset(pud, vstart);
1007 if (!pmd_present(*pmd)) {
1010 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1011 alloc_bytes += PAGE_SIZE;
1012 pmd_populate_kernel(&init_mm, pmd, new);
1015 pte = pte_offset_kernel(pmd, vstart);
1016 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1017 if (this_end > vend)
1020 while (vstart < this_end) {
1021 pte_val(*pte) = (paddr | pgprot_val(prot));
1023 vstart += PAGE_SIZE;
1032 extern unsigned int kvmap_linear_patch[1];
1033 #endif /* CONFIG_DEBUG_PAGEALLOC */
1035 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1037 const unsigned long shift_256MB = 28;
1038 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1039 const unsigned long size_256MB = (1UL << shift_256MB);
1041 while (start < end) {
1044 remains = end - start;
1045 if (remains < size_256MB)
1048 if (start & mask_256MB) {
1049 start = (start + size_256MB) & ~mask_256MB;
1053 while (remains >= size_256MB) {
1054 unsigned long index = start >> shift_256MB;
1056 __set_bit(index, kpte_linear_bitmap);
1058 start += size_256MB;
1059 remains -= size_256MB;
1064 static void __init kernel_physical_mapping_init(void)
1067 #ifdef CONFIG_DEBUG_PAGEALLOC
1068 unsigned long mem_alloced = 0UL;
1071 read_obp_memory("reg", &pall[0], &pall_ents);
1073 for (i = 0; i < pall_ents; i++) {
1074 unsigned long phys_start, phys_end;
1076 phys_start = pall[i].phys_addr;
1077 phys_end = phys_start + pall[i].reg_size;
1079 mark_kpte_bitmap(phys_start, phys_end);
1081 #ifdef CONFIG_DEBUG_PAGEALLOC
1082 mem_alloced += kernel_map_range(phys_start, phys_end,
1087 #ifdef CONFIG_DEBUG_PAGEALLOC
1088 printk("Allocated %ld bytes for kernel page tables.\n",
1091 kvmap_linear_patch[0] = 0x01000000; /* nop */
1092 flushi(&kvmap_linear_patch[0]);
1098 #ifdef CONFIG_DEBUG_PAGEALLOC
1099 void kernel_map_pages(struct page *page, int numpages, int enable)
1101 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1102 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1104 kernel_map_range(phys_start, phys_end,
1105 (enable ? PAGE_KERNEL : __pgprot(0)));
1107 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1108 PAGE_OFFSET + phys_end);
1110 /* we should perform an IPI and flush all tlbs,
1111 * but that can deadlock->flush only current cpu.
1113 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1114 PAGE_OFFSET + phys_end);
1118 unsigned long __init find_ecache_flush_span(unsigned long size)
1122 for (i = 0; i < pavail_ents; i++) {
1123 if (pavail[i].reg_size >= size)
1124 return pavail[i].phys_addr;
1130 static void __init tsb_phys_patch(void)
1132 struct tsb_ldquad_phys_patch_entry *pquad;
1133 struct tsb_phys_patch_entry *p;
1135 pquad = &__tsb_ldquad_phys_patch;
1136 while (pquad < &__tsb_ldquad_phys_patch_end) {
1137 unsigned long addr = pquad->addr;
1139 if (tlb_type == hypervisor)
1140 *(unsigned int *) addr = pquad->sun4v_insn;
1142 *(unsigned int *) addr = pquad->sun4u_insn;
1144 __asm__ __volatile__("flush %0"
1151 p = &__tsb_phys_patch;
1152 while (p < &__tsb_phys_patch_end) {
1153 unsigned long addr = p->addr;
1155 *(unsigned int *) addr = p->insn;
1157 __asm__ __volatile__("flush %0"
1165 /* Don't mark as init, we give this to the Hypervisor. */
1166 static struct hv_tsb_descr ktsb_descr[2];
1167 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1169 static void __init sun4v_ktsb_init(void)
1171 unsigned long ktsb_pa;
1173 /* First KTSB for PAGE_SIZE mappings. */
1174 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1176 switch (PAGE_SIZE) {
1179 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1180 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1184 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1185 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1189 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1190 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1193 case 4 * 1024 * 1024:
1194 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1195 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1199 ktsb_descr[0].assoc = 1;
1200 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1201 ktsb_descr[0].ctx_idx = 0;
1202 ktsb_descr[0].tsb_base = ktsb_pa;
1203 ktsb_descr[0].resv = 0;
1205 /* Second KTSB for 4MB/256MB mappings. */
1206 ktsb_pa = (kern_base +
1207 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1209 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1210 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1211 HV_PGSZ_MASK_256MB);
1212 ktsb_descr[1].assoc = 1;
1213 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1214 ktsb_descr[1].ctx_idx = 0;
1215 ktsb_descr[1].tsb_base = ktsb_pa;
1216 ktsb_descr[1].resv = 0;
1219 void __cpuinit sun4v_ktsb_register(void)
1221 register unsigned long func asm("%o5");
1222 register unsigned long arg0 asm("%o0");
1223 register unsigned long arg1 asm("%o1");
1226 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1228 func = HV_FAST_MMU_TSB_CTX0;
1231 __asm__ __volatile__("ta %6"
1232 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1233 : "0" (func), "1" (arg0), "2" (arg1),
1234 "i" (HV_FAST_TRAP));
1237 /* paging_init() sets up the page tables */
1239 extern void cheetah_ecache_flush_init(void);
1240 extern void sun4v_patch_tlb_handlers(void);
1242 static unsigned long last_valid_pfn;
1243 pgd_t swapper_pg_dir[2048];
1245 static void sun4u_pgprot_init(void);
1246 static void sun4v_pgprot_init(void);
1248 void __init paging_init(void)
1250 unsigned long end_pfn, pages_avail, shift, phys_base;
1251 unsigned long real_end, i;
1253 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1254 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1256 /* Invalidate both kernel TSBs. */
1257 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1258 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1260 if (tlb_type == hypervisor)
1261 sun4v_pgprot_init();
1263 sun4u_pgprot_init();
1265 if (tlb_type == cheetah_plus ||
1266 tlb_type == hypervisor)
1269 if (tlb_type == hypervisor) {
1270 sun4v_patch_tlb_handlers();
1274 /* Find available physical memory... */
1275 read_obp_memory("available", &pavail[0], &pavail_ents);
1277 phys_base = 0xffffffffffffffffUL;
1278 for (i = 0; i < pavail_ents; i++)
1279 phys_base = min(phys_base, pavail[i].phys_addr);
1281 set_bit(0, mmu_context_bmap);
1283 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1285 real_end = (unsigned long)_end;
1286 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1288 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1289 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1293 /* Set kernel pgd to upper alias so physical page computations
1296 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1298 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1300 /* Now can init the kernel/bad page tables. */
1301 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1302 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1304 inherit_prom_mappings();
1306 /* Ok, we can use our TLB miss and window trap handlers safely. */
1311 if (tlb_type == hypervisor)
1312 sun4v_ktsb_register();
1314 /* Setup bootmem... */
1316 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1318 max_mapnr = last_valid_pfn;
1320 kernel_physical_mapping_init();
1323 unsigned long zones_size[MAX_NR_ZONES];
1324 unsigned long zholes_size[MAX_NR_ZONES];
1327 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1328 zones_size[znum] = zholes_size[znum] = 0;
1330 zones_size[ZONE_DMA] = end_pfn;
1331 zholes_size[ZONE_DMA] = end_pfn - pages_avail;
1333 free_area_init_node(0, &contig_page_data, zones_size,
1334 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1341 static void __init taint_real_pages(void)
1345 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1347 /* Find changes discovered in the physmem available rescan and
1348 * reserve the lost portions in the bootmem maps.
1350 for (i = 0; i < pavail_ents; i++) {
1351 unsigned long old_start, old_end;
1353 old_start = pavail[i].phys_addr;
1354 old_end = old_start +
1356 while (old_start < old_end) {
1359 for (n = 0; pavail_rescan_ents; n++) {
1360 unsigned long new_start, new_end;
1362 new_start = pavail_rescan[n].phys_addr;
1363 new_end = new_start +
1364 pavail_rescan[n].reg_size;
1366 if (new_start <= old_start &&
1367 new_end >= (old_start + PAGE_SIZE)) {
1368 set_bit(old_start >> 22,
1369 sparc64_valid_addr_bitmap);
1373 reserve_bootmem(old_start, PAGE_SIZE);
1376 old_start += PAGE_SIZE;
1381 void __init mem_init(void)
1383 unsigned long codepages, datapages, initpages;
1384 unsigned long addr, last;
1387 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1389 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1390 if (sparc64_valid_addr_bitmap == NULL) {
1391 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1394 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1396 addr = PAGE_OFFSET + kern_base;
1397 last = PAGE_ALIGN(kern_size) + addr;
1398 while (addr < last) {
1399 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1405 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1407 #ifdef CONFIG_DEBUG_BOOTMEM
1408 prom_printf("mem_init: Calling free_all_bootmem().\n");
1410 totalram_pages = num_physpages = free_all_bootmem() - 1;
1413 * Set up the zero page, mark it reserved, so that page count
1414 * is not manipulated when freeing the page from user ptes.
1416 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1417 if (mem_map_zero == NULL) {
1418 prom_printf("paging_init: Cannot alloc zero page.\n");
1421 SetPageReserved(mem_map_zero);
1423 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1424 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1425 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1426 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1427 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1428 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1430 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1431 nr_free_pages() << (PAGE_SHIFT-10),
1432 codepages << (PAGE_SHIFT-10),
1433 datapages << (PAGE_SHIFT-10),
1434 initpages << (PAGE_SHIFT-10),
1435 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1437 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1438 cheetah_ecache_flush_init();
1441 void free_initmem(void)
1443 unsigned long addr, initend;
1446 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1448 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1449 initend = (unsigned long)(__init_end) & PAGE_MASK;
1450 for (; addr < initend; addr += PAGE_SIZE) {
1455 ((unsigned long) __va(kern_base)) -
1456 ((unsigned long) KERNBASE));
1457 memset((void *)addr, 0xcc, PAGE_SIZE);
1458 p = virt_to_page(page);
1460 ClearPageReserved(p);
1461 set_page_count(p, 1);
1468 #ifdef CONFIG_BLK_DEV_INITRD
1469 void free_initrd_mem(unsigned long start, unsigned long end)
1472 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1473 for (; start < end; start += PAGE_SIZE) {
1474 struct page *p = virt_to_page(start);
1476 ClearPageReserved(p);
1477 set_page_count(p, 1);
1485 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1486 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1487 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1488 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1489 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1490 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1492 pgprot_t PAGE_KERNEL __read_mostly;
1493 EXPORT_SYMBOL(PAGE_KERNEL);
1495 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1496 pgprot_t PAGE_COPY __read_mostly;
1498 pgprot_t PAGE_SHARED __read_mostly;
1499 EXPORT_SYMBOL(PAGE_SHARED);
1501 pgprot_t PAGE_EXEC __read_mostly;
1502 unsigned long pg_iobits __read_mostly;
1504 unsigned long _PAGE_IE __read_mostly;
1506 unsigned long _PAGE_E __read_mostly;
1507 EXPORT_SYMBOL(_PAGE_E);
1509 unsigned long _PAGE_CACHE __read_mostly;
1510 EXPORT_SYMBOL(_PAGE_CACHE);
1512 static void prot_init_common(unsigned long page_none,
1513 unsigned long page_shared,
1514 unsigned long page_copy,
1515 unsigned long page_readonly,
1516 unsigned long page_exec_bit)
1518 PAGE_COPY = __pgprot(page_copy);
1519 PAGE_SHARED = __pgprot(page_shared);
1521 protection_map[0x0] = __pgprot(page_none);
1522 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1523 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1524 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1525 protection_map[0x4] = __pgprot(page_readonly);
1526 protection_map[0x5] = __pgprot(page_readonly);
1527 protection_map[0x6] = __pgprot(page_copy);
1528 protection_map[0x7] = __pgprot(page_copy);
1529 protection_map[0x8] = __pgprot(page_none);
1530 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1531 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1532 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1533 protection_map[0xc] = __pgprot(page_readonly);
1534 protection_map[0xd] = __pgprot(page_readonly);
1535 protection_map[0xe] = __pgprot(page_shared);
1536 protection_map[0xf] = __pgprot(page_shared);
1539 static void __init sun4u_pgprot_init(void)
1541 unsigned long page_none, page_shared, page_copy, page_readonly;
1542 unsigned long page_exec_bit;
1544 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1545 _PAGE_CACHE_4U | _PAGE_P_4U |
1546 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1548 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1549 _PAGE_CACHE_4U | _PAGE_P_4U |
1550 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1551 _PAGE_EXEC_4U | _PAGE_L_4U);
1552 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1554 _PAGE_IE = _PAGE_IE_4U;
1555 _PAGE_E = _PAGE_E_4U;
1556 _PAGE_CACHE = _PAGE_CACHE_4U;
1558 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1559 __ACCESS_BITS_4U | _PAGE_E_4U);
1561 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1563 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1564 _PAGE_P_4U | _PAGE_W_4U);
1566 /* XXX Should use 256MB on Panther. XXX */
1567 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1569 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1570 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1571 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1572 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1575 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1576 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1577 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1578 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1579 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1580 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1581 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1583 page_exec_bit = _PAGE_EXEC_4U;
1585 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1589 static void __init sun4v_pgprot_init(void)
1591 unsigned long page_none, page_shared, page_copy, page_readonly;
1592 unsigned long page_exec_bit;
1594 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1595 _PAGE_CACHE_4V | _PAGE_P_4V |
1596 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1598 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1599 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1601 _PAGE_IE = _PAGE_IE_4V;
1602 _PAGE_E = _PAGE_E_4V;
1603 _PAGE_CACHE = _PAGE_CACHE_4V;
1605 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1607 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1608 _PAGE_P_4V | _PAGE_W_4V);
1610 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1612 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1613 _PAGE_P_4V | _PAGE_W_4V);
1615 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1616 __ACCESS_BITS_4V | _PAGE_E_4V);
1618 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1619 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1620 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1621 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1622 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1624 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1625 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1626 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1627 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1628 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1629 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1630 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1632 page_exec_bit = _PAGE_EXEC_4V;
1634 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1638 unsigned long pte_sz_bits(unsigned long sz)
1640 if (tlb_type == hypervisor) {
1644 return _PAGE_SZ8K_4V;
1646 return _PAGE_SZ64K_4V;
1648 return _PAGE_SZ512K_4V;
1649 case 4 * 1024 * 1024:
1650 return _PAGE_SZ4MB_4V;
1656 return _PAGE_SZ8K_4U;
1658 return _PAGE_SZ64K_4U;
1660 return _PAGE_SZ512K_4U;
1661 case 4 * 1024 * 1024:
1662 return _PAGE_SZ4MB_4U;
1667 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1671 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1672 pte_val(pte) |= (((unsigned long)space) << 32);
1673 pte_val(pte) |= pte_sz_bits(page_size);
1678 static unsigned long kern_large_tte(unsigned long paddr)
1682 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1683 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1684 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1685 if (tlb_type == hypervisor)
1686 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1687 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1688 _PAGE_EXEC_4V | _PAGE_W_4V);
1694 * Translate PROM's mapping we capture at boot time into physical address.
1695 * The second parameter is only set from prom_callback() invocations.
1697 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1702 mask = _PAGE_PADDR_4U;
1703 if (tlb_type == hypervisor)
1704 mask = _PAGE_PADDR_4V;
1706 for (i = 0; i < prom_trans_ents; i++) {
1707 struct linux_prom_translation *p = &prom_trans[i];
1709 if (promva >= p->virt &&
1710 promva < (p->virt + p->size)) {
1711 unsigned long base = p->data & mask;
1715 return base + (promva & (8192 - 1));
1723 /* XXX We should kill off this ugly thing at so me point. XXX */
1724 unsigned long sun4u_get_pte(unsigned long addr)
1730 unsigned long mask = _PAGE_PADDR_4U;
1732 if (tlb_type == hypervisor)
1733 mask = _PAGE_PADDR_4V;
1735 if (addr >= PAGE_OFFSET)
1738 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1739 return prom_virt_to_phys(addr, NULL);
1741 pgdp = pgd_offset_k(addr);
1742 pudp = pud_offset(pgdp, addr);
1743 pmdp = pmd_offset(pudp, addr);
1744 ptep = pte_offset_kernel(pmdp, addr);
1746 return pte_val(*ptep) & mask;
1749 /* If not locked, zap it. */
1750 void __flush_tlb_all(void)
1752 unsigned long pstate;
1755 __asm__ __volatile__("flushw\n\t"
1756 "rdpr %%pstate, %0\n\t"
1757 "wrpr %0, %1, %%pstate"
1760 if (tlb_type == spitfire) {
1761 for (i = 0; i < 64; i++) {
1762 /* Spitfire Errata #32 workaround */
1763 /* NOTE: Always runs on spitfire, so no
1764 * cheetah+ page size encodings.
1766 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1770 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1772 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1773 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1776 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1777 spitfire_put_dtlb_data(i, 0x0UL);
1780 /* Spitfire Errata #32 workaround */
1781 /* NOTE: Always runs on spitfire, so no
1782 * cheetah+ page size encodings.
1784 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1788 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1790 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1791 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1794 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1795 spitfire_put_itlb_data(i, 0x0UL);
1798 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1799 cheetah_flush_dtlb_all();
1800 cheetah_flush_itlb_all();
1802 __asm__ __volatile__("wrpr %0, 0, %%pstate"