arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/system.h>
  28 #include <asm/page.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/oplib.h>
  32 #include <asm/iommu.h>
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/dma.h>
  38 #include <asm/starfire.h>
  39 #include <asm/tlb.h>
  40 #include <asm/spitfire.h>
  41 #include <asm/sections.h>
  42
  43 extern void device_scan(void);
  44
  45 #define MAX_BANKS       32
  46
  47 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  48 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  49 static int pavail_ents __initdata;
  50 static int pavail_rescan_ents __initdata;
  51
  52 static int cmp_p64(const void *a, const void *b)
  53 {
  54         const struct linux_prom64_registers *x = a, *y = b;
  55
  56         if (x->phys_addr > y->phys_addr)
  57                 return 1;
  58         if (x->phys_addr < y->phys_addr)
  59                 return -1;
  60         return 0;
  61 }
  62
  63 static void __init read_obp_memory(const char *property,
  64                                    struct linux_prom64_registers *regs,
  65                                    int *num_ents)
  66 {
  67         int node = prom_finddevice("/memory");
  68         int prop_size = prom_getproplen(node, property);
  69         int ents, ret, i;
  70
  71         ents = prop_size / sizeof(struct linux_prom64_registers);
  72         if (ents > MAX_BANKS) {
  73                 prom_printf("The machine has more %s property entries than "
  74                             "this kernel can support (%d).\n",
  75                             property, MAX_BANKS);
  76                 prom_halt();
  77         }
  78
  79         ret = prom_getproperty(node, property, (char *) regs, prop_size);
  80         if (ret == -1) {
  81                 prom_printf("Couldn't get %s property from /memory.\n");
  82                 prom_halt();
  83         }
  84
  85         *num_ents = ents;
  86
  87         /* Sanitize what we got from the firmware, by page aligning
  88          * everything.
  89          */
  90         for (i = 0; i < ents; i++) {
  91                 unsigned long base, size;
  92
  93                 base = regs[i].phys_addr;
  94                 size = regs[i].reg_size;
  95
  96                 size &= PAGE_MASK;
  97                 if (base & ~PAGE_MASK) {
  98                         unsigned long new_base = PAGE_ALIGN(base);
  99
 100                         size -= new_base - base;
 101                         if ((long) size < 0L)
 102                                 size = 0UL;
 103                         base = new_base;
 104                 }
 105                 regs[i].phys_addr = base;
 106                 regs[i].reg_size = size;
 107         }
 108         sort(regs, ents, sizeof(struct linux_prom64_registers),
 109              cmp_p64, NULL);
 110 }
 111
 112 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 113
 114 /* Ugly, but necessary... -DaveM */
 115 unsigned long phys_base __read_mostly;
 116 unsigned long kern_base __read_mostly;
 117 unsigned long kern_size __read_mostly;
 118 unsigned long pfn_base __read_mostly;
 119
 120 /* get_new_mmu_context() uses "cache + 1".  */
 121 DEFINE_SPINLOCK(ctx_alloc_lock);
 122 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 123 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 124 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 125
 126 /* References to special section boundaries */
 127 extern char  _start[], _end[];
 128
 129 /* Initial ramdisk setup */
 130 extern unsigned long sparc_ramdisk_image64;
 131 extern unsigned int sparc_ramdisk_image;
 132 extern unsigned int sparc_ramdisk_size;
 133
 134 struct page *mem_map_zero __read_mostly;
 135
 136 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 137
 138 unsigned long sparc64_kern_pri_context __read_mostly;
 139 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 140 unsigned long sparc64_kern_sec_context __read_mostly;
 141
 142 int bigkernel = 0;
 143
 144 /* XXX Tune this... */
 145 #define PGT_CACHE_LOW   25
 146 #define PGT_CACHE_HIGH  50
 147
 148 void check_pgt_cache(void)
 149 {
 150         preempt_disable();
 151         if (pgtable_cache_size > PGT_CACHE_HIGH) {
 152                 do {
 153                         if (pgd_quicklist)
 154                                 free_pgd_slow(get_pgd_fast());
 155                         if (pte_quicklist[0])
 156                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
 157                         if (pte_quicklist[1])
 158                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
 159                 } while (pgtable_cache_size > PGT_CACHE_LOW);
 160         }
 161         preempt_enable();
 162 }
 163
 164 #ifdef CONFIG_DEBUG_DCFLUSH
 165 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 166 #ifdef CONFIG_SMP
 167 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 168 #endif
 169 #endif
 170
 171 __inline__ void flush_dcache_page_impl(struct page *page)
 172 {
 173 #ifdef CONFIG_DEBUG_DCFLUSH
 174         atomic_inc(&dcpage_flushes);
 175 #endif
 176
 177 #ifdef DCACHE_ALIASING_POSSIBLE
 178         __flush_dcache_page(page_address(page),
 179                             ((tlb_type == spitfire) &&
 180                              page_mapping(page) != NULL));
 181 #else
 182         if (page_mapping(page) != NULL &&
 183             tlb_type == spitfire)
 184                 __flush_icache_page(__pa(page_address(page)));
 185 #endif
 186 }
 187
 188 #define PG_dcache_dirty         PG_arch_1
 189 #define PG_dcache_cpu_shift     24
 190 #define PG_dcache_cpu_mask      (256 - 1)
 191
 192 #if NR_CPUS > 256
 193 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 194 #endif
 195
 196 #define dcache_dirty_cpu(page) \
 197         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 198
 199 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 200 {
 201         unsigned long mask = this_cpu;
 202         unsigned long non_cpu_bits;
 203
 204         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 205         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 206
 207         __asm__ __volatile__("1:\n\t"
 208                              "ldx       [%2], %%g7\n\t"
 209                              "and       %%g7, %1, %%g1\n\t"
 210                              "or        %%g1, %0, %%g1\n\t"
 211                              "casx      [%2], %%g7, %%g1\n\t"
 212                              "cmp       %%g7, %%g1\n\t"
 213                              "membar    #StoreLoad | #StoreStore\n\t"
 214                              "bne,pn    %%xcc, 1b\n\t"
 215                              " nop"
 216                              : /* no outputs */
 217                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 218                              : "g1", "g7");
 219 }
 220
 221 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 222 {
 223         unsigned long mask = (1UL << PG_dcache_dirty);
 224
 225         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 226                              "1:\n\t"
 227                              "ldx       [%2], %%g7\n\t"
 228                              "srlx      %%g7, %4, %%g1\n\t"
 229                              "and       %%g1, %3, %%g1\n\t"
 230                              "cmp       %%g1, %0\n\t"
 231                              "bne,pn    %%icc, 2f\n\t"
 232                              " andn     %%g7, %1, %%g1\n\t"
 233                              "casx      [%2], %%g7, %%g1\n\t"
 234                              "cmp       %%g7, %%g1\n\t"
 235                              "membar    #StoreLoad | #StoreStore\n\t"
 236                              "bne,pn    %%xcc, 1b\n\t"
 237                              " nop\n"
 238                              "2:"
 239                              : /* no outputs */
 240                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 241                                "i" (PG_dcache_cpu_mask),
 242                                "i" (PG_dcache_cpu_shift)
 243                              : "g1", "g7");
 244 }
 245
 246 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 247 {
 248         struct page *page;
 249         unsigned long pfn;
 250         unsigned long pg_flags;
 251
 252         pfn = pte_pfn(pte);
 253         if (pfn_valid(pfn) &&
 254             (page = pfn_to_page(pfn), page_mapping(page)) &&
 255             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 256                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 257                            PG_dcache_cpu_mask);
 258                 int this_cpu = get_cpu();
 259
 260                 /* This is just to optimize away some function calls
 261                  * in the SMP case.
 262                  */
 263                 if (cpu == this_cpu)
 264                         flush_dcache_page_impl(page);
 265                 else
 266                         smp_flush_dcache_page_impl(page, cpu);
 267
 268                 clear_dcache_dirty_cpu(page, cpu);
 269
 270                 put_cpu();
 271         }
 272 }
 273
 274 void flush_dcache_page(struct page *page)
 275 {
 276         struct address_space *mapping;
 277         int this_cpu;
 278
 279         /* Do not bother with the expensive D-cache flush if it
 280          * is merely the zero page.  The 'bigcore' testcase in GDB
 281          * causes this case to run millions of times.
 282          */
 283         if (page == ZERO_PAGE(0))
 284                 return;
 285
 286         this_cpu = get_cpu();
 287
 288         mapping = page_mapping(page);
 289         if (mapping && !mapping_mapped(mapping)) {
 290                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 291                 if (dirty) {
 292                         int dirty_cpu = dcache_dirty_cpu(page);
 293
 294                         if (dirty_cpu == this_cpu)
 295                                 goto out;
 296                         smp_flush_dcache_page_impl(page, dirty_cpu);
 297                 }
 298                 set_dcache_dirty(page, this_cpu);
 299         } else {
 300                 /* We could delay the flush for the !page_mapping
 301                  * case too.  But that case is for exec env/arg
 302                  * pages and those are %99 certainly going to get
 303                  * faulted into the tlb (and thus flushed) anyways.
 304                  */
 305                 flush_dcache_page_impl(page);
 306         }
 307
 308 out:
 309         put_cpu();
 310 }
 311
 312 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 313 {
 314         /* Cheetah has coherent I-cache. */
 315         if (tlb_type == spitfire) {
 316                 unsigned long kaddr;
 317
 318                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 319                         __flush_icache_page(__get_phys(kaddr));
 320         }
 321 }
 322
 323 unsigned long page_to_pfn(struct page *page)
 324 {
 325         return (unsigned long) ((page - mem_map) + pfn_base);
 326 }
 327
 328 struct page *pfn_to_page(unsigned long pfn)
 329 {
 330         return (mem_map + (pfn - pfn_base));
 331 }
 332
 333 void show_mem(void)
 334 {
 335         printk("Mem-info:\n");
 336         show_free_areas();
 337         printk("Free swap:       %6ldkB\n",
 338                nr_swap_pages << (PAGE_SHIFT-10));
 339         printk("%ld pages of RAM\n", num_physpages);
 340         printk("%d free pages\n", nr_free_pages());
 341         printk("%d pages in page table cache\n",pgtable_cache_size);
 342 }
 343
 344 void mmu_info(struct seq_file *m)
 345 {
 346         if (tlb_type == cheetah)
 347                 seq_printf(m, "MMU Type\t: Cheetah\n");
 348         else if (tlb_type == cheetah_plus)
 349                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 350         else if (tlb_type == spitfire)
 351                 seq_printf(m, "MMU Type\t: Spitfire\n");
 352         else
 353                 seq_printf(m, "MMU Type\t: ???\n");
 354
 355 #ifdef CONFIG_DEBUG_DCFLUSH
 356         seq_printf(m, "DCPageFlushes\t: %d\n",
 357                    atomic_read(&dcpage_flushes));
 358 #ifdef CONFIG_SMP
 359         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 360                    atomic_read(&dcpage_flushes_xcall));
 361 #endif /* CONFIG_SMP */
 362 #endif /* CONFIG_DEBUG_DCFLUSH */
 363 }
 364
 365 struct linux_prom_translation {
 366         unsigned long virt;
 367         unsigned long size;
 368         unsigned long data;
 369 };
 370
 371 /* Exported for kernel TLB miss handling in ktlb.S */
 372 struct linux_prom_translation prom_trans[512] __read_mostly;
 373 unsigned int prom_trans_ents __read_mostly;
 374 unsigned int swapper_pgd_zero __read_mostly;
 375
 376 extern unsigned long prom_boot_page;
 377 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 378 extern int prom_get_mmu_ihandle(void);
 379 extern void register_prom_callbacks(void);
 380
 381 /* Exported for SMP bootup purposes. */
 382 unsigned long kern_locked_tte_data;
 383
 384 /*
 385  * Translate PROM's mapping we capture at boot time into physical address.
 386  * The second parameter is only set from prom_callback() invocations.
 387  */
 388 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 389 {
 390         int i;
 391
 392         for (i = 0; i < prom_trans_ents; i++) {
 393                 struct linux_prom_translation *p = &prom_trans[i];
 394
 395                 if (promva >= p->virt &&
 396                     promva < (p->virt + p->size)) {
 397                         unsigned long base = p->data & _PAGE_PADDR;
 398
 399                         if (error)
 400                                 *error = 0;
 401                         return base + (promva & (8192 - 1));
 402                 }
 403         }
 404         if (error)
 405                 *error = 1;
 406         return 0UL;
 407 }
 408
 409 /* The obp translations are saved based on 8k pagesize, since obp can
 410  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 411  * HI_OBP_ADDRESS range are handled in ktlb.S.
 412  */
 413 static inline int in_obp_range(unsigned long vaddr)
 414 {
 415         return (vaddr >= LOW_OBP_ADDRESS &&
 416                 vaddr < HI_OBP_ADDRESS);
 417 }
 418
 419 static int cmp_ptrans(const void *a, const void *b)
 420 {
 421         const struct linux_prom_translation *x = a, *y = b;
 422
 423         if (x->virt > y->virt)
 424                 return 1;
 425         if (x->virt < y->virt)
 426                 return -1;
 427         return 0;
 428 }
 429
 430 /* Read OBP translations property into 'prom_trans[]'.  */
 431 static void __init read_obp_translations(void)
 432 {
 433         int n, node, ents, first, last, i;
 434
 435         node = prom_finddevice("/virtual-memory");
 436         n = prom_getproplen(node, "translations");
 437         if (unlikely(n == 0 || n == -1)) {
 438                 prom_printf("prom_mappings: Couldn't get size.\n");
 439                 prom_halt();
 440         }
 441         if (unlikely(n > sizeof(prom_trans))) {
 442                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 443                 prom_halt();
 444         }
 445
 446         if ((n = prom_getproperty(node, "translations",
 447                                   (char *)&prom_trans[0],
 448                                   sizeof(prom_trans))) == -1) {
 449                 prom_printf("prom_mappings: Couldn't get property.\n");
 450                 prom_halt();
 451         }
 452
 453         n = n / sizeof(struct linux_prom_translation);
 454
 455         ents = n;
 456
 457         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 458              cmp_ptrans, NULL);
 459
 460         /* Now kick out all the non-OBP entries.  */
 461         for (i = 0; i < ents; i++) {
 462                 if (in_obp_range(prom_trans[i].virt))
 463                         break;
 464         }
 465         first = i;
 466         for (; i < ents; i++) {
 467                 if (!in_obp_range(prom_trans[i].virt))
 468                         break;
 469         }
 470         last = i;
 471
 472         for (i = 0; i < (last - first); i++) {
 473                 struct linux_prom_translation *src = &prom_trans[i + first];
 474                 struct linux_prom_translation *dest = &prom_trans[i];
 475
 476                 *dest = *src;
 477         }
 478         for (; i < ents; i++) {
 479                 struct linux_prom_translation *dest = &prom_trans[i];
 480                 dest->virt = dest->size = dest->data = 0x0UL;
 481         }
 482
 483         prom_trans_ents = last - first;
 484
 485         if (tlb_type == spitfire) {
 486                 /* Clear diag TTE bits. */
 487                 for (i = 0; i < prom_trans_ents; i++)
 488                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 489         }
 490 }
 491
 492 static void __init remap_kernel(void)
 493 {
 494         unsigned long phys_page, tte_vaddr, tte_data;
 495         int tlb_ent = sparc64_highest_locked_tlbent();
 496
 497         tte_vaddr = (unsigned long) KERNBASE;
 498         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 499         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
 500                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
 501                                  _PAGE_L | _PAGE_W));
 502
 503         kern_locked_tte_data = tte_data;
 504
 505         /* Now lock us into the TLBs via OBP. */
 506         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 507         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 508         if (bigkernel) {
 509                 tlb_ent -= 1;
 510                 prom_dtlb_load(tlb_ent,
 511                                tte_data + 0x400000,
 512                                tte_vaddr + 0x400000);
 513                 prom_itlb_load(tlb_ent,
 514                                tte_data + 0x400000,
 515                                tte_vaddr + 0x400000);
 516         }
 517         sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 518         if (tlb_type == cheetah_plus) {
 519                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 520                                             CTX_CHEETAH_PLUS_NUC);
 521                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 522                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 523         }
 524 }
 525
 526
 527 static void __init inherit_prom_mappings(void)
 528 {
 529         read_obp_translations();
 530
 531         /* Now fixup OBP's idea about where we really are mapped. */
 532         prom_printf("Remapping the kernel... ");
 533         remap_kernel();
 534         prom_printf("done.\n");
 535
 536         prom_printf("Registering callbacks... ");
 537         register_prom_callbacks();
 538         prom_printf("done.\n");
 539 }
 540
 541 static int prom_ditlb_set;
 542 struct prom_tlb_entry {
 543         int             tlb_ent;
 544         unsigned long   tlb_tag;
 545         unsigned long   tlb_data;
 546 };
 547 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 548
 549 void prom_world(int enter)
 550 {
 551         unsigned long pstate;
 552         int i;
 553
 554         if (!enter)
 555                 set_fs((mm_segment_t) { get_thread_current_ds() });
 556
 557         if (!prom_ditlb_set)
 558                 return;
 559
 560         /* Make sure the following runs atomically. */
 561         __asm__ __volatile__("flushw\n\t"
 562                              "rdpr      %%pstate, %0\n\t"
 563                              "wrpr      %0, %1, %%pstate"
 564                              : "=r" (pstate)
 565                              : "i" (PSTATE_IE));
 566
 567         if (enter) {
 568                 /* Install PROM world. */
 569                 for (i = 0; i < 16; i++) {
 570                         if (prom_dtlb[i].tlb_ent != -1) {
 571                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 572                                                      "membar #Sync"
 573                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 574                                         "i" (ASI_DMMU));
 575                                 if (tlb_type == spitfire)
 576                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 577                                                                prom_dtlb[i].tlb_data);
 578                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 579                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 580                                                                prom_dtlb[i].tlb_data);
 581                         }
 582                         if (prom_itlb[i].tlb_ent != -1) {
 583                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 584                                                      "membar #Sync"
 585                                                      : : "r" (prom_itlb[i].tlb_tag),
 586                                                      "r" (TLB_TAG_ACCESS),
 587                                                      "i" (ASI_IMMU));
 588                                 if (tlb_type == spitfire)
 589                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 590                                                                prom_itlb[i].tlb_data);
 591                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 592                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 593                                                                prom_itlb[i].tlb_data);
 594                         }
 595                 }
 596         } else {
 597                 for (i = 0; i < 16; i++) {
 598                         if (prom_dtlb[i].tlb_ent != -1) {
 599                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 600                                                      "membar #Sync"
 601                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 602                                 if (tlb_type == spitfire)
 603                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 604                                 else
 605                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 606                         }
 607                         if (prom_itlb[i].tlb_ent != -1) {
 608                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 609                                                      "membar #Sync"
 610                                                      : : "r" (TLB_TAG_ACCESS),
 611                                                      "i" (ASI_IMMU));
 612                                 if (tlb_type == spitfire)
 613                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 614                                 else
 615                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 616                         }
 617                 }
 618         }
 619         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 620                              : : "r" (pstate));
 621 }
 622
 623 void inherit_locked_prom_mappings(int save_p)
 624 {
 625         int i;
 626         int dtlb_seen = 0;
 627         int itlb_seen = 0;
 628
 629         /* Fucking losing PROM has more mappings in the TLB, but
 630          * it (conveniently) fails to mention any of these in the
 631          * translations property.  The only ones that matter are
 632          * the locked PROM tlb entries, so we impose the following
 633          * irrecovable rule on the PROM, it is allowed 8 locked
 634          * entries in the ITLB and 8 in the DTLB.
 635          *
 636          * Supposedly the upper 16GB of the address space is
 637          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 638          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 639          * used between the client program and the firmware on sun5
 640          * systems to coordinate mmu mappings is also COMPLETELY
 641          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 642          */
 643         if (save_p) {
 644                 for (i = 0; i < 16; i++) {
 645                         prom_itlb[i].tlb_ent = -1;
 646                         prom_dtlb[i].tlb_ent = -1;
 647                 }
 648         }
 649         if (tlb_type == spitfire) {
 650                 int high = sparc64_highest_unlocked_tlb_ent;
 651                 for (i = 0; i <= high; i++) {
 652                         unsigned long data;
 653
 654                         /* Spitfire Errata #32 workaround */
 655                         /* NOTE: Always runs on spitfire, so no cheetah+
 656                          *       page size encodings.
 657                          */
 658                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 659                                              "flush     %%g6"
 660                                              : /* No outputs */
 661                                              : "r" (0),
 662                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 663
 664                         data = spitfire_get_dtlb_data(i);
 665                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 666                                 unsigned long tag;
 667
 668                                 /* Spitfire Errata #32 workaround */
 669                                 /* NOTE: Always runs on spitfire, so no
 670                                  *       cheetah+ page size encodings.
 671                                  */
 672                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 673                                                      "flush     %%g6"
 674                                                      : /* No outputs */
 675                                                      : "r" (0),
 676                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 677
 678                                 tag = spitfire_get_dtlb_tag(i);
 679                                 if (save_p) {
 680                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 681                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 682                                         prom_dtlb[dtlb_seen].tlb_data = data;
 683                                 }
 684                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 685                                                      "membar #Sync"
 686                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 687                                 spitfire_put_dtlb_data(i, 0x0UL);
 688
 689                                 dtlb_seen++;
 690                                 if (dtlb_seen > 15)
 691                                         break;
 692                         }
 693                 }
 694
 695                 for (i = 0; i < high; i++) {
 696                         unsigned long data;
 697
 698                         /* Spitfire Errata #32 workaround */
 699                         /* NOTE: Always runs on spitfire, so no
 700                          *       cheetah+ page size encodings.
 701                          */
 702                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 703                                              "flush     %%g6"
 704                                              : /* No outputs */
 705                                              : "r" (0),
 706                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 707
 708                         data = spitfire_get_itlb_data(i);
 709                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 710                                 unsigned long tag;
 711
 712                                 /* Spitfire Errata #32 workaround */
 713                                 /* NOTE: Always runs on spitfire, so no
 714                                  *       cheetah+ page size encodings.
 715                                  */
 716                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 717                                                      "flush     %%g6"
 718                                                      : /* No outputs */
 719                                                      : "r" (0),
 720                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 721
 722                                 tag = spitfire_get_itlb_tag(i);
 723                                 if (save_p) {
 724                                         prom_itlb[itlb_seen].tlb_ent = i;
 725                                         prom_itlb[itlb_seen].tlb_tag = tag;
 726                                         prom_itlb[itlb_seen].tlb_data = data;
 727                                 }
 728                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 729                                                      "membar #Sync"
 730                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 731                                 spitfire_put_itlb_data(i, 0x0UL);
 732
 733                                 itlb_seen++;
 734                                 if (itlb_seen > 15)
 735                                         break;
 736                         }
 737                 }
 738         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 739                 int high = sparc64_highest_unlocked_tlb_ent;
 740
 741                 for (i = 0; i <= high; i++) {
 742                         unsigned long data;
 743
 744                         data = cheetah_get_ldtlb_data(i);
 745                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 746                                 unsigned long tag;
 747
 748                                 tag = cheetah_get_ldtlb_tag(i);
 749                                 if (save_p) {
 750                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 751                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 752                                         prom_dtlb[dtlb_seen].tlb_data = data;
 753                                 }
 754                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 755                                                      "membar #Sync"
 756                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 757                                 cheetah_put_ldtlb_data(i, 0x0UL);
 758
 759                                 dtlb_seen++;
 760                                 if (dtlb_seen > 15)
 761                                         break;
 762                         }
 763                 }
 764
 765                 for (i = 0; i < high; i++) {
 766                         unsigned long data;
 767
 768                         data = cheetah_get_litlb_data(i);
 769                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 770                                 unsigned long tag;
 771
 772                                 tag = cheetah_get_litlb_tag(i);
 773                                 if (save_p) {
 774                                         prom_itlb[itlb_seen].tlb_ent = i;
 775                                         prom_itlb[itlb_seen].tlb_tag = tag;
 776                                         prom_itlb[itlb_seen].tlb_data = data;
 777                                 }
 778                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 779                                                      "membar #Sync"
 780                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 781                                 cheetah_put_litlb_data(i, 0x0UL);
 782
 783                                 itlb_seen++;
 784                                 if (itlb_seen > 15)
 785                                         break;
 786                         }
 787                 }
 788         } else {
 789                 /* Implement me :-) */
 790                 BUG();
 791         }
 792         if (save_p)
 793                 prom_ditlb_set = 1;
 794 }
 795
 796 /* Give PROM back his world, done during reboots... */
 797 void prom_reload_locked(void)
 798 {
 799         int i;
 800
 801         for (i = 0; i < 16; i++) {
 802                 if (prom_dtlb[i].tlb_ent != -1) {
 803                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 804                                              "membar #Sync"
 805                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 806                                 "i" (ASI_DMMU));
 807                         if (tlb_type == spitfire)
 808                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 809                                                        prom_dtlb[i].tlb_data);
 810                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 811                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 812                                                       prom_dtlb[i].tlb_data);
 813                 }
 814
 815                 if (prom_itlb[i].tlb_ent != -1) {
 816                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 817                                              "membar #Sync"
 818                                              : : "r" (prom_itlb[i].tlb_tag),
 819                                              "r" (TLB_TAG_ACCESS),
 820                                              "i" (ASI_IMMU));
 821                         if (tlb_type == spitfire)
 822                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 823                                                        prom_itlb[i].tlb_data);
 824                         else
 825                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 826                                                        prom_itlb[i].tlb_data);
 827                 }
 828         }
 829 }
 830
 831 #ifdef DCACHE_ALIASING_POSSIBLE
 832 void __flush_dcache_range(unsigned long start, unsigned long end)
 833 {
 834         unsigned long va;
 835
 836         if (tlb_type == spitfire) {
 837                 int n = 0;
 838
 839                 for (va = start; va < end; va += 32) {
 840                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 841                         if (++n >= 512)
 842                                 break;
 843                 }
 844         } else {
 845                 start = __pa(start);
 846                 end = __pa(end);
 847                 for (va = start; va < end; va += 32)
 848                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 849                                              "membar #Sync"
 850                                              : /* no outputs */
 851                                              : "r" (va),
 852                                                "i" (ASI_DCACHE_INVALIDATE));
 853         }
 854 }
 855 #endif /* DCACHE_ALIASING_POSSIBLE */
 856
 857 /* If not locked, zap it. */
 858 void __flush_tlb_all(void)
 859 {
 860         unsigned long pstate;
 861         int i;
 862
 863         __asm__ __volatile__("flushw\n\t"
 864                              "rdpr      %%pstate, %0\n\t"
 865                              "wrpr      %0, %1, %%pstate"
 866                              : "=r" (pstate)
 867                              : "i" (PSTATE_IE));
 868         if (tlb_type == spitfire) {
 869                 for (i = 0; i < 64; i++) {
 870                         /* Spitfire Errata #32 workaround */
 871                         /* NOTE: Always runs on spitfire, so no
 872                          *       cheetah+ page size encodings.
 873                          */
 874                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 875                                              "flush     %%g6"
 876                                              : /* No outputs */
 877                                              : "r" (0),
 878                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 879
 880                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
 881                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 882                                                      "membar #Sync"
 883                                                      : /* no outputs */
 884                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 885                                 spitfire_put_dtlb_data(i, 0x0UL);
 886                         }
 887
 888                         /* Spitfire Errata #32 workaround */
 889                         /* NOTE: Always runs on spitfire, so no
 890                          *       cheetah+ page size encodings.
 891                          */
 892                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 893                                              "flush     %%g6"
 894                                              : /* No outputs */
 895                                              : "r" (0),
 896                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 897
 898                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
 899                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 900                                                      "membar #Sync"
 901                                                      : /* no outputs */
 902                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 903                                 spitfire_put_itlb_data(i, 0x0UL);
 904                         }
 905                 }
 906         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 907                 cheetah_flush_dtlb_all();
 908                 cheetah_flush_itlb_all();
 909         }
 910         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 911                              : : "r" (pstate));
 912 }
 913
 914 /* Caller does TLB context flushing on local CPU if necessary.
 915  * The caller also ensures that CTX_VALID(mm->context) is false.
 916  *
 917  * We must be careful about boundary cases so that we never
 918  * let the user have CTX 0 (nucleus) or we ever use a CTX
 919  * version of zero (and thus NO_CONTEXT would not be caught
 920  * by version mis-match tests in mmu_context.h).
 921  */
 922 void get_new_mmu_context(struct mm_struct *mm)
 923 {
 924         unsigned long ctx, new_ctx;
 925         unsigned long orig_pgsz_bits;
 926
 927
 928         spin_lock(&ctx_alloc_lock);
 929         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 930         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 931         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 932         if (new_ctx >= (1 << CTX_NR_BITS)) {
 933                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 934                 if (new_ctx >= ctx) {
 935                         int i;
 936                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 937                                 CTX_FIRST_VERSION;
 938                         if (new_ctx == 1)
 939                                 new_ctx = CTX_FIRST_VERSION;
 940
 941                         /* Don't call memset, for 16 entries that's just
 942                          * plain silly...
 943                          */
 944                         mmu_context_bmap[0] = 3;
 945                         mmu_context_bmap[1] = 0;
 946                         mmu_context_bmap[2] = 0;
 947                         mmu_context_bmap[3] = 0;
 948                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 949                                 mmu_context_bmap[i + 0] = 0;
 950                                 mmu_context_bmap[i + 1] = 0;
 951                                 mmu_context_bmap[i + 2] = 0;
 952                                 mmu_context_bmap[i + 3] = 0;
 953                         }
 954                         goto out;
 955                 }
 956         }
 957         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 958         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 959 out:
 960         tlb_context_cache = new_ctx;
 961         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 962         spin_unlock(&ctx_alloc_lock);
 963 }
 964
 965 #ifndef CONFIG_SMP
 966 struct pgtable_cache_struct pgt_quicklists;
 967 #endif
 968
 969 /* XXX We don't need to color these things in the D-cache any longer.  */
 970 #ifdef DCACHE_ALIASING_POSSIBLE
 971 #define DC_ALIAS_SHIFT  1
 972 #else
 973 #define DC_ALIAS_SHIFT  0
 974 #endif
 975 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 976 {
 977         struct page *page;
 978         unsigned long color;
 979
 980         {
 981                 pte_t *ptep = pte_alloc_one_fast(mm, address);
 982
 983                 if (ptep)
 984                         return ptep;
 985         }
 986
 987         color = VPTE_COLOR(address);
 988         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
 989         if (page) {
 990                 unsigned long *to_free;
 991                 unsigned long paddr;
 992                 pte_t *pte;
 993
 994 #ifdef DCACHE_ALIASING_POSSIBLE
 995                 set_page_count(page, 1);
 996                 ClearPageCompound(page);
 997
 998                 set_page_count((page + 1), 1);
 999                 ClearPageCompound(page + 1);
1000 #endif
1001                 paddr = (unsigned long) page_address(page);
1002                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1003
1004                 if (!color) {
1005                         pte = (pte_t *) paddr;
1006                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1007                 } else {
1008                         pte = (pte_t *) (paddr + PAGE_SIZE);
1009                         to_free = (unsigned long *) paddr;
1010                 }
1011
1012 #ifdef DCACHE_ALIASING_POSSIBLE
1013                 /* Now free the other one up, adjust cache size. */
1014                 preempt_disable();
1015                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1016                 pte_quicklist[color ^ 0x1] = to_free;
1017                 pgtable_cache_size++;
1018                 preempt_enable();
1019 #endif
1020
1021                 return pte;
1022         }
1023         return NULL;
1024 }
1025
1026 void sparc_ultra_dump_itlb(void)
1027 {
1028         int slot;
1029
1030         if (tlb_type == spitfire) {
1031                 printk ("Contents of itlb: ");
1032                 for (slot = 0; slot < 14; slot++) printk ("    ");
1033                 printk ("%2x:%016lx,%016lx\n",
1034                         0,
1035                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1036                 for (slot = 1; slot < 64; slot+=3) {
1037                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1038                                 slot,
1039                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1040                                 slot+1,
1041                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1042                                 slot+2,
1043                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1044                 }
1045         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1046                 printk ("Contents of itlb0:\n");
1047                 for (slot = 0; slot < 16; slot+=2) {
1048                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1049                                 slot,
1050                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1051                                 slot+1,
1052                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1053                 }
1054                 printk ("Contents of itlb2:\n");
1055                 for (slot = 0; slot < 128; slot+=2) {
1056                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1057                                 slot,
1058                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1059                                 slot+1,
1060                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1061                 }
1062         }
1063 }
1064
1065 void sparc_ultra_dump_dtlb(void)
1066 {
1067         int slot;
1068
1069         if (tlb_type == spitfire) {
1070                 printk ("Contents of dtlb: ");
1071                 for (slot = 0; slot < 14; slot++) printk ("    ");
1072                 printk ("%2x:%016lx,%016lx\n", 0,
1073                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1074                 for (slot = 1; slot < 64; slot+=3) {
1075                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1076                                 slot,
1077                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1078                                 slot+1,
1079                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1080                                 slot+2,
1081                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1082                 }
1083         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1084                 printk ("Contents of dtlb0:\n");
1085                 for (slot = 0; slot < 16; slot+=2) {
1086                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1087                                 slot,
1088                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1089                                 slot+1,
1090                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1091                 }
1092                 printk ("Contents of dtlb2:\n");
1093                 for (slot = 0; slot < 512; slot+=2) {
1094                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1095                                 slot,
1096                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1097                                 slot+1,
1098                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1099                 }
1100                 if (tlb_type == cheetah_plus) {
1101                         printk ("Contents of dtlb3:\n");
1102                         for (slot = 0; slot < 512; slot+=2) {
1103                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1104                                         slot,
1105                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1106                                         slot+1,
1107                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1108                         }
1109                 }
1110         }
1111 }
1112
1113 extern unsigned long cmdline_memory_size;
1114
1115 unsigned long __init bootmem_init(unsigned long *pages_avail)
1116 {
1117         unsigned long bootmap_size, start_pfn, end_pfn;
1118         unsigned long end_of_phys_memory = 0UL;
1119         unsigned long bootmap_pfn, bytes_avail, size;
1120         int i;
1121
1122 #ifdef CONFIG_DEBUG_BOOTMEM
1123         prom_printf("bootmem_init: Scan pavail, ");
1124 #endif
1125
1126         bytes_avail = 0UL;
1127         for (i = 0; i < pavail_ents; i++) {
1128                 end_of_phys_memory = pavail[i].phys_addr +
1129                         pavail[i].reg_size;
1130                 bytes_avail += pavail[i].reg_size;
1131                 if (cmdline_memory_size) {
1132                         if (bytes_avail > cmdline_memory_size) {
1133                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1134
1135                                 bytes_avail -= slack;
1136                                 end_of_phys_memory -= slack;
1137
1138                                 pavail[i].reg_size -= slack;
1139                                 if ((long)pavail[i].reg_size <= 0L) {
1140                                         pavail[i].phys_addr = 0xdeadbeefUL;
1141                                         pavail[i].reg_size = 0UL;
1142                                         pavail_ents = i;
1143                                 } else {
1144                                         pavail[i+1].reg_size = 0Ul;
1145                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
1146                                         pavail_ents = i + 1;
1147                                 }
1148                                 break;
1149                         }
1150                 }
1151         }
1152
1153         *pages_avail = bytes_avail >> PAGE_SHIFT;
1154
1155         /* Start with page aligned address of last symbol in kernel
1156          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1157          * 4MB locked TLB translation.
1158          */
1159         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1160
1161         bootmap_pfn = start_pfn;
1162
1163         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1164
1165 #ifdef CONFIG_BLK_DEV_INITRD
1166         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1167         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1168                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1169                         sparc_ramdisk_image : sparc_ramdisk_image64;
1170                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1171                         ramdisk_image -= KERNBASE;
1172                 initrd_start = ramdisk_image + phys_base;
1173                 initrd_end = initrd_start + sparc_ramdisk_size;
1174                 if (initrd_end > end_of_phys_memory) {
1175                         printk(KERN_CRIT "initrd extends beyond end of memory "
1176                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1177                                initrd_end, end_of_phys_memory);
1178                         initrd_start = 0;
1179                 }
1180                 if (initrd_start) {
1181                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1182                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1183                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1184                 }
1185         }
1186 #endif
1187         /* Initialize the boot-time allocator. */
1188         max_pfn = max_low_pfn = end_pfn;
1189         min_low_pfn = pfn_base;
1190
1191 #ifdef CONFIG_DEBUG_BOOTMEM
1192         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1193                     min_low_pfn, bootmap_pfn, max_low_pfn);
1194 #endif
1195         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1196
1197         /* Now register the available physical memory with the
1198          * allocator.
1199          */
1200         for (i = 0; i < pavail_ents; i++) {
1201 #ifdef CONFIG_DEBUG_BOOTMEM
1202                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1203                             i, pavail[i].phys_addr, pavail[i].reg_size);
1204 #endif
1205                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1206         }
1207
1208 #ifdef CONFIG_BLK_DEV_INITRD
1209         if (initrd_start) {
1210                 size = initrd_end - initrd_start;
1211
1212                 /* Resert the initrd image area. */
1213 #ifdef CONFIG_DEBUG_BOOTMEM
1214                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1215                         initrd_start, initrd_end);
1216 #endif
1217                 reserve_bootmem(initrd_start, size);
1218                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1219
1220                 initrd_start += PAGE_OFFSET;
1221                 initrd_end += PAGE_OFFSET;
1222         }
1223 #endif
1224         /* Reserve the kernel text/data/bss. */
1225 #ifdef CONFIG_DEBUG_BOOTMEM
1226         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1227 #endif
1228         reserve_bootmem(kern_base, kern_size);
1229         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1230
1231         /* Reserve the bootmem map.   We do not account for it
1232          * in pages_avail because we will release that memory
1233          * in free_all_bootmem.
1234          */
1235         size = bootmap_size;
1236 #ifdef CONFIG_DEBUG_BOOTMEM
1237         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1238                     (bootmap_pfn << PAGE_SHIFT), size);
1239 #endif
1240         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1241         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1242
1243         return end_pfn;
1244 }
1245
1246 #ifdef CONFIG_DEBUG_PAGEALLOC
1247 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1248 {
1249         unsigned long vstart = PAGE_OFFSET + pstart;
1250         unsigned long vend = PAGE_OFFSET + pend;
1251         unsigned long alloc_bytes = 0UL;
1252
1253         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1254                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1255                             vstart, vend);
1256                 prom_halt();
1257         }
1258
1259         while (vstart < vend) {
1260                 unsigned long this_end, paddr = __pa(vstart);
1261                 pgd_t *pgd = pgd_offset_k(vstart);
1262                 pud_t *pud;
1263                 pmd_t *pmd;
1264                 pte_t *pte;
1265
1266                 pud = pud_offset(pgd, vstart);
1267                 if (pud_none(*pud)) {
1268                         pmd_t *new;
1269
1270                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1271                         alloc_bytes += PAGE_SIZE;
1272                         pud_populate(&init_mm, pud, new);
1273                 }
1274
1275                 pmd = pmd_offset(pud, vstart);
1276                 if (!pmd_present(*pmd)) {
1277                         pte_t *new;
1278
1279                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1280                         alloc_bytes += PAGE_SIZE;
1281                         pmd_populate_kernel(&init_mm, pmd, new);
1282                 }
1283
1284                 pte = pte_offset_kernel(pmd, vstart);
1285                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1286                 if (this_end > vend)
1287                         this_end = vend;
1288
1289                 while (vstart < this_end) {
1290                         pte_val(*pte) = (paddr | pgprot_val(prot));
1291
1292                         vstart += PAGE_SIZE;
1293                         paddr += PAGE_SIZE;
1294                         pte++;
1295                 }
1296         }
1297
1298         return alloc_bytes;
1299 }
1300
1301 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1302 static int pall_ents __initdata;
1303
1304 extern unsigned int kvmap_linear_patch[1];
1305
1306 static void __init kernel_physical_mapping_init(void)
1307 {
1308         unsigned long i, mem_alloced = 0UL;
1309
1310         read_obp_memory("reg", &pall[0], &pall_ents);
1311
1312         for (i = 0; i < pall_ents; i++) {
1313                 unsigned long phys_start, phys_end;
1314
1315                 phys_start = pall[i].phys_addr;
1316                 phys_end = phys_start + pall[i].reg_size;
1317                 mem_alloced += kernel_map_range(phys_start, phys_end,
1318                                                 PAGE_KERNEL);
1319         }
1320
1321         printk("Allocated %ld bytes for kernel page tables.\n",
1322                mem_alloced);
1323
1324         kvmap_linear_patch[0] = 0x01000000; /* nop */
1325         flushi(&kvmap_linear_patch[0]);
1326
1327         __flush_tlb_all();
1328 }
1329
1330 void kernel_map_pages(struct page *page, int numpages, int enable)
1331 {
1332         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1333         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1334
1335         kernel_map_range(phys_start, phys_end,
1336                          (enable ? PAGE_KERNEL : __pgprot(0)));
1337
1338         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1339                                PAGE_OFFSET + phys_end);
1340
1341         /* we should perform an IPI and flush all tlbs,
1342          * but that can deadlock->flush only current cpu.
1343          */
1344         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1345                                  PAGE_OFFSET + phys_end);
1346 }
1347 #endif
1348
1349 unsigned long __init find_ecache_flush_span(unsigned long size)
1350 {
1351         int i;
1352
1353         for (i = 0; i < pavail_ents; i++) {
1354                 if (pavail[i].reg_size >= size)
1355                         return pavail[i].phys_addr;
1356         }
1357
1358         return ~0UL;
1359 }
1360
1361 /* paging_init() sets up the page tables */
1362
1363 extern void cheetah_ecache_flush_init(void);
1364
1365 static unsigned long last_valid_pfn;
1366 pgd_t swapper_pg_dir[2048];
1367
1368 void __init paging_init(void)
1369 {
1370         unsigned long end_pfn, pages_avail, shift;
1371         unsigned long real_end, i;
1372
1373         /* Find available physical memory... */
1374         read_obp_memory("available", &pavail[0], &pavail_ents);
1375
1376         phys_base = 0xffffffffffffffffUL;
1377         for (i = 0; i < pavail_ents; i++)
1378                 phys_base = min(phys_base, pavail[i].phys_addr);
1379
1380         pfn_base = phys_base >> PAGE_SHIFT;
1381
1382         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1383         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1384
1385         set_bit(0, mmu_context_bmap);
1386
1387         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1388
1389         real_end = (unsigned long)_end;
1390         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1391                 bigkernel = 1;
1392         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1393                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1394                 prom_halt();
1395         }
1396
1397         /* Set kernel pgd to upper alias so physical page computations
1398          * work.
1399          */
1400         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1401
1402         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1403
1404         /* Now can init the kernel/bad page tables. */
1405         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1406                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1407
1408         swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1409
1410         inherit_prom_mappings();
1411
1412         /* Ok, we can use our TLB miss and window trap handlers safely.
1413          * We need to do a quick peek here to see if we are on StarFire
1414          * or not, so setup_tba can setup the IRQ globals correctly (it
1415          * needs to get the hard smp processor id correctly).
1416          */
1417         {
1418                 extern void setup_tba(int);
1419                 setup_tba(this_is_starfire);
1420         }
1421
1422         inherit_locked_prom_mappings(1);
1423
1424         __flush_tlb_all();
1425
1426         /* Setup bootmem... */
1427         pages_avail = 0;
1428         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1429
1430 #ifdef CONFIG_DEBUG_PAGEALLOC
1431         kernel_physical_mapping_init();
1432 #endif
1433
1434         {
1435                 unsigned long zones_size[MAX_NR_ZONES];
1436                 unsigned long zholes_size[MAX_NR_ZONES];
1437                 unsigned long npages;
1438                 int znum;
1439
1440                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1441                         zones_size[znum] = zholes_size[znum] = 0;
1442
1443                 npages = end_pfn - pfn_base;
1444                 zones_size[ZONE_DMA] = npages;
1445                 zholes_size[ZONE_DMA] = npages - pages_avail;
1446
1447                 free_area_init_node(0, &contig_page_data, zones_size,
1448                                     phys_base >> PAGE_SHIFT, zholes_size);
1449         }
1450
1451         device_scan();
1452 }
1453
1454 static void __init taint_real_pages(void)
1455 {
1456         int i;
1457
1458         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1459
1460         /* Find changes discovered in the physmem available rescan and
1461          * reserve the lost portions in the bootmem maps.
1462          */
1463         for (i = 0; i < pavail_ents; i++) {
1464                 unsigned long old_start, old_end;
1465
1466                 old_start = pavail[i].phys_addr;
1467                 old_end = old_start +
1468                         pavail[i].reg_size;
1469                 while (old_start < old_end) {
1470                         int n;
1471
1472                         for (n = 0; pavail_rescan_ents; n++) {
1473                                 unsigned long new_start, new_end;
1474
1475                                 new_start = pavail_rescan[n].phys_addr;
1476                                 new_end = new_start +
1477                                         pavail_rescan[n].reg_size;
1478
1479                                 if (new_start <= old_start &&
1480                                     new_end >= (old_start + PAGE_SIZE)) {
1481                                         set_bit(old_start >> 22,
1482                                                 sparc64_valid_addr_bitmap);
1483                                         goto do_next_page;
1484                                 }
1485                         }
1486                         reserve_bootmem(old_start, PAGE_SIZE);
1487
1488                 do_next_page:
1489                         old_start += PAGE_SIZE;
1490                 }
1491         }
1492 }
1493
1494 void __init mem_init(void)
1495 {
1496         unsigned long codepages, datapages, initpages;
1497         unsigned long addr, last;
1498         int i;
1499
1500         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1501         i += 1;
1502         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1503         if (sparc64_valid_addr_bitmap == NULL) {
1504                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1505                 prom_halt();
1506         }
1507         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1508
1509         addr = PAGE_OFFSET + kern_base;
1510         last = PAGE_ALIGN(kern_size) + addr;
1511         while (addr < last) {
1512                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1513                 addr += PAGE_SIZE;
1514         }
1515
1516         taint_real_pages();
1517
1518         max_mapnr = last_valid_pfn - pfn_base;
1519         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1520
1521 #ifdef CONFIG_DEBUG_BOOTMEM
1522         prom_printf("mem_init: Calling free_all_bootmem().\n");
1523 #endif
1524         totalram_pages = num_physpages = free_all_bootmem() - 1;
1525
1526         /*
1527          * Set up the zero page, mark it reserved, so that page count
1528          * is not manipulated when freeing the page from user ptes.
1529          */
1530         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1531         if (mem_map_zero == NULL) {
1532                 prom_printf("paging_init: Cannot alloc zero page.\n");
1533                 prom_halt();
1534         }
1535         SetPageReserved(mem_map_zero);
1536
1537         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1538         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1539         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1540         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1541         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1542         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1543
1544         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1545                nr_free_pages() << (PAGE_SHIFT-10),
1546                codepages << (PAGE_SHIFT-10),
1547                datapages << (PAGE_SHIFT-10),
1548                initpages << (PAGE_SHIFT-10),
1549                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1550
1551         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1552                 cheetah_ecache_flush_init();
1553 }
1554
1555 void free_initmem(void)
1556 {
1557         unsigned long addr, initend;
1558
1559         /*
1560          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1561          */
1562         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1563         initend = (unsigned long)(__init_end) & PAGE_MASK;
1564         for (; addr < initend; addr += PAGE_SIZE) {
1565                 unsigned long page;
1566                 struct page *p;
1567
1568                 page = (addr +
1569                         ((unsigned long) __va(kern_base)) -
1570                         ((unsigned long) KERNBASE));
1571                 memset((void *)addr, 0xcc, PAGE_SIZE);
1572                 p = virt_to_page(page);
1573
1574                 ClearPageReserved(p);
1575                 set_page_count(p, 1);
1576                 __free_page(p);
1577                 num_physpages++;
1578                 totalram_pages++;
1579         }
1580 }
1581
1582 #ifdef CONFIG_BLK_DEV_INITRD
1583 void free_initrd_mem(unsigned long start, unsigned long end)
1584 {
1585         if (start < end)
1586                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1587         for (; start < end; start += PAGE_SIZE) {
1588                 struct page *p = virt_to_page(start);
1589
1590                 ClearPageReserved(p);
1591                 set_page_count(p, 1);
1592                 __free_page(p);
1593                 num_physpages++;
1594                 totalram_pages++;
1595         }
1596 }
1597 #endif