arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/system.h>
  28 #include <asm/page.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/oplib.h>
  32 #include <asm/iommu.h>
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/dma.h>
  38 #include <asm/starfire.h>
  39 #include <asm/tlb.h>
  40 #include <asm/spitfire.h>
  41 #include <asm/sections.h>
  42 #include <asm/tsb.h>
  43
  44 extern void device_scan(void);
  45
  46 #define MAX_BANKS       32
  47
  48 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  49 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  50 static int pavail_ents __initdata;
  51 static int pavail_rescan_ents __initdata;
  52
  53 static int cmp_p64(const void *a, const void *b)
  54 {
  55         const struct linux_prom64_registers *x = a, *y = b;
  56
  57         if (x->phys_addr > y->phys_addr)
  58                 return 1;
  59         if (x->phys_addr < y->phys_addr)
  60                 return -1;
  61         return 0;
  62 }
  63
  64 static void __init read_obp_memory(const char *property,
  65                                    struct linux_prom64_registers *regs,
  66                                    int *num_ents)
  67 {
  68         int node = prom_finddevice("/memory");
  69         int prop_size = prom_getproplen(node, property);
  70         int ents, ret, i;
  71
  72         ents = prop_size / sizeof(struct linux_prom64_registers);
  73         if (ents > MAX_BANKS) {
  74                 prom_printf("The machine has more %s property entries than "
  75                             "this kernel can support (%d).\n",
  76                             property, MAX_BANKS);
  77                 prom_halt();
  78         }
  79
  80         ret = prom_getproperty(node, property, (char *) regs, prop_size);
  81         if (ret == -1) {
  82                 prom_printf("Couldn't get %s property from /memory.\n");
  83                 prom_halt();
  84         }
  85
  86         *num_ents = ents;
  87
  88         /* Sanitize what we got from the firmware, by page aligning
  89          * everything.
  90          */
  91         for (i = 0; i < ents; i++) {
  92                 unsigned long base, size;
  93
  94                 base = regs[i].phys_addr;
  95                 size = regs[i].reg_size;
  96
  97                 size &= PAGE_MASK;
  98                 if (base & ~PAGE_MASK) {
  99                         unsigned long new_base = PAGE_ALIGN(base);
 100
 101                         size -= new_base - base;
 102                         if ((long) size < 0L)
 103                                 size = 0UL;
 104                         base = new_base;
 105                 }
 106                 regs[i].phys_addr = base;
 107                 regs[i].reg_size = size;
 108         }
 109         sort(regs, ents, sizeof(struct linux_prom64_registers),
 110              cmp_p64, NULL);
 111 }
 112
 113 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 114
 115 /* Ugly, but necessary... -DaveM */
 116 unsigned long phys_base __read_mostly;
 117 unsigned long kern_base __read_mostly;
 118 unsigned long kern_size __read_mostly;
 119 unsigned long pfn_base __read_mostly;
 120
 121 /* get_new_mmu_context() uses "cache + 1".  */
 122 DEFINE_SPINLOCK(ctx_alloc_lock);
 123 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 124 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 125 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 126
 127 /* References to special section boundaries */
 128 extern char  _start[], _end[];
 129
 130 /* Initial ramdisk setup */
 131 extern unsigned long sparc_ramdisk_image64;
 132 extern unsigned int sparc_ramdisk_image;
 133 extern unsigned int sparc_ramdisk_size;
 134
 135 struct page *mem_map_zero __read_mostly;
 136
 137 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 138
 139 unsigned long sparc64_kern_pri_context __read_mostly;
 140 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 141 unsigned long sparc64_kern_sec_context __read_mostly;
 142
 143 int bigkernel = 0;
 144
 145 kmem_cache_t *pgtable_cache __read_mostly;
 146
 147 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
 148 {
 149         clear_page(addr);
 150 }
 151
 152 void pgtable_cache_init(void)
 153 {
 154         pgtable_cache = kmem_cache_create("pgtable_cache",
 155                                           PAGE_SIZE, PAGE_SIZE,
 156                                           SLAB_HWCACHE_ALIGN |
 157                                           SLAB_MUST_HWCACHE_ALIGN,
 158                                           zero_ctor,
 159                                           NULL);
 160         if (!pgtable_cache) {
 161                 prom_printf("pgtable_cache_init(): Could not create!\n");
 162                 prom_halt();
 163         }
 164 }
 165
 166 #ifdef CONFIG_DEBUG_DCFLUSH
 167 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 168 #ifdef CONFIG_SMP
 169 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 170 #endif
 171 #endif
 172
 173 __inline__ void flush_dcache_page_impl(struct page *page)
 174 {
 175 #ifdef CONFIG_DEBUG_DCFLUSH
 176         atomic_inc(&dcpage_flushes);
 177 #endif
 178
 179 #ifdef DCACHE_ALIASING_POSSIBLE
 180         __flush_dcache_page(page_address(page),
 181                             ((tlb_type == spitfire) &&
 182                              page_mapping(page) != NULL));
 183 #else
 184         if (page_mapping(page) != NULL &&
 185             tlb_type == spitfire)
 186                 __flush_icache_page(__pa(page_address(page)));
 187 #endif
 188 }
 189
 190 #define PG_dcache_dirty         PG_arch_1
 191 #define PG_dcache_cpu_shift     24
 192 #define PG_dcache_cpu_mask      (256 - 1)
 193
 194 #if NR_CPUS > 256
 195 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 196 #endif
 197
 198 #define dcache_dirty_cpu(page) \
 199         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 200
 201 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 202 {
 203         unsigned long mask = this_cpu;
 204         unsigned long non_cpu_bits;
 205
 206         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 207         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 208
 209         __asm__ __volatile__("1:\n\t"
 210                              "ldx       [%2], %%g7\n\t"
 211                              "and       %%g7, %1, %%g1\n\t"
 212                              "or        %%g1, %0, %%g1\n\t"
 213                              "casx      [%2], %%g7, %%g1\n\t"
 214                              "cmp       %%g7, %%g1\n\t"
 215                              "membar    #StoreLoad | #StoreStore\n\t"
 216                              "bne,pn    %%xcc, 1b\n\t"
 217                              " nop"
 218                              : /* no outputs */
 219                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 220                              : "g1", "g7");
 221 }
 222
 223 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 224 {
 225         unsigned long mask = (1UL << PG_dcache_dirty);
 226
 227         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 228                              "1:\n\t"
 229                              "ldx       [%2], %%g7\n\t"
 230                              "srlx      %%g7, %4, %%g1\n\t"
 231                              "and       %%g1, %3, %%g1\n\t"
 232                              "cmp       %%g1, %0\n\t"
 233                              "bne,pn    %%icc, 2f\n\t"
 234                              " andn     %%g7, %1, %%g1\n\t"
 235                              "casx      [%2], %%g7, %%g1\n\t"
 236                              "cmp       %%g7, %%g1\n\t"
 237                              "membar    #StoreLoad | #StoreStore\n\t"
 238                              "bne,pn    %%xcc, 1b\n\t"
 239                              " nop\n"
 240                              "2:"
 241                              : /* no outputs */
 242                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 243                                "i" (PG_dcache_cpu_mask),
 244                                "i" (PG_dcache_cpu_shift)
 245                              : "g1", "g7");
 246 }
 247
 248 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 249 {
 250         unsigned long tsb_addr = (unsigned long) ent;
 251
 252         if (tlb_type == cheetah_plus)
 253                 tsb_addr = __pa(tsb_addr);
 254
 255         __tsb_insert(tsb_addr, tag, pte);
 256 }
 257
 258 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 259 {
 260         struct mm_struct *mm;
 261         struct page *page;
 262         unsigned long pfn;
 263         unsigned long pg_flags;
 264
 265         pfn = pte_pfn(pte);
 266         if (pfn_valid(pfn) &&
 267             (page = pfn_to_page(pfn), page_mapping(page)) &&
 268             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 269                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 270                            PG_dcache_cpu_mask);
 271                 int this_cpu = get_cpu();
 272
 273                 /* This is just to optimize away some function calls
 274                  * in the SMP case.
 275                  */
 276                 if (cpu == this_cpu)
 277                         flush_dcache_page_impl(page);
 278                 else
 279                         smp_flush_dcache_page_impl(page, cpu);
 280
 281                 clear_dcache_dirty_cpu(page, cpu);
 282
 283                 put_cpu();
 284         }
 285
 286         mm = vma->vm_mm;
 287         if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
 288                 struct tsb *tsb;
 289                 unsigned long tag;
 290
 291                 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
 292                                        (mm->context.tsb_nentries - 1UL)];
 293                 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
 294                 tsb_insert(tsb, tag, pte_val(pte));
 295         }
 296 }
 297
 298 void flush_dcache_page(struct page *page)
 299 {
 300         struct address_space *mapping;
 301         int this_cpu;
 302
 303         /* Do not bother with the expensive D-cache flush if it
 304          * is merely the zero page.  The 'bigcore' testcase in GDB
 305          * causes this case to run millions of times.
 306          */
 307         if (page == ZERO_PAGE(0))
 308                 return;
 309
 310         this_cpu = get_cpu();
 311
 312         mapping = page_mapping(page);
 313         if (mapping && !mapping_mapped(mapping)) {
 314                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 315                 if (dirty) {
 316                         int dirty_cpu = dcache_dirty_cpu(page);
 317
 318                         if (dirty_cpu == this_cpu)
 319                                 goto out;
 320                         smp_flush_dcache_page_impl(page, dirty_cpu);
 321                 }
 322                 set_dcache_dirty(page, this_cpu);
 323         } else {
 324                 /* We could delay the flush for the !page_mapping
 325                  * case too.  But that case is for exec env/arg
 326                  * pages and those are %99 certainly going to get
 327                  * faulted into the tlb (and thus flushed) anyways.
 328                  */
 329                 flush_dcache_page_impl(page);
 330         }
 331
 332 out:
 333         put_cpu();
 334 }
 335
 336 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 337 {
 338         /* Cheetah has coherent I-cache. */
 339         if (tlb_type == spitfire) {
 340                 unsigned long kaddr;
 341
 342                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 343                         __flush_icache_page(__get_phys(kaddr));
 344         }
 345 }
 346
 347 unsigned long page_to_pfn(struct page *page)
 348 {
 349         return (unsigned long) ((page - mem_map) + pfn_base);
 350 }
 351
 352 struct page *pfn_to_page(unsigned long pfn)
 353 {
 354         return (mem_map + (pfn - pfn_base));
 355 }
 356
 357 void show_mem(void)
 358 {
 359         printk("Mem-info:\n");
 360         show_free_areas();
 361         printk("Free swap:       %6ldkB\n",
 362                nr_swap_pages << (PAGE_SHIFT-10));
 363         printk("%ld pages of RAM\n", num_physpages);
 364         printk("%d free pages\n", nr_free_pages());
 365 }
 366
 367 void mmu_info(struct seq_file *m)
 368 {
 369         if (tlb_type == cheetah)
 370                 seq_printf(m, "MMU Type\t: Cheetah\n");
 371         else if (tlb_type == cheetah_plus)
 372                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 373         else if (tlb_type == spitfire)
 374                 seq_printf(m, "MMU Type\t: Spitfire\n");
 375         else
 376                 seq_printf(m, "MMU Type\t: ???\n");
 377
 378 #ifdef CONFIG_DEBUG_DCFLUSH
 379         seq_printf(m, "DCPageFlushes\t: %d\n",
 380                    atomic_read(&dcpage_flushes));
 381 #ifdef CONFIG_SMP
 382         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 383                    atomic_read(&dcpage_flushes_xcall));
 384 #endif /* CONFIG_SMP */
 385 #endif /* CONFIG_DEBUG_DCFLUSH */
 386 }
 387
 388 struct linux_prom_translation {
 389         unsigned long virt;
 390         unsigned long size;
 391         unsigned long data;
 392 };
 393
 394 /* Exported for kernel TLB miss handling in ktlb.S */
 395 struct linux_prom_translation prom_trans[512] __read_mostly;
 396 unsigned int prom_trans_ents __read_mostly;
 397
 398 extern unsigned long prom_boot_page;
 399 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 400 extern int prom_get_mmu_ihandle(void);
 401 extern void register_prom_callbacks(void);
 402
 403 /* Exported for SMP bootup purposes. */
 404 unsigned long kern_locked_tte_data;
 405
 406 /*
 407  * Translate PROM's mapping we capture at boot time into physical address.
 408  * The second parameter is only set from prom_callback() invocations.
 409  */
 410 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 411 {
 412         int i;
 413
 414         for (i = 0; i < prom_trans_ents; i++) {
 415                 struct linux_prom_translation *p = &prom_trans[i];
 416
 417                 if (promva >= p->virt &&
 418                     promva < (p->virt + p->size)) {
 419                         unsigned long base = p->data & _PAGE_PADDR;
 420
 421                         if (error)
 422                                 *error = 0;
 423                         return base + (promva & (8192 - 1));
 424                 }
 425         }
 426         if (error)
 427                 *error = 1;
 428         return 0UL;
 429 }
 430
 431 /* The obp translations are saved based on 8k pagesize, since obp can
 432  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 433  * HI_OBP_ADDRESS range are handled in ktlb.S.
 434  */
 435 static inline int in_obp_range(unsigned long vaddr)
 436 {
 437         return (vaddr >= LOW_OBP_ADDRESS &&
 438                 vaddr < HI_OBP_ADDRESS);
 439 }
 440
 441 static int cmp_ptrans(const void *a, const void *b)
 442 {
 443         const struct linux_prom_translation *x = a, *y = b;
 444
 445         if (x->virt > y->virt)
 446                 return 1;
 447         if (x->virt < y->virt)
 448                 return -1;
 449         return 0;
 450 }
 451
 452 /* Read OBP translations property into 'prom_trans[]'.  */
 453 static void __init read_obp_translations(void)
 454 {
 455         int n, node, ents, first, last, i;
 456
 457         node = prom_finddevice("/virtual-memory");
 458         n = prom_getproplen(node, "translations");
 459         if (unlikely(n == 0 || n == -1)) {
 460                 prom_printf("prom_mappings: Couldn't get size.\n");
 461                 prom_halt();
 462         }
 463         if (unlikely(n > sizeof(prom_trans))) {
 464                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 465                 prom_halt();
 466         }
 467
 468         if ((n = prom_getproperty(node, "translations",
 469                                   (char *)&prom_trans[0],
 470                                   sizeof(prom_trans))) == -1) {
 471                 prom_printf("prom_mappings: Couldn't get property.\n");
 472                 prom_halt();
 473         }
 474
 475         n = n / sizeof(struct linux_prom_translation);
 476
 477         ents = n;
 478
 479         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 480              cmp_ptrans, NULL);
 481
 482         /* Now kick out all the non-OBP entries.  */
 483         for (i = 0; i < ents; i++) {
 484                 if (in_obp_range(prom_trans[i].virt))
 485                         break;
 486         }
 487         first = i;
 488         for (; i < ents; i++) {
 489                 if (!in_obp_range(prom_trans[i].virt))
 490                         break;
 491         }
 492         last = i;
 493
 494         for (i = 0; i < (last - first); i++) {
 495                 struct linux_prom_translation *src = &prom_trans[i + first];
 496                 struct linux_prom_translation *dest = &prom_trans[i];
 497
 498                 *dest = *src;
 499         }
 500         for (; i < ents; i++) {
 501                 struct linux_prom_translation *dest = &prom_trans[i];
 502                 dest->virt = dest->size = dest->data = 0x0UL;
 503         }
 504
 505         prom_trans_ents = last - first;
 506
 507         if (tlb_type == spitfire) {
 508                 /* Clear diag TTE bits. */
 509                 for (i = 0; i < prom_trans_ents; i++)
 510                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 511         }
 512 }
 513
 514 static void __init remap_kernel(void)
 515 {
 516         unsigned long phys_page, tte_vaddr, tte_data;
 517         int tlb_ent = sparc64_highest_locked_tlbent();
 518
 519         tte_vaddr = (unsigned long) KERNBASE;
 520         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 521         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
 522                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
 523                                  _PAGE_L | _PAGE_W));
 524
 525         kern_locked_tte_data = tte_data;
 526
 527         /* Now lock us into the TLBs via OBP. */
 528         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 529         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 530         if (bigkernel) {
 531                 tlb_ent -= 1;
 532                 prom_dtlb_load(tlb_ent,
 533                                tte_data + 0x400000,
 534                                tte_vaddr + 0x400000);
 535                 prom_itlb_load(tlb_ent,
 536                                tte_data + 0x400000,
 537                                tte_vaddr + 0x400000);
 538         }
 539         sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 540         if (tlb_type == cheetah_plus) {
 541                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 542                                             CTX_CHEETAH_PLUS_NUC);
 543                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 544                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 545         }
 546 }
 547
 548
 549 static void __init inherit_prom_mappings(void)
 550 {
 551         read_obp_translations();
 552
 553         /* Now fixup OBP's idea about where we really are mapped. */
 554         prom_printf("Remapping the kernel... ");
 555         remap_kernel();
 556         prom_printf("done.\n");
 557
 558         prom_printf("Registering callbacks... ");
 559         register_prom_callbacks();
 560         prom_printf("done.\n");
 561 }
 562
 563 void prom_world(int enter)
 564 {
 565         if (!enter)
 566                 set_fs((mm_segment_t) { get_thread_current_ds() });
 567
 568         __asm__ __volatile__("flushw");
 569 }
 570
 571 #ifdef DCACHE_ALIASING_POSSIBLE
 572 void __flush_dcache_range(unsigned long start, unsigned long end)
 573 {
 574         unsigned long va;
 575
 576         if (tlb_type == spitfire) {
 577                 int n = 0;
 578
 579                 for (va = start; va < end; va += 32) {
 580                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 581                         if (++n >= 512)
 582                                 break;
 583                 }
 584         } else {
 585                 start = __pa(start);
 586                 end = __pa(end);
 587                 for (va = start; va < end; va += 32)
 588                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 589                                              "membar #Sync"
 590                                              : /* no outputs */
 591                                              : "r" (va),
 592                                                "i" (ASI_DCACHE_INVALIDATE));
 593         }
 594 }
 595 #endif /* DCACHE_ALIASING_POSSIBLE */
 596
 597 /* If not locked, zap it. */
 598 void __flush_tlb_all(void)
 599 {
 600         unsigned long pstate;
 601         int i;
 602
 603         __asm__ __volatile__("flushw\n\t"
 604                              "rdpr      %%pstate, %0\n\t"
 605                              "wrpr      %0, %1, %%pstate"
 606                              : "=r" (pstate)
 607                              : "i" (PSTATE_IE));
 608         if (tlb_type == spitfire) {
 609                 for (i = 0; i < 64; i++) {
 610                         /* Spitfire Errata #32 workaround */
 611                         /* NOTE: Always runs on spitfire, so no
 612                          *       cheetah+ page size encodings.
 613                          */
 614                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 615                                              "flush     %%g6"
 616                                              : /* No outputs */
 617                                              : "r" (0),
 618                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 619
 620                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
 621                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 622                                                      "membar #Sync"
 623                                                      : /* no outputs */
 624                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 625                                 spitfire_put_dtlb_data(i, 0x0UL);
 626                         }
 627
 628                         /* Spitfire Errata #32 workaround */
 629                         /* NOTE: Always runs on spitfire, so no
 630                          *       cheetah+ page size encodings.
 631                          */
 632                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 633                                              "flush     %%g6"
 634                                              : /* No outputs */
 635                                              : "r" (0),
 636                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 637
 638                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
 639                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 640                                                      "membar #Sync"
 641                                                      : /* no outputs */
 642                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 643                                 spitfire_put_itlb_data(i, 0x0UL);
 644                         }
 645                 }
 646         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 647                 cheetah_flush_dtlb_all();
 648                 cheetah_flush_itlb_all();
 649         }
 650         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 651                              : : "r" (pstate));
 652 }
 653
 654 /* Caller does TLB context flushing on local CPU if necessary.
 655  * The caller also ensures that CTX_VALID(mm->context) is false.
 656  *
 657  * We must be careful about boundary cases so that we never
 658  * let the user have CTX 0 (nucleus) or we ever use a CTX
 659  * version of zero (and thus NO_CONTEXT would not be caught
 660  * by version mis-match tests in mmu_context.h).
 661  */
 662 void get_new_mmu_context(struct mm_struct *mm)
 663 {
 664         unsigned long ctx, new_ctx;
 665         unsigned long orig_pgsz_bits;
 666
 667
 668         spin_lock(&ctx_alloc_lock);
 669         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 670         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 671         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 672         if (new_ctx >= (1 << CTX_NR_BITS)) {
 673                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 674                 if (new_ctx >= ctx) {
 675                         int i;
 676                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 677                                 CTX_FIRST_VERSION;
 678                         if (new_ctx == 1)
 679                                 new_ctx = CTX_FIRST_VERSION;
 680
 681                         /* Don't call memset, for 16 entries that's just
 682                          * plain silly...
 683                          */
 684                         mmu_context_bmap[0] = 3;
 685                         mmu_context_bmap[1] = 0;
 686                         mmu_context_bmap[2] = 0;
 687                         mmu_context_bmap[3] = 0;
 688                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 689                                 mmu_context_bmap[i + 0] = 0;
 690                                 mmu_context_bmap[i + 1] = 0;
 691                                 mmu_context_bmap[i + 2] = 0;
 692                                 mmu_context_bmap[i + 3] = 0;
 693                         }
 694                         goto out;
 695                 }
 696         }
 697         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 698         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 699 out:
 700         tlb_context_cache = new_ctx;
 701         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 702         spin_unlock(&ctx_alloc_lock);
 703 }
 704
 705 void sparc_ultra_dump_itlb(void)
 706 {
 707         int slot;
 708
 709         if (tlb_type == spitfire) {
 710                 printk ("Contents of itlb: ");
 711                 for (slot = 0; slot < 14; slot++) printk ("    ");
 712                 printk ("%2x:%016lx,%016lx\n",
 713                         0,
 714                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
 715                 for (slot = 1; slot < 64; slot+=3) {
 716                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 717                                 slot,
 718                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
 719                                 slot+1,
 720                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
 721                                 slot+2,
 722                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
 723                 }
 724         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 725                 printk ("Contents of itlb0:\n");
 726                 for (slot = 0; slot < 16; slot+=2) {
 727                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 728                                 slot,
 729                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
 730                                 slot+1,
 731                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
 732                 }
 733                 printk ("Contents of itlb2:\n");
 734                 for (slot = 0; slot < 128; slot+=2) {
 735                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 736                                 slot,
 737                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
 738                                 slot+1,
 739                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
 740                 }
 741         }
 742 }
 743
 744 void sparc_ultra_dump_dtlb(void)
 745 {
 746         int slot;
 747
 748         if (tlb_type == spitfire) {
 749                 printk ("Contents of dtlb: ");
 750                 for (slot = 0; slot < 14; slot++) printk ("    ");
 751                 printk ("%2x:%016lx,%016lx\n", 0,
 752                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
 753                 for (slot = 1; slot < 64; slot+=3) {
 754                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 755                                 slot,
 756                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
 757                                 slot+1,
 758                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
 759                                 slot+2,
 760                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
 761                 }
 762         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 763                 printk ("Contents of dtlb0:\n");
 764                 for (slot = 0; slot < 16; slot+=2) {
 765                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 766                                 slot,
 767                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
 768                                 slot+1,
 769                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
 770                 }
 771                 printk ("Contents of dtlb2:\n");
 772                 for (slot = 0; slot < 512; slot+=2) {
 773                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 774                                 slot,
 775                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
 776                                 slot+1,
 777                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
 778                 }
 779                 if (tlb_type == cheetah_plus) {
 780                         printk ("Contents of dtlb3:\n");
 781                         for (slot = 0; slot < 512; slot+=2) {
 782                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 783                                         slot,
 784                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
 785                                         slot+1,
 786                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
 787                         }
 788                 }
 789         }
 790 }
 791
 792 static inline void spitfire_errata32(void)
 793 {
 794         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 795                              "flush     %%g6"
 796                              : /* No outputs */
 797                              : "r" (0),
 798                                "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 799 }
 800
 801 extern unsigned long cmdline_memory_size;
 802
 803 unsigned long __init bootmem_init(unsigned long *pages_avail)
 804 {
 805         unsigned long bootmap_size, start_pfn, end_pfn;
 806         unsigned long end_of_phys_memory = 0UL;
 807         unsigned long bootmap_pfn, bytes_avail, size;
 808         int i;
 809
 810 #ifdef CONFIG_DEBUG_BOOTMEM
 811         prom_printf("bootmem_init: Scan pavail, ");
 812 #endif
 813
 814         bytes_avail = 0UL;
 815         for (i = 0; i < pavail_ents; i++) {
 816                 end_of_phys_memory = pavail[i].phys_addr +
 817                         pavail[i].reg_size;
 818                 bytes_avail += pavail[i].reg_size;
 819                 if (cmdline_memory_size) {
 820                         if (bytes_avail > cmdline_memory_size) {
 821                                 unsigned long slack = bytes_avail - cmdline_memory_size;
 822
 823                                 bytes_avail -= slack;
 824                                 end_of_phys_memory -= slack;
 825
 826                                 pavail[i].reg_size -= slack;
 827                                 if ((long)pavail[i].reg_size <= 0L) {
 828                                         pavail[i].phys_addr = 0xdeadbeefUL;
 829                                         pavail[i].reg_size = 0UL;
 830                                         pavail_ents = i;
 831                                 } else {
 832                                         pavail[i+1].reg_size = 0Ul;
 833                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
 834                                         pavail_ents = i + 1;
 835                                 }
 836                                 break;
 837                         }
 838                 }
 839         }
 840
 841         *pages_avail = bytes_avail >> PAGE_SHIFT;
 842
 843         /* Start with page aligned address of last symbol in kernel
 844          * image.  The kernel is hard mapped below PAGE_OFFSET in a
 845          * 4MB locked TLB translation.
 846          */
 847         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
 848
 849         bootmap_pfn = start_pfn;
 850
 851         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
 852
 853 #ifdef CONFIG_BLK_DEV_INITRD
 854         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
 855         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 856                 unsigned long ramdisk_image = sparc_ramdisk_image ?
 857                         sparc_ramdisk_image : sparc_ramdisk_image64;
 858                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
 859                         ramdisk_image -= KERNBASE;
 860                 initrd_start = ramdisk_image + phys_base;
 861                 initrd_end = initrd_start + sparc_ramdisk_size;
 862                 if (initrd_end > end_of_phys_memory) {
 863                         printk(KERN_CRIT "initrd extends beyond end of memory "
 864                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
 865                                initrd_end, end_of_phys_memory);
 866                         initrd_start = 0;
 867                 }
 868                 if (initrd_start) {
 869                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
 870                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
 871                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
 872                 }
 873         }
 874 #endif
 875         /* Initialize the boot-time allocator. */
 876         max_pfn = max_low_pfn = end_pfn;
 877         min_low_pfn = pfn_base;
 878
 879 #ifdef CONFIG_DEBUG_BOOTMEM
 880         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
 881                     min_low_pfn, bootmap_pfn, max_low_pfn);
 882 #endif
 883         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
 884
 885         /* Now register the available physical memory with the
 886          * allocator.
 887          */
 888         for (i = 0; i < pavail_ents; i++) {
 889 #ifdef CONFIG_DEBUG_BOOTMEM
 890                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
 891                             i, pavail[i].phys_addr, pavail[i].reg_size);
 892 #endif
 893                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
 894         }
 895
 896 #ifdef CONFIG_BLK_DEV_INITRD
 897         if (initrd_start) {
 898                 size = initrd_end - initrd_start;
 899
 900                 /* Resert the initrd image area. */
 901 #ifdef CONFIG_DEBUG_BOOTMEM
 902                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
 903                         initrd_start, initrd_end);
 904 #endif
 905                 reserve_bootmem(initrd_start, size);
 906                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 907
 908                 initrd_start += PAGE_OFFSET;
 909                 initrd_end += PAGE_OFFSET;
 910         }
 911 #endif
 912         /* Reserve the kernel text/data/bss. */
 913 #ifdef CONFIG_DEBUG_BOOTMEM
 914         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
 915 #endif
 916         reserve_bootmem(kern_base, kern_size);
 917         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
 918
 919         /* Reserve the bootmem map.   We do not account for it
 920          * in pages_avail because we will release that memory
 921          * in free_all_bootmem.
 922          */
 923         size = bootmap_size;
 924 #ifdef CONFIG_DEBUG_BOOTMEM
 925         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
 926                     (bootmap_pfn << PAGE_SHIFT), size);
 927 #endif
 928         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
 929         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 930
 931         return end_pfn;
 932 }
 933
 934 #ifdef CONFIG_DEBUG_PAGEALLOC
 935 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
 936 {
 937         unsigned long vstart = PAGE_OFFSET + pstart;
 938         unsigned long vend = PAGE_OFFSET + pend;
 939         unsigned long alloc_bytes = 0UL;
 940
 941         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
 942                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
 943                             vstart, vend);
 944                 prom_halt();
 945         }
 946
 947         while (vstart < vend) {
 948                 unsigned long this_end, paddr = __pa(vstart);
 949                 pgd_t *pgd = pgd_offset_k(vstart);
 950                 pud_t *pud;
 951                 pmd_t *pmd;
 952                 pte_t *pte;
 953
 954                 pud = pud_offset(pgd, vstart);
 955                 if (pud_none(*pud)) {
 956                         pmd_t *new;
 957
 958                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
 959                         alloc_bytes += PAGE_SIZE;
 960                         pud_populate(&init_mm, pud, new);
 961                 }
 962
 963                 pmd = pmd_offset(pud, vstart);
 964                 if (!pmd_present(*pmd)) {
 965                         pte_t *new;
 966
 967                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
 968                         alloc_bytes += PAGE_SIZE;
 969                         pmd_populate_kernel(&init_mm, pmd, new);
 970                 }
 971
 972                 pte = pte_offset_kernel(pmd, vstart);
 973                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
 974                 if (this_end > vend)
 975                         this_end = vend;
 976
 977                 while (vstart < this_end) {
 978                         pte_val(*pte) = (paddr | pgprot_val(prot));
 979
 980                         vstart += PAGE_SIZE;
 981                         paddr += PAGE_SIZE;
 982                         pte++;
 983                 }
 984         }
 985
 986         return alloc_bytes;
 987 }
 988
 989 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
 990 static int pall_ents __initdata;
 991
 992 extern unsigned int kvmap_linear_patch[1];
 993
 994 static void __init kernel_physical_mapping_init(void)
 995 {
 996         unsigned long i, mem_alloced = 0UL;
 997
 998         read_obp_memory("reg", &pall[0], &pall_ents);
 999
1000         for (i = 0; i < pall_ents; i++) {
1001                 unsigned long phys_start, phys_end;
1002
1003                 phys_start = pall[i].phys_addr;
1004                 phys_end = phys_start + pall[i].reg_size;
1005                 mem_alloced += kernel_map_range(phys_start, phys_end,
1006                                                 PAGE_KERNEL);
1007         }
1008
1009         printk("Allocated %ld bytes for kernel page tables.\n",
1010                mem_alloced);
1011
1012         kvmap_linear_patch[0] = 0x01000000; /* nop */
1013         flushi(&kvmap_linear_patch[0]);
1014
1015         __flush_tlb_all();
1016 }
1017
1018 void kernel_map_pages(struct page *page, int numpages, int enable)
1019 {
1020         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1021         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1022
1023         kernel_map_range(phys_start, phys_end,
1024                          (enable ? PAGE_KERNEL : __pgprot(0)));
1025
1026         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1027                                PAGE_OFFSET + phys_end);
1028
1029         /* we should perform an IPI and flush all tlbs,
1030          * but that can deadlock->flush only current cpu.
1031          */
1032         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1033                                  PAGE_OFFSET + phys_end);
1034 }
1035 #endif
1036
1037 unsigned long __init find_ecache_flush_span(unsigned long size)
1038 {
1039         int i;
1040
1041         for (i = 0; i < pavail_ents; i++) {
1042                 if (pavail[i].reg_size >= size)
1043                         return pavail[i].phys_addr;
1044         }
1045
1046         return ~0UL;
1047 }
1048
1049 static void __init tsb_phys_patch(void)
1050 {
1051         struct tsb_phys_patch_entry *p;
1052
1053         p = &__tsb_phys_patch;
1054         while (p < &__tsb_phys_patch_end) {
1055                 unsigned long addr = p->addr;
1056
1057                 *(unsigned int *) addr = p->insn;
1058                 wmb();
1059                 __asm__ __volatile__("flush     %0"
1060                                      : /* no outputs */
1061                                      : "r" (addr));
1062
1063                 p++;
1064         }
1065 }
1066
1067 /* paging_init() sets up the page tables */
1068
1069 extern void cheetah_ecache_flush_init(void);
1070
1071 static unsigned long last_valid_pfn;
1072 pgd_t swapper_pg_dir[2048];
1073
1074 void __init paging_init(void)
1075 {
1076         unsigned long end_pfn, pages_avail, shift;
1077         unsigned long real_end, i;
1078
1079         if (tlb_type == cheetah_plus)
1080                 tsb_phys_patch();
1081
1082         /* Find available physical memory... */
1083         read_obp_memory("available", &pavail[0], &pavail_ents);
1084
1085         phys_base = 0xffffffffffffffffUL;
1086         for (i = 0; i < pavail_ents; i++)
1087                 phys_base = min(phys_base, pavail[i].phys_addr);
1088
1089         pfn_base = phys_base >> PAGE_SHIFT;
1090
1091         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1092         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1093
1094         set_bit(0, mmu_context_bmap);
1095
1096         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1097
1098         real_end = (unsigned long)_end;
1099         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1100                 bigkernel = 1;
1101         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1102                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1103                 prom_halt();
1104         }
1105
1106         /* Set kernel pgd to upper alias so physical page computations
1107          * work.
1108          */
1109         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1110
1111         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1112
1113         /* Now can init the kernel/bad page tables. */
1114         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1115                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1116
1117         inherit_prom_mappings();
1118
1119         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1120         setup_tba();
1121
1122         __flush_tlb_all();
1123
1124         /* Setup bootmem... */
1125         pages_avail = 0;
1126         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1127
1128 #ifdef CONFIG_DEBUG_PAGEALLOC
1129         kernel_physical_mapping_init();
1130 #endif
1131
1132         {
1133                 unsigned long zones_size[MAX_NR_ZONES];
1134                 unsigned long zholes_size[MAX_NR_ZONES];
1135                 unsigned long npages;
1136                 int znum;
1137
1138                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1139                         zones_size[znum] = zholes_size[znum] = 0;
1140
1141                 npages = end_pfn - pfn_base;
1142                 zones_size[ZONE_DMA] = npages;
1143                 zholes_size[ZONE_DMA] = npages - pages_avail;
1144
1145                 free_area_init_node(0, &contig_page_data, zones_size,
1146                                     phys_base >> PAGE_SHIFT, zholes_size);
1147         }
1148
1149         device_scan();
1150 }
1151
1152 static void __init taint_real_pages(void)
1153 {
1154         int i;
1155
1156         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1157
1158         /* Find changes discovered in the physmem available rescan and
1159          * reserve the lost portions in the bootmem maps.
1160          */
1161         for (i = 0; i < pavail_ents; i++) {
1162                 unsigned long old_start, old_end;
1163
1164                 old_start = pavail[i].phys_addr;
1165                 old_end = old_start +
1166                         pavail[i].reg_size;
1167                 while (old_start < old_end) {
1168                         int n;
1169
1170                         for (n = 0; pavail_rescan_ents; n++) {
1171                                 unsigned long new_start, new_end;
1172
1173                                 new_start = pavail_rescan[n].phys_addr;
1174                                 new_end = new_start +
1175                                         pavail_rescan[n].reg_size;
1176
1177                                 if (new_start <= old_start &&
1178                                     new_end >= (old_start + PAGE_SIZE)) {
1179                                         set_bit(old_start >> 22,
1180                                                 sparc64_valid_addr_bitmap);
1181                                         goto do_next_page;
1182                                 }
1183                         }
1184                         reserve_bootmem(old_start, PAGE_SIZE);
1185
1186                 do_next_page:
1187                         old_start += PAGE_SIZE;
1188                 }
1189         }
1190 }
1191
1192 void __init mem_init(void)
1193 {
1194         unsigned long codepages, datapages, initpages;
1195         unsigned long addr, last;
1196         int i;
1197
1198         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1199         i += 1;
1200         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1201         if (sparc64_valid_addr_bitmap == NULL) {
1202                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1203                 prom_halt();
1204         }
1205         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1206
1207         addr = PAGE_OFFSET + kern_base;
1208         last = PAGE_ALIGN(kern_size) + addr;
1209         while (addr < last) {
1210                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1211                 addr += PAGE_SIZE;
1212         }
1213
1214         taint_real_pages();
1215
1216         max_mapnr = last_valid_pfn - pfn_base;
1217         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1218
1219 #ifdef CONFIG_DEBUG_BOOTMEM
1220         prom_printf("mem_init: Calling free_all_bootmem().\n");
1221 #endif
1222         totalram_pages = num_physpages = free_all_bootmem() - 1;
1223
1224         /*
1225          * Set up the zero page, mark it reserved, so that page count
1226          * is not manipulated when freeing the page from user ptes.
1227          */
1228         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1229         if (mem_map_zero == NULL) {
1230                 prom_printf("paging_init: Cannot alloc zero page.\n");
1231                 prom_halt();
1232         }
1233         SetPageReserved(mem_map_zero);
1234
1235         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1236         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1237         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1238         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1239         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1240         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1241
1242         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1243                nr_free_pages() << (PAGE_SHIFT-10),
1244                codepages << (PAGE_SHIFT-10),
1245                datapages << (PAGE_SHIFT-10),
1246                initpages << (PAGE_SHIFT-10),
1247                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1248
1249         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1250                 cheetah_ecache_flush_init();
1251 }
1252
1253 void free_initmem(void)
1254 {
1255         unsigned long addr, initend;
1256
1257         /*
1258          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1259          */
1260         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1261         initend = (unsigned long)(__init_end) & PAGE_MASK;
1262         for (; addr < initend; addr += PAGE_SIZE) {
1263                 unsigned long page;
1264                 struct page *p;
1265
1266                 page = (addr +
1267                         ((unsigned long) __va(kern_base)) -
1268                         ((unsigned long) KERNBASE));
1269                 memset((void *)addr, 0xcc, PAGE_SIZE);
1270                 p = virt_to_page(page);
1271
1272                 ClearPageReserved(p);
1273                 set_page_count(p, 1);
1274                 __free_page(p);
1275                 num_physpages++;
1276                 totalram_pages++;
1277         }
1278 }
1279
1280 #ifdef CONFIG_BLK_DEV_INITRD
1281 void free_initrd_mem(unsigned long start, unsigned long end)
1282 {
1283         if (start < end)
1284                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1285         for (; start < end; start += PAGE_SIZE) {
1286                 struct page *p = virt_to_page(start);
1287
1288                 ClearPageReserved(p);
1289                 set_page_count(p, 1);
1290                 __free_page(p);
1291                 num_physpages++;
1292                 totalram_pages++;
1293         }
1294 }
1295 #endif