2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
35 #include <asm/pgalloc.h>
36 #include <asm/mach_apic.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
45 int disable_apic_timer __cpuinitdata;
46 static int apic_calibrate_pmtmr __initdata;
48 /* Local APIC timer works in C2? */
49 int local_apic_timer_c2_ok;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
52 static struct resource lapic_resource = {
54 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
57 static unsigned int calibration_result;
59 static int lapic_next_event(unsigned long delta,
60 struct clock_event_device *evt);
61 static void lapic_timer_setup(enum clock_event_mode mode,
62 struct clock_event_device *evt);
64 static void lapic_timer_broadcast(cpumask_t mask);
66 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen);
68 static struct clock_event_device lapic_clockevent = {
70 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
71 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
73 .set_mode = lapic_timer_setup,
74 .set_next_event = lapic_next_event,
75 .broadcast = lapic_timer_broadcast,
79 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
81 static int lapic_next_event(unsigned long delta,
82 struct clock_event_device *evt)
84 apic_write(APIC_TMICT, delta);
88 static void lapic_timer_setup(enum clock_event_mode mode,
89 struct clock_event_device *evt)
94 /* Lapic used as dummy for broadcast ? */
95 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
98 local_irq_save(flags);
101 case CLOCK_EVT_MODE_PERIODIC:
102 case CLOCK_EVT_MODE_ONESHOT:
103 __setup_APIC_LVTT(calibration_result,
104 mode != CLOCK_EVT_MODE_PERIODIC, 1);
106 case CLOCK_EVT_MODE_UNUSED:
107 case CLOCK_EVT_MODE_SHUTDOWN:
108 v = apic_read(APIC_LVTT);
109 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
110 apic_write(APIC_LVTT, v);
112 case CLOCK_EVT_MODE_RESUME:
113 /* Nothing to do here */
117 local_irq_restore(flags);
121 * Local APIC timer broadcast function
123 static void lapic_timer_broadcast(cpumask_t mask)
126 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
130 static void apic_pm_activate(void);
132 void apic_wait_icr_idle(void)
134 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
138 u32 safe_apic_wait_icr_idle(void)
145 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
149 } while (timeout++ < 1000);
154 void enable_NMI_through_LVT0 (void * dummy)
158 /* unmask and set to NMI */
160 apic_write(APIC_LVT0, v);
163 int lapic_get_maxlvt(void)
165 unsigned int v, maxlvt;
167 v = apic_read(APIC_LVR);
168 maxlvt = GET_APIC_MAXLVT(v);
173 * 'what should we do if we get a hw irq event on an illegal vector'.
174 * each architecture has to answer this themselves.
176 void ack_bad_irq(unsigned int irq)
178 printk("unexpected IRQ trap at vector %02x\n", irq);
180 * Currently unexpected vectors happen only on SMP and APIC.
181 * We _must_ ack these because every local APIC has only N
182 * irq slots per priority level, and a 'hanging, unacked' IRQ
183 * holds up an irq slot - in excessive cases (when multiple
184 * unexpected vectors occur) that might lock up the APIC
186 * But don't ack when the APIC is disabled. -AK
192 void clear_local_APIC(void)
197 maxlvt = lapic_get_maxlvt();
200 * Masking an LVT entry can trigger a local APIC error
201 * if the vector is zero. Mask LVTERR first to prevent this.
204 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
205 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
208 * Careful: we have to set masks only first to deassert
209 * any level-triggered sources.
211 v = apic_read(APIC_LVTT);
212 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
213 v = apic_read(APIC_LVT0);
214 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
215 v = apic_read(APIC_LVT1);
216 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
218 v = apic_read(APIC_LVTPC);
219 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
223 * Clean APIC state for other OSs:
225 apic_write(APIC_LVTT, APIC_LVT_MASKED);
226 apic_write(APIC_LVT0, APIC_LVT_MASKED);
227 apic_write(APIC_LVT1, APIC_LVT_MASKED);
229 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
231 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
232 apic_write(APIC_ESR, 0);
236 void disconnect_bsp_APIC(int virt_wire_setup)
238 /* Go back to Virtual Wire compatibility mode */
241 /* For the spurious interrupt use vector F, and enable it */
242 value = apic_read(APIC_SPIV);
243 value &= ~APIC_VECTOR_MASK;
244 value |= APIC_SPIV_APIC_ENABLED;
246 apic_write(APIC_SPIV, value);
248 if (!virt_wire_setup) {
250 * For LVT0 make it edge triggered, active high,
251 * external and enabled
253 value = apic_read(APIC_LVT0);
254 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
255 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
256 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
257 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
258 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
259 apic_write(APIC_LVT0, value);
262 apic_write(APIC_LVT0, APIC_LVT_MASKED);
265 /* For LVT1 make it edge triggered, active high, nmi and enabled */
266 value = apic_read(APIC_LVT1);
267 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
268 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
269 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
270 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
271 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
272 apic_write(APIC_LVT1, value);
275 void disable_local_APIC(void)
282 * Disable APIC (implies clearing of registers
285 value = apic_read(APIC_SPIV);
286 value &= ~APIC_SPIV_APIC_ENABLED;
287 apic_write(APIC_SPIV, value);
290 void lapic_shutdown(void)
297 local_irq_save(flags);
299 disable_local_APIC();
301 local_irq_restore(flags);
305 * This is to verify that we're looking at a real local APIC.
306 * Check these against your board if the CPUs aren't getting
307 * started for no apparent reason.
309 int __init verify_local_APIC(void)
311 unsigned int reg0, reg1;
314 * The version register is read-only in a real APIC.
316 reg0 = apic_read(APIC_LVR);
317 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
318 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
319 reg1 = apic_read(APIC_LVR);
320 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
323 * The two version reads above should print the same
324 * numbers. If the second one is different, then we
325 * poke at a non-APIC.
331 * Check if the version looks reasonably.
333 reg1 = GET_APIC_VERSION(reg0);
334 if (reg1 == 0x00 || reg1 == 0xff)
336 reg1 = lapic_get_maxlvt();
337 if (reg1 < 0x02 || reg1 == 0xff)
341 * The ID register is read/write in a real APIC.
343 reg0 = apic_read(APIC_ID);
344 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
345 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
346 reg1 = apic_read(APIC_ID);
347 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
348 apic_write(APIC_ID, reg0);
349 if (reg1 != (reg0 ^ APIC_ID_MASK))
353 * The next two are just to see if we have sane values.
354 * They're only really relevant if we're in Virtual Wire
355 * compatibility mode, but most boxes are anymore.
357 reg0 = apic_read(APIC_LVT0);
358 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
359 reg1 = apic_read(APIC_LVT1);
360 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
365 void __init sync_Arb_IDs(void)
367 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
368 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
369 if (ver >= 0x14) /* P4 or higher */
375 apic_wait_icr_idle();
377 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
378 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
383 * An initial setup of the virtual wire mode.
385 void __init init_bsp_APIC(void)
390 * Don't do the setup now if we have a SMP BIOS as the
391 * through-I/O-APIC virtual wire mode might be active.
393 if (smp_found_config || !cpu_has_apic)
396 value = apic_read(APIC_LVR);
399 * Do not trust the local APIC being empty at bootup.
406 value = apic_read(APIC_SPIV);
407 value &= ~APIC_VECTOR_MASK;
408 value |= APIC_SPIV_APIC_ENABLED;
409 value |= APIC_SPIV_FOCUS_DISABLED;
410 value |= SPURIOUS_APIC_VECTOR;
411 apic_write(APIC_SPIV, value);
414 * Set up the virtual wire mode.
416 apic_write(APIC_LVT0, APIC_DM_EXTINT);
418 apic_write(APIC_LVT1, value);
421 void __cpuinit setup_local_APIC (void)
423 unsigned int value, maxlvt;
426 value = apic_read(APIC_LVR);
428 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
431 * Double-check whether this APIC is really registered.
432 * This is meaningless in clustered apic mode, so we skip it.
434 if (!apic_id_registered())
438 * Intel recommends to set DFR, LDR and TPR before enabling
439 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
440 * document number 292116). So here it goes...
445 * Set Task Priority to 'accept all'. We never change this
448 value = apic_read(APIC_TASKPRI);
449 value &= ~APIC_TPRI_MASK;
450 apic_write(APIC_TASKPRI, value);
453 * After a crash, we no longer service the interrupts and a pending
454 * interrupt from previous kernel might still have ISR bit set.
456 * Most probably by now CPU has serviced that pending interrupt and
457 * it might not have done the ack_APIC_irq() because it thought,
458 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
459 * does not clear the ISR bit and cpu thinks it has already serivced
460 * the interrupt. Hence a vector might get locked. It was noticed
461 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
463 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
464 value = apic_read(APIC_ISR + i*0x10);
465 for (j = 31; j >= 0; j--) {
472 * Now that we are all set up, enable the APIC
474 value = apic_read(APIC_SPIV);
475 value &= ~APIC_VECTOR_MASK;
479 value |= APIC_SPIV_APIC_ENABLED;
481 /* We always use processor focus */
484 * Set spurious IRQ vector
486 value |= SPURIOUS_APIC_VECTOR;
487 apic_write(APIC_SPIV, value);
492 * set up through-local-APIC on the BP's LINT0. This is not
493 * strictly necessary in pure symmetric-IO mode, but sometimes
494 * we delegate interrupts to the 8259A.
497 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
499 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
500 if (!smp_processor_id() && !value) {
501 value = APIC_DM_EXTINT;
502 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
505 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
506 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
509 apic_write(APIC_LVT0, value);
512 * only the BP should see the LINT1 NMI signal, obviously.
514 if (!smp_processor_id())
517 value = APIC_DM_NMI | APIC_LVT_MASKED;
518 apic_write(APIC_LVT1, value);
522 maxlvt = lapic_get_maxlvt();
523 oldvalue = apic_read(APIC_ESR);
524 value = ERROR_APIC_VECTOR; // enables sending errors
525 apic_write(APIC_LVTERR, value);
527 * spec says clear errors after enabling vector.
530 apic_write(APIC_ESR, 0);
531 value = apic_read(APIC_ESR);
532 if (value != oldvalue)
533 apic_printk(APIC_VERBOSE,
534 "ESR value after enabling vector: %08x, after %08x\n",
538 nmi_watchdog_default();
539 setup_apic_nmi_watchdog(NULL);
546 /* 'active' is true if the local APIC was enabled by us and
547 not the BIOS; this signifies that we are also responsible
548 for disabling it before entering apm/acpi suspend */
550 /* r/w apic fields */
551 unsigned int apic_id;
552 unsigned int apic_taskpri;
553 unsigned int apic_ldr;
554 unsigned int apic_dfr;
555 unsigned int apic_spiv;
556 unsigned int apic_lvtt;
557 unsigned int apic_lvtpc;
558 unsigned int apic_lvt0;
559 unsigned int apic_lvt1;
560 unsigned int apic_lvterr;
561 unsigned int apic_tmict;
562 unsigned int apic_tdcr;
563 unsigned int apic_thmr;
566 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
571 if (!apic_pm_state.active)
574 maxlvt = lapic_get_maxlvt();
576 apic_pm_state.apic_id = apic_read(APIC_ID);
577 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
578 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
579 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
580 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
581 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
583 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
584 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
585 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
586 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
587 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
588 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
589 #ifdef CONFIG_X86_MCE_INTEL
591 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
593 local_irq_save(flags);
594 disable_local_APIC();
595 local_irq_restore(flags);
599 static int lapic_resume(struct sys_device *dev)
605 if (!apic_pm_state.active)
608 maxlvt = lapic_get_maxlvt();
610 local_irq_save(flags);
611 rdmsr(MSR_IA32_APICBASE, l, h);
612 l &= ~MSR_IA32_APICBASE_BASE;
613 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
614 wrmsr(MSR_IA32_APICBASE, l, h);
615 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
616 apic_write(APIC_ID, apic_pm_state.apic_id);
617 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
618 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
619 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
620 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
621 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
622 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
623 #ifdef CONFIG_X86_MCE_INTEL
625 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
628 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
629 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
630 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
631 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
632 apic_write(APIC_ESR, 0);
634 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
635 apic_write(APIC_ESR, 0);
637 local_irq_restore(flags);
641 static struct sysdev_class lapic_sysclass = {
643 .resume = lapic_resume,
644 .suspend = lapic_suspend,
647 static struct sys_device device_lapic = {
649 .cls = &lapic_sysclass,
652 static void __cpuinit apic_pm_activate(void)
654 apic_pm_state.active = 1;
657 static int __init init_lapic_sysfs(void)
662 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
663 error = sysdev_class_register(&lapic_sysclass);
665 error = sysdev_register(&device_lapic);
668 device_initcall(init_lapic_sysfs);
670 #else /* CONFIG_PM */
672 static void apic_pm_activate(void) { }
674 #endif /* CONFIG_PM */
676 static int __init apic_set_verbosity(char *str)
679 skip_ioapic_setup = 0;
683 if (strcmp("debug", str) == 0)
684 apic_verbosity = APIC_DEBUG;
685 else if (strcmp("verbose", str) == 0)
686 apic_verbosity = APIC_VERBOSE;
688 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
689 " use apic=verbose or apic=debug\n", str);
695 early_param("apic", apic_set_verbosity);
698 * Detect and enable local APICs on non-SMP boards.
699 * Original code written by Keir Fraser.
700 * On AMD64 we trust the BIOS - if it says no APIC it is likely
701 * not correctly set up (usually the APIC timer won't work etc.)
704 static int __init detect_init_APIC (void)
707 printk(KERN_INFO "No local APIC present\n");
711 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
716 void __init init_apic_mappings(void)
718 unsigned long apic_phys;
721 * If no local APIC can be found then set up a fake all
722 * zeroes page to simulate the local APIC and another
723 * one for the IO-APIC.
725 if (!smp_found_config && detect_init_APIC()) {
726 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
727 apic_phys = __pa(apic_phys);
729 apic_phys = mp_lapic_addr;
731 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
732 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
733 APIC_BASE, apic_phys);
735 /* Put local APIC into the resource map. */
736 lapic_resource.start = apic_phys;
737 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
738 insert_resource(&iomem_resource, &lapic_resource);
741 * Fetch the APIC ID of the BSP in case we have a
742 * default configuration (or the MP table is broken).
744 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
748 * This function sets up the local APIC timer, with a timeout of
749 * 'clocks' APIC bus clock. During calibration we actually call
750 * this function twice on the boot CPU, once with a bogus timeout
751 * value, second time for real. The other (noncalibrating) CPUs
752 * call this function only once, with the real, calibrated value.
754 * We do reads before writes even if unnecessary, to get around the
755 * P5 APIC double write bug.
758 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
760 unsigned int lvtt_value, tmp_value;
762 lvtt_value = LOCAL_TIMER_VECTOR;
764 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
766 lvtt_value |= APIC_LVT_MASKED;
768 apic_write(APIC_LVTT, lvtt_value);
773 tmp_value = apic_read(APIC_TDCR);
774 apic_write(APIC_TDCR, (tmp_value
775 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
779 apic_write(APIC_TMICT, clocks);
782 static void setup_APIC_timer(void)
784 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
786 memcpy(levt, &lapic_clockevent, sizeof(*levt));
787 levt->cpumask = cpumask_of_cpu(smp_processor_id());
789 clockevents_register_device(levt);
793 * In this function we calibrate APIC bus clocks to the external
794 * timer. Unfortunately we cannot use jiffies and the timer irq
795 * to calibrate, since some later bootup code depends on getting
796 * the first irq? Ugh.
798 * We want to do the calibration only once since we
799 * want to have local timer irqs syncron. CPUs connected
800 * by the same APIC bus have the very same bus frequency.
801 * And we want to have irqs off anyways, no accidental
805 #define TICK_COUNT 100000000
807 static void __init calibrate_APIC_clock(void)
809 unsigned apic, apic_start;
810 unsigned long tsc, tsc_start;
816 * Put whatever arbitrary (but long enough) timeout
817 * value into the APIC clock, we just want to get the
818 * counter running for calibration.
820 * No interrupt enable !
822 __setup_APIC_LVTT(250000000, 0, 0);
824 apic_start = apic_read(APIC_TMCCT);
825 #ifdef CONFIG_X86_PM_TIMER
826 if (apic_calibrate_pmtmr && pmtmr_ioport) {
827 pmtimer_wait(5000); /* 5ms wait */
828 apic = apic_read(APIC_TMCCT);
829 result = (apic_start - apic) * 1000L / 5;
836 apic = apic_read(APIC_TMCCT);
838 } while ((tsc - tsc_start) < TICK_COUNT &&
839 (apic_start - apic) < TICK_COUNT);
841 result = (apic_start - apic) * 1000L * tsc_khz /
847 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
849 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
850 result / 1000 / 1000, result / 1000 % 1000);
852 /* Calculate the scaled math multiplication factor */
853 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
854 lapic_clockevent.max_delta_ns =
855 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
856 lapic_clockevent.min_delta_ns =
857 clockevent_delta2ns(0xF, &lapic_clockevent);
859 calibration_result = result / HZ;
862 void __init setup_boot_APIC_clock (void)
865 * The local apic timer can be disabled via the kernel commandline.
866 * Register the lapic timer as a dummy clock event source on SMP
867 * systems, so the broadcast mechanism is used. On UP systems simply
870 if (disable_apic_timer) {
871 printk(KERN_INFO "Disabling APIC timer\n");
872 /* No broadcast on UP ! */
873 if (num_possible_cpus() > 1)
878 printk(KERN_INFO "Using local APIC timer interrupts.\n");
879 calibrate_APIC_clock();
882 * If nmi_watchdog is set to IO_APIC, we need the
883 * PIT/HPET going. Otherwise register lapic as a dummy
886 if (nmi_watchdog != NMI_IO_APIC)
887 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
889 printk(KERN_WARNING "APIC timer registered as dummy,"
890 " due to nmi_watchdog=1!\n");
896 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
897 * C1E flag only in the secondary CPU, so when we detect the wreckage
898 * we already have enabled the boot CPU local apic timer. Check, if
899 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
900 * set the DUMMY flag again and force the broadcast mode in the
903 void __cpuinit check_boot_apic_timer_broadcast(void)
905 if (!disable_apic_timer ||
906 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
909 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
910 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
913 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id);
917 void __cpuinit setup_secondary_APIC_clock(void)
919 check_boot_apic_timer_broadcast();
923 int setup_profiling_timer(unsigned int multiplier)
928 void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
929 unsigned char msg_type, unsigned char mask)
931 unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;
932 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
937 * Local timer interrupt handler. It does both profiling and
938 * process statistics/rescheduling.
940 * We do profiling in every local tick, statistics/rescheduling
941 * happen only every 'profiling multiplier' ticks. The default
942 * multiplier is 1 and it can be changed by writing the new multiplier
943 * value into /proc/profile.
946 void smp_local_timer_interrupt(void)
948 int cpu = smp_processor_id();
949 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
952 * Normally we should not be here till LAPIC has been initialized but
953 * in some cases like kdump, its possible that there is a pending LAPIC
954 * timer interrupt from previous kernel's context and is delivered in
955 * new kernel the moment interrupts are enabled.
957 * Interrupts are enabled early and LAPIC is setup much later, hence
958 * its possible that when we get here evt->event_handler is NULL.
959 * Check for event_handler being NULL and discard the interrupt as
962 if (!evt->event_handler) {
964 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
966 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
971 * the NMI deadlock-detector uses this.
973 add_pda(apic_timer_irqs, 1);
975 evt->event_handler(evt);
979 * Local APIC timer interrupt. This is the most natural way for doing
980 * local interrupts, but local timer interrupts can be emulated by
981 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
983 * [ if a single-CPU system runs an SMP kernel then we call the local
984 * interrupt as well. Thus we cannot inline the local irq ... ]
986 void smp_apic_timer_interrupt(struct pt_regs *regs)
988 struct pt_regs *old_regs = set_irq_regs(regs);
991 * NOTE! We'd better ACK the irq immediately,
992 * because timer handling can be slow.
996 * update_process_times() expects us to have done irq_enter().
997 * Besides, if we don't timer interrupts ignore the global
998 * interrupt lock, which is the WrongThing (tm) to do.
1002 smp_local_timer_interrupt();
1004 set_irq_regs(old_regs);
1008 * apic_is_clustered_box() -- Check if we can expect good TSC
1010 * Thus far, the major user of this is IBM's Summit2 series:
1012 * Clustered boxes may have unsynced TSC problems if they are
1013 * multi-chassis. Use available data to take a good guess.
1014 * If in doubt, go HPET.
1016 __cpuinit int apic_is_clustered_box(void)
1018 int i, clusters, zeros;
1020 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1022 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1024 for (i = 0; i < NR_CPUS; i++) {
1025 id = bios_cpu_apicid[i];
1026 if (id != BAD_APICID)
1027 __set_bit(APIC_CLUSTERID(id), clustermap);
1030 /* Problem: Partially populated chassis may not have CPUs in some of
1031 * the APIC clusters they have been allocated. Only present CPUs have
1032 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1033 * clusters are allocated sequentially, count zeros only if they are
1038 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1039 if (test_bit(i, clustermap)) {
1040 clusters += 1 + zeros;
1047 * If clusters > 2, then should be multi-chassis.
1048 * May have to revisit this when multi-core + hyperthreaded CPUs come
1049 * out, but AFAIK this will work even for them.
1051 return (clusters > 2);
1055 * This interrupt should _never_ happen with our APIC/SMP architecture
1057 asmlinkage void smp_spurious_interrupt(void)
1063 * Check if this really is a spurious interrupt and ACK it
1064 * if it is a vectored one. Just in case...
1065 * Spurious interrupts should not be ACKed.
1067 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1068 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1071 add_pda(irq_spurious_count, 1);
1076 * This interrupt should never happen with our APIC/SMP architecture
1079 asmlinkage void smp_error_interrupt(void)
1085 /* First tickle the hardware, only then report what went on. -- REW */
1086 v = apic_read(APIC_ESR);
1087 apic_write(APIC_ESR, 0);
1088 v1 = apic_read(APIC_ESR);
1090 atomic_inc(&irq_err_count);
1092 /* Here is what the APIC error bits mean:
1095 2: Send accept error
1096 3: Receive accept error
1098 5: Send illegal vector
1099 6: Received illegal vector
1100 7: Illegal register address
1102 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1103 smp_processor_id(), v , v1);
1110 * This initializes the IO-APIC and APIC hardware if this is
1113 int __init APIC_init_uniprocessor (void)
1116 printk(KERN_INFO "Apic disabled\n");
1119 if (!cpu_has_apic) {
1121 printk(KERN_INFO "Apic disabled by BIOS\n");
1125 verify_local_APIC();
1127 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
1128 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
1132 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1136 setup_boot_APIC_clock();
1137 check_nmi_watchdog();
1141 static __init int setup_disableapic(char *str)
1144 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1147 early_param("disableapic", setup_disableapic);
1149 /* same as disableapic, for compatibility */
1150 static __init int setup_nolapic(char *str)
1152 return setup_disableapic(str);
1154 early_param("nolapic", setup_nolapic);
1156 static int __init parse_lapic_timer_c2_ok(char *arg)
1158 local_apic_timer_c2_ok = 1;
1161 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1163 static __init int setup_noapictimer(char *str)
1165 if (str[0] != ' ' && str[0] != 0)
1167 disable_apic_timer = 1;
1170 __setup("noapictimer", setup_noapictimer);
1172 static __init int setup_apicpmtimer(char *s)
1174 apic_calibrate_pmtmr = 1;
1178 __setup("apicpmtimer", setup_apicpmtimer);