arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/proto.h>
  43 #include <asm/mach_apic.h>
  44 #include <asm/acpi.h>
  45 #include <asm/dma.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
  51
  52 #define __apicdebuginit  __init
  53
  54 int sis_apic_bug; /* not actually supported, dummy for compile */
  55
  56 static int no_timer_check;
  57
  58 static int disable_timer_pin_1 __initdata;
  59
  60 int timer_over_8254 __initdata = 1;
  61
  62 /* Where if anywhere is the i8259 connect in external int mode */
  63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  64
  65 static DEFINE_SPINLOCK(ioapic_lock);
  66 DEFINE_SPINLOCK(vector_lock);
  67
  68 /*
  69  * # of IRQ routing registers
  70  */
  71 int nr_ioapic_registers[MAX_IO_APICS];
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         short apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 struct io_apic {
  92         unsigned int index;
  93         unsigned int unused[3];
  94         unsigned int data;
  95 };
  96
  97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
  98 {
  99         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 100                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 101 }
 102
 103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 104 {
 105         struct io_apic __iomem *io_apic = io_apic_base(apic);
 106         writel(reg, &io_apic->index);
 107         return readl(&io_apic->data);
 108 }
 109
 110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 111 {
 112         struct io_apic __iomem *io_apic = io_apic_base(apic);
 113         writel(reg, &io_apic->index);
 114         writel(value, &io_apic->data);
 115 }
 116
 117 /*
 118  * Re-write a value: to be used for read-modify-write
 119  * cycles where the read already set up the index register.
 120  */
 121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 122 {
 123         struct io_apic __iomem *io_apic = io_apic_base(apic);
 124         writel(value, &io_apic->data);
 125 }
 126
 127 /*
 128  * Synchronize the IO-APIC and the CPU by doing
 129  * a dummy read from the IO-APIC
 130  */
 131 static inline void io_apic_sync(unsigned int apic)
 132 {
 133         struct io_apic __iomem *io_apic = io_apic_base(apic);
 134         readl(&io_apic->data);
 135 }
 136
 137 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 138                                                                         \
 139 {                                                                       \
 140         int pin;                                                        \
 141         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 142                                                                         \
 143         BUG_ON(irq >= NR_IRQS);                                         \
 144         for (;;) {                                                      \
 145                 unsigned int reg;                                       \
 146                 pin = entry->pin;                                       \
 147                 if (pin == -1)                                          \
 148                         break;                                          \
 149                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 150                 reg ACTION;                                             \
 151                 io_apic_modify(entry->apic, reg);                       \
 152                 if (!entry->next)                                       \
 153                         break;                                          \
 154                 entry = irq_2_pin + entry->next;                        \
 155         }                                                               \
 156         FINAL;                                                          \
 157 }
 158
 159 union entry_union {
 160         struct { u32 w1, w2; };
 161         struct IO_APIC_route_entry entry;
 162 };
 163
 164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 165 {
 166         union entry_union eu;
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 170         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172         return eu.entry;
 173 }
 174
 175 /*
 176  * When we write a new IO APIC routing entry, we need to write the high
 177  * word first! If the mask bit in the low word is clear, we will enable
 178  * the interrupt, and we need to make sure the entry is fully populated
 179  * before that happens.
 180  */
 181 static void
 182 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 183 {
 184         union entry_union eu;
 185         eu.entry = e;
 186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 187         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 188 }
 189
 190 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 191 {
 192         unsigned long flags;
 193         spin_lock_irqsave(&ioapic_lock, flags);
 194         __ioapic_write_entry(apic, pin, e);
 195         spin_unlock_irqrestore(&ioapic_lock, flags);
 196 }
 197
 198 /*
 199  * When we mask an IO APIC routing entry, we need to write the low
 200  * word first, in order to set the mask bit before we change the
 201  * high bits!
 202  */
 203 static void ioapic_mask_entry(int apic, int pin)
 204 {
 205         unsigned long flags;
 206         union entry_union eu = { .entry.mask = 1 };
 207
 208         spin_lock_irqsave(&ioapic_lock, flags);
 209         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 210         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 211         spin_unlock_irqrestore(&ioapic_lock, flags);
 212 }
 213
 214 #ifdef CONFIG_SMP
 215 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 216 {
 217         int apic, pin;
 218         struct irq_pin_list *entry = irq_2_pin + irq;
 219
 220         BUG_ON(irq >= NR_IRQS);
 221         for (;;) {
 222                 unsigned int reg;
 223                 apic = entry->apic;
 224                 pin = entry->pin;
 225                 if (pin == -1)
 226                         break;
 227                 io_apic_write(apic, 0x11 + pin*2, dest);
 228                 reg = io_apic_read(apic, 0x10 + pin*2);
 229                 reg &= ~0x000000ff;
 230                 reg |= vector;
 231                 io_apic_modify(apic, reg);
 232                 if (!entry->next)
 233                         break;
 234                 entry = irq_2_pin + entry->next;
 235         }
 236 }
 237
 238 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 239 {
 240         unsigned long flags;
 241         unsigned int dest;
 242         cpumask_t tmp;
 243         int vector;
 244
 245         cpus_and(tmp, mask, cpu_online_map);
 246         if (cpus_empty(tmp))
 247                 tmp = TARGET_CPUS;
 248
 249         cpus_and(mask, tmp, CPU_MASK_ALL);
 250
 251         vector = assign_irq_vector(irq, mask, &tmp);
 252         if (vector < 0)
 253                 return;
 254
 255         dest = cpu_mask_to_apicid(tmp);
 256
 257         /*
 258          * Only the high 8 bits are valid.
 259          */
 260         dest = SET_APIC_LOGICAL_ID(dest);
 261
 262         spin_lock_irqsave(&ioapic_lock, flags);
 263         __target_IO_APIC_irq(irq, dest, vector);
 264         irq_desc[irq].affinity = mask;
 265         spin_unlock_irqrestore(&ioapic_lock, flags);
 266 }
 267 #endif
 268
 269 /*
 270  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 271  * shared ISA-space IRQs, so we have to support them. We are super
 272  * fast in the common case, and fast for shared ISA-space IRQs.
 273  */
 274 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 275 {
 276         static int first_free_entry = NR_IRQS;
 277         struct irq_pin_list *entry = irq_2_pin + irq;
 278
 279         BUG_ON(irq >= NR_IRQS);
 280         while (entry->next)
 281                 entry = irq_2_pin + entry->next;
 282
 283         if (entry->pin != -1) {
 284                 entry->next = first_free_entry;
 285                 entry = irq_2_pin + entry->next;
 286                 if (++first_free_entry >= PIN_MAP_SIZE)
 287                         panic("io_apic.c: ran out of irq_2_pin entries!");
 288         }
 289         entry->apic = apic;
 290         entry->pin = pin;
 291 }
 292
 293
 294 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 295                                                                         \
 296         static void name##_IO_APIC_irq (unsigned int irq)               \
 297         __DO_ACTION(R, ACTION, FINAL)
 298
 299 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 300                                                 /* mask = 1 */
 301 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 302                                                 /* mask = 0 */
 303
 304 static void mask_IO_APIC_irq (unsigned int irq)
 305 {
 306         unsigned long flags;
 307
 308         spin_lock_irqsave(&ioapic_lock, flags);
 309         __mask_IO_APIC_irq(irq);
 310         spin_unlock_irqrestore(&ioapic_lock, flags);
 311 }
 312
 313 static void unmask_IO_APIC_irq (unsigned int irq)
 314 {
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&ioapic_lock, flags);
 318         __unmask_IO_APIC_irq(irq);
 319         spin_unlock_irqrestore(&ioapic_lock, flags);
 320 }
 321
 322 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 323 {
 324         struct IO_APIC_route_entry entry;
 325
 326         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 327         entry = ioapic_read_entry(apic, pin);
 328         if (entry.delivery_mode == dest_SMI)
 329                 return;
 330         /*
 331          * Disable it in the IO-APIC irq-routing table:
 332          */
 333         ioapic_mask_entry(apic, pin);
 334 }
 335
 336 static void clear_IO_APIC (void)
 337 {
 338         int apic, pin;
 339
 340         for (apic = 0; apic < nr_ioapics; apic++)
 341                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 342                         clear_IO_APIC_pin(apic, pin);
 343 }
 344
 345 int skip_ioapic_setup;
 346 int ioapic_force;
 347
 348 /* dummy parsing: see setup.c */
 349
 350 static int __init disable_ioapic_setup(char *str)
 351 {
 352         skip_ioapic_setup = 1;
 353         return 0;
 354 }
 355 early_param("noapic", disable_ioapic_setup);
 356
 357 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 358 static int __init disable_timer_pin_setup(char *arg)
 359 {
 360         disable_timer_pin_1 = 1;
 361         return 1;
 362 }
 363 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 364
 365 static int __init setup_disable_8254_timer(char *s)
 366 {
 367         timer_over_8254 = -1;
 368         return 1;
 369 }
 370 static int __init setup_enable_8254_timer(char *s)
 371 {
 372         timer_over_8254 = 2;
 373         return 1;
 374 }
 375
 376 __setup("disable_8254_timer", setup_disable_8254_timer);
 377 __setup("enable_8254_timer", setup_enable_8254_timer);
 378
 379
 380 /*
 381  * Find the IRQ entry number of a certain pin.
 382  */
 383 static int find_irq_entry(int apic, int pin, int type)
 384 {
 385         int i;
 386
 387         for (i = 0; i < mp_irq_entries; i++)
 388                 if (mp_irqs[i].mpc_irqtype == type &&
 389                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 390                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 391                     mp_irqs[i].mpc_dstirq == pin)
 392                         return i;
 393
 394         return -1;
 395 }
 396
 397 /*
 398  * Find the pin to which IRQ[irq] (ISA) is connected
 399  */
 400 static int __init find_isa_irq_pin(int irq, int type)
 401 {
 402         int i;
 403
 404         for (i = 0; i < mp_irq_entries; i++) {
 405                 int lbus = mp_irqs[i].mpc_srcbus;
 406
 407                 if (test_bit(lbus, mp_bus_not_pci) &&
 408                     (mp_irqs[i].mpc_irqtype == type) &&
 409                     (mp_irqs[i].mpc_srcbusirq == irq))
 410
 411                         return mp_irqs[i].mpc_dstirq;
 412         }
 413         return -1;
 414 }
 415
 416 static int __init find_isa_irq_apic(int irq, int type)
 417 {
 418         int i;
 419
 420         for (i = 0; i < mp_irq_entries; i++) {
 421                 int lbus = mp_irqs[i].mpc_srcbus;
 422
 423                 if (test_bit(lbus, mp_bus_not_pci) &&
 424                     (mp_irqs[i].mpc_irqtype == type) &&
 425                     (mp_irqs[i].mpc_srcbusirq == irq))
 426                         break;
 427         }
 428         if (i < mp_irq_entries) {
 429                 int apic;
 430                 for(apic = 0; apic < nr_ioapics; apic++) {
 431                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 432                                 return apic;
 433                 }
 434         }
 435
 436         return -1;
 437 }
 438
 439 /*
 440  * Find a specific PCI IRQ entry.
 441  * Not an __init, possibly needed by modules
 442  */
 443 static int pin_2_irq(int idx, int apic, int pin);
 444
 445 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 446 {
 447         int apic, i, best_guess = -1;
 448
 449         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 450                 bus, slot, pin);
 451         if (mp_bus_id_to_pci_bus[bus] == -1) {
 452                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 453                 return -1;
 454         }
 455         for (i = 0; i < mp_irq_entries; i++) {
 456                 int lbus = mp_irqs[i].mpc_srcbus;
 457
 458                 for (apic = 0; apic < nr_ioapics; apic++)
 459                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 460                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 461                                 break;
 462
 463                 if (!test_bit(lbus, mp_bus_not_pci) &&
 464                     !mp_irqs[i].mpc_irqtype &&
 465                     (bus == lbus) &&
 466                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 467                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 468
 469                         if (!(apic || IO_APIC_IRQ(irq)))
 470                                 continue;
 471
 472                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 473                                 return irq;
 474                         /*
 475                          * Use the first all-but-pin matching entry as a
 476                          * best-guess fuzzy result for broken mptables.
 477                          */
 478                         if (best_guess < 0)
 479                                 best_guess = irq;
 480                 }
 481         }
 482         BUG_ON(best_guess >= NR_IRQS);
 483         return best_guess;
 484 }
 485
 486 /* ISA interrupts are always polarity zero edge triggered,
 487  * when listed as conforming in the MP table. */
 488
 489 #define default_ISA_trigger(idx)        (0)
 490 #define default_ISA_polarity(idx)       (0)
 491
 492 /* PCI interrupts are always polarity one level triggered,
 493  * when listed as conforming in the MP table. */
 494
 495 #define default_PCI_trigger(idx)        (1)
 496 #define default_PCI_polarity(idx)       (1)
 497
 498 static int __init MPBIOS_polarity(int idx)
 499 {
 500         int bus = mp_irqs[idx].mpc_srcbus;
 501         int polarity;
 502
 503         /*
 504          * Determine IRQ line polarity (high active or low active):
 505          */
 506         switch (mp_irqs[idx].mpc_irqflag & 3)
 507         {
 508                 case 0: /* conforms, ie. bus-type dependent polarity */
 509                         if (test_bit(bus, mp_bus_not_pci))
 510                                 polarity = default_ISA_polarity(idx);
 511                         else
 512                                 polarity = default_PCI_polarity(idx);
 513                         break;
 514                 case 1: /* high active */
 515                 {
 516                         polarity = 0;
 517                         break;
 518                 }
 519                 case 2: /* reserved */
 520                 {
 521                         printk(KERN_WARNING "broken BIOS!!\n");
 522                         polarity = 1;
 523                         break;
 524                 }
 525                 case 3: /* low active */
 526                 {
 527                         polarity = 1;
 528                         break;
 529                 }
 530                 default: /* invalid */
 531                 {
 532                         printk(KERN_WARNING "broken BIOS!!\n");
 533                         polarity = 1;
 534                         break;
 535                 }
 536         }
 537         return polarity;
 538 }
 539
 540 static int MPBIOS_trigger(int idx)
 541 {
 542         int bus = mp_irqs[idx].mpc_srcbus;
 543         int trigger;
 544
 545         /*
 546          * Determine IRQ trigger mode (edge or level sensitive):
 547          */
 548         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 549         {
 550                 case 0: /* conforms, ie. bus-type dependent */
 551                         if (test_bit(bus, mp_bus_not_pci))
 552                                 trigger = default_ISA_trigger(idx);
 553                         else
 554                                 trigger = default_PCI_trigger(idx);
 555                         break;
 556                 case 1: /* edge */
 557                 {
 558                         trigger = 0;
 559                         break;
 560                 }
 561                 case 2: /* reserved */
 562                 {
 563                         printk(KERN_WARNING "broken BIOS!!\n");
 564                         trigger = 1;
 565                         break;
 566                 }
 567                 case 3: /* level */
 568                 {
 569                         trigger = 1;
 570                         break;
 571                 }
 572                 default: /* invalid */
 573                 {
 574                         printk(KERN_WARNING "broken BIOS!!\n");
 575                         trigger = 0;
 576                         break;
 577                 }
 578         }
 579         return trigger;
 580 }
 581
 582 static inline int irq_polarity(int idx)
 583 {
 584         return MPBIOS_polarity(idx);
 585 }
 586
 587 static inline int irq_trigger(int idx)
 588 {
 589         return MPBIOS_trigger(idx);
 590 }
 591
 592 static int pin_2_irq(int idx, int apic, int pin)
 593 {
 594         int irq, i;
 595         int bus = mp_irqs[idx].mpc_srcbus;
 596
 597         /*
 598          * Debugging check, we are in big trouble if this message pops up!
 599          */
 600         if (mp_irqs[idx].mpc_dstirq != pin)
 601                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 602
 603         if (test_bit(bus, mp_bus_not_pci)) {
 604                 irq = mp_irqs[idx].mpc_srcbusirq;
 605         } else {
 606                 /*
 607                  * PCI IRQs are mapped in order
 608                  */
 609                 i = irq = 0;
 610                 while (i < apic)
 611                         irq += nr_ioapic_registers[i++];
 612                 irq += pin;
 613         }
 614         BUG_ON(irq >= NR_IRQS);
 615         return irq;
 616 }
 617
 618
 619 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 620 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
 621         [0] = FIRST_EXTERNAL_VECTOR + 0,
 622         [1] = FIRST_EXTERNAL_VECTOR + 1,
 623         [2] = FIRST_EXTERNAL_VECTOR + 2,
 624         [3] = FIRST_EXTERNAL_VECTOR + 3,
 625         [4] = FIRST_EXTERNAL_VECTOR + 4,
 626         [5] = FIRST_EXTERNAL_VECTOR + 5,
 627         [6] = FIRST_EXTERNAL_VECTOR + 6,
 628         [7] = FIRST_EXTERNAL_VECTOR + 7,
 629         [8] = FIRST_EXTERNAL_VECTOR + 8,
 630         [9] = FIRST_EXTERNAL_VECTOR + 9,
 631         [10] = FIRST_EXTERNAL_VECTOR + 10,
 632         [11] = FIRST_EXTERNAL_VECTOR + 11,
 633         [12] = FIRST_EXTERNAL_VECTOR + 12,
 634         [13] = FIRST_EXTERNAL_VECTOR + 13,
 635         [14] = FIRST_EXTERNAL_VECTOR + 14,
 636         [15] = FIRST_EXTERNAL_VECTOR + 15,
 637 };
 638
 639 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
 640         [0] = CPU_MASK_ALL,
 641         [1] = CPU_MASK_ALL,
 642         [2] = CPU_MASK_ALL,
 643         [3] = CPU_MASK_ALL,
 644         [4] = CPU_MASK_ALL,
 645         [5] = CPU_MASK_ALL,
 646         [6] = CPU_MASK_ALL,
 647         [7] = CPU_MASK_ALL,
 648         [8] = CPU_MASK_ALL,
 649         [9] = CPU_MASK_ALL,
 650         [10] = CPU_MASK_ALL,
 651         [11] = CPU_MASK_ALL,
 652         [12] = CPU_MASK_ALL,
 653         [13] = CPU_MASK_ALL,
 654         [14] = CPU_MASK_ALL,
 655         [15] = CPU_MASK_ALL,
 656 };
 657
 658 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 659 {
 660         /*
 661          * NOTE! The local APIC isn't very good at handling
 662          * multiple interrupts at the same interrupt level.
 663          * As the interrupt level is determined by taking the
 664          * vector number and shifting that right by 4, we
 665          * want to spread these out a bit so that they don't
 666          * all fall in the same interrupt level.
 667          *
 668          * Also, we've got to be careful not to trash gate
 669          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 670          */
 671         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 672         cpumask_t old_mask = CPU_MASK_NONE;
 673         int old_vector = -1;
 674         int cpu;
 675
 676         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
 677
 678         /* Only try and allocate irqs on cpus that are present */
 679         cpus_and(mask, mask, cpu_online_map);
 680
 681         if (irq_vector[irq] > 0)
 682                 old_vector = irq_vector[irq];
 683         if (old_vector > 0) {
 684                 cpus_and(*result, irq_domain[irq], mask);
 685                 if (!cpus_empty(*result))
 686                         return old_vector;
 687                 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
 688         }
 689
 690         for_each_cpu_mask(cpu, mask) {
 691                 cpumask_t domain, new_mask;
 692                 int new_cpu, old_cpu;
 693                 int vector, offset;
 694
 695                 domain = vector_allocation_domain(cpu);
 696                 cpus_and(new_mask, domain, cpu_online_map);
 697
 698                 vector = current_vector;
 699                 offset = current_offset;
 700 next:
 701                 vector += 8;
 702                 if (vector >= FIRST_SYSTEM_VECTOR) {
 703                         /* If we run out of vectors on large boxen, must share them. */
 704                         offset = (offset + 1) % 8;
 705                         vector = FIRST_DEVICE_VECTOR + offset;
 706                 }
 707                 if (unlikely(current_vector == vector))
 708                         continue;
 709                 if (vector == IA32_SYSCALL_VECTOR)
 710                         goto next;
 711                 for_each_cpu_mask(new_cpu, new_mask)
 712                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 713                                 goto next;
 714                 /* Found one! */
 715                 current_vector = vector;
 716                 current_offset = offset;
 717                 for_each_cpu_mask(old_cpu, old_mask)
 718                         per_cpu(vector_irq, old_cpu)[old_vector] = -1;
 719                 for_each_cpu_mask(new_cpu, new_mask)
 720                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 721                 irq_vector[irq] = vector;
 722                 irq_domain[irq] = domain;
 723                 cpus_and(*result, domain, mask);
 724                 return vector;
 725         }
 726         return -ENOSPC;
 727 }
 728
 729 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 730 {
 731         int vector;
 732         unsigned long flags;
 733
 734         spin_lock_irqsave(&vector_lock, flags);
 735         vector = __assign_irq_vector(irq, mask, result);
 736         spin_unlock_irqrestore(&vector_lock, flags);
 737         return vector;
 738 }
 739
 740 static void __clear_irq_vector(int irq)
 741 {
 742         cpumask_t mask;
 743         int cpu, vector;
 744
 745         BUG_ON(!irq_vector[irq]);
 746
 747         vector = irq_vector[irq];
 748         cpus_and(mask, irq_domain[irq], cpu_online_map);
 749         for_each_cpu_mask(cpu, mask)
 750                 per_cpu(vector_irq, cpu)[vector] = -1;
 751
 752         irq_vector[irq] = 0;
 753         irq_domain[irq] = CPU_MASK_NONE;
 754 }
 755
 756 void __setup_vector_irq(int cpu)
 757 {
 758         /* Initialize vector_irq on a new cpu */
 759         /* This function must be called with vector_lock held */
 760         int irq, vector;
 761
 762         /* Mark the inuse vectors */
 763         for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
 764                 if (!cpu_isset(cpu, irq_domain[irq]))
 765                         continue;
 766                 vector = irq_vector[irq];
 767                 per_cpu(vector_irq, cpu)[vector] = irq;
 768         }
 769         /* Mark the free vectors */
 770         for (vector = 0; vector < NR_VECTORS; ++vector) {
 771                 irq = per_cpu(vector_irq, cpu)[vector];
 772                 if (irq < 0)
 773                         continue;
 774                 if (!cpu_isset(cpu, irq_domain[irq]))
 775                         per_cpu(vector_irq, cpu)[vector] = -1;
 776         }
 777 }
 778
 779
 780 static struct irq_chip ioapic_chip;
 781
 782 static void ioapic_register_intr(int irq, unsigned long trigger)
 783 {
 784         if (trigger)
 785                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 786                                               handle_fasteoi_irq, "fasteoi");
 787         else
 788                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 789                                               handle_edge_irq, "edge");
 790 }
 791
 792 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
 793                               int trigger, int polarity)
 794 {
 795         struct IO_APIC_route_entry entry;
 796         cpumask_t mask;
 797         int vector;
 798         unsigned long flags;
 799
 800         if (!IO_APIC_IRQ(irq))
 801                 return;
 802
 803         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
 804         if (vector < 0)
 805                 return;
 806
 807         apic_printk(APIC_VERBOSE,KERN_DEBUG
 808                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
 809                     "IRQ %d Mode:%i Active:%i)\n",
 810                     apic, mp_ioapics[apic].mpc_apicid, pin, vector,
 811                     irq, trigger, polarity);
 812
 813         /*
 814          * add it to the IO-APIC irq-routing table:
 815          */
 816         memset(&entry,0,sizeof(entry));
 817
 818         entry.delivery_mode = INT_DELIVERY_MODE;
 819         entry.dest_mode = INT_DEST_MODE;
 820         entry.dest = cpu_mask_to_apicid(mask);
 821         entry.mask = 0;                         /* enable IRQ */
 822         entry.trigger = trigger;
 823         entry.polarity = polarity;
 824         entry.vector = vector;
 825
 826         /* Mask level triggered irqs.
 827          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
 828          */
 829         if (trigger)
 830                 entry.mask = 1;
 831
 832         ioapic_register_intr(irq, trigger);
 833         if (irq < 16)
 834                 disable_8259A_irq(irq);
 835
 836         ioapic_write_entry(apic, pin, entry);
 837
 838         spin_lock_irqsave(&ioapic_lock, flags);
 839         irq_desc[irq].affinity = TARGET_CPUS;
 840         spin_unlock_irqrestore(&ioapic_lock, flags);
 841 }
 842
 843 static void __init setup_IO_APIC_irqs(void)
 844 {
 845         int apic, pin, idx, irq, first_notcon = 1;
 846
 847         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 848
 849         for (apic = 0; apic < nr_ioapics; apic++) {
 850         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 851
 852                 idx = find_irq_entry(apic,pin,mp_INT);
 853                 if (idx == -1) {
 854                         if (first_notcon) {
 855                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 856                                 first_notcon = 0;
 857                         } else
 858                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 859                         continue;
 860                 }
 861
 862                 irq = pin_2_irq(idx, apic, pin);
 863                 add_pin_to_irq(irq, apic, pin);
 864
 865                 setup_IO_APIC_irq(apic, pin, irq,
 866                                   irq_trigger(idx), irq_polarity(idx));
 867         }
 868         }
 869
 870         if (!first_notcon)
 871                 apic_printk(APIC_VERBOSE," not connected.\n");
 872 }
 873
 874 /*
 875  * Set up the 8259A-master output pin as broadcast to all
 876  * CPUs.
 877  */
 878 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 879 {
 880         struct IO_APIC_route_entry entry;
 881         unsigned long flags;
 882
 883         memset(&entry,0,sizeof(entry));
 884
 885         disable_8259A_irq(0);
 886
 887         /* mask LVT0 */
 888         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 889
 890         /*
 891          * We use logical delivery to get the timer IRQ
 892          * to the first CPU.
 893          */
 894         entry.dest_mode = INT_DEST_MODE;
 895         entry.mask = 0;                                 /* unmask IRQ now */
 896         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
 897         entry.delivery_mode = INT_DELIVERY_MODE;
 898         entry.polarity = 0;
 899         entry.trigger = 0;
 900         entry.vector = vector;
 901
 902         /*
 903          * The timer IRQ doesn't have to know that behind the
 904          * scene we have a 8259A-master in AEOI mode ...
 905          */
 906         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 907
 908         /*
 909          * Add it to the IO-APIC irq-routing table:
 910          */
 911         spin_lock_irqsave(&ioapic_lock, flags);
 912         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 913         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 914         spin_unlock_irqrestore(&ioapic_lock, flags);
 915
 916         enable_8259A_irq(0);
 917 }
 918
 919 void __init UNEXPECTED_IO_APIC(void)
 920 {
 921 }
 922
 923 void __apicdebuginit print_IO_APIC(void)
 924 {
 925         int apic, i;
 926         union IO_APIC_reg_00 reg_00;
 927         union IO_APIC_reg_01 reg_01;
 928         union IO_APIC_reg_02 reg_02;
 929         unsigned long flags;
 930
 931         if (apic_verbosity == APIC_QUIET)
 932                 return;
 933
 934         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 935         for (i = 0; i < nr_ioapics; i++)
 936                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 937                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 938
 939         /*
 940          * We are a bit conservative about what we expect.  We have to
 941          * know about every hardware change ASAP.
 942          */
 943         printk(KERN_INFO "testing the IO APIC.......................\n");
 944
 945         for (apic = 0; apic < nr_ioapics; apic++) {
 946
 947         spin_lock_irqsave(&ioapic_lock, flags);
 948         reg_00.raw = io_apic_read(apic, 0);
 949         reg_01.raw = io_apic_read(apic, 1);
 950         if (reg_01.bits.version >= 0x10)
 951                 reg_02.raw = io_apic_read(apic, 2);
 952         spin_unlock_irqrestore(&ioapic_lock, flags);
 953
 954         printk("\n");
 955         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 956         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 957         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 958         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 959                 UNEXPECTED_IO_APIC();
 960
 961         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 962         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 963         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 964                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 965                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 966                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 967                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 968                 (reg_01.bits.entries != 0x2E) &&
 969                 (reg_01.bits.entries != 0x3F) &&
 970                 (reg_01.bits.entries != 0x03)
 971         )
 972                 UNEXPECTED_IO_APIC();
 973
 974         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 975         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 976         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 977                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 978                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 979                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 980                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 981                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 982         )
 983                 UNEXPECTED_IO_APIC();
 984         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 985                 UNEXPECTED_IO_APIC();
 986
 987         if (reg_01.bits.version >= 0x10) {
 988                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 989                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 990                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 991                         UNEXPECTED_IO_APIC();
 992         }
 993
 994         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 995
 996         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
 997                           " Stat Dmod Deli Vect:   \n");
 998
 999         for (i = 0; i <= reg_01.bits.entries; i++) {
1000                 struct IO_APIC_route_entry entry;
1001
1002                 entry = ioapic_read_entry(apic, i);
1003
1004                 printk(KERN_DEBUG " %02x %03X ",
1005                         i,
1006                         entry.dest
1007                 );
1008
1009                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1010                         entry.mask,
1011                         entry.trigger,
1012                         entry.irr,
1013                         entry.polarity,
1014                         entry.delivery_status,
1015                         entry.dest_mode,
1016                         entry.delivery_mode,
1017                         entry.vector
1018                 );
1019         }
1020         }
1021         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1022         for (i = 0; i < NR_IRQS; i++) {
1023                 struct irq_pin_list *entry = irq_2_pin + i;
1024                 if (entry->pin < 0)
1025                         continue;
1026                 printk(KERN_DEBUG "IRQ%d ", i);
1027                 for (;;) {
1028                         printk("-> %d:%d", entry->apic, entry->pin);
1029                         if (!entry->next)
1030                                 break;
1031                         entry = irq_2_pin + entry->next;
1032                 }
1033                 printk("\n");
1034         }
1035
1036         printk(KERN_INFO ".................................... done.\n");
1037
1038         return;
1039 }
1040
1041 #if 0
1042
1043 static __apicdebuginit void print_APIC_bitfield (int base)
1044 {
1045         unsigned int v;
1046         int i, j;
1047
1048         if (apic_verbosity == APIC_QUIET)
1049                 return;
1050
1051         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1052         for (i = 0; i < 8; i++) {
1053                 v = apic_read(base + i*0x10);
1054                 for (j = 0; j < 32; j++) {
1055                         if (v & (1<<j))
1056                                 printk("1");
1057                         else
1058                                 printk("0");
1059                 }
1060                 printk("\n");
1061         }
1062 }
1063
1064 void __apicdebuginit print_local_APIC(void * dummy)
1065 {
1066         unsigned int v, ver, maxlvt;
1067
1068         if (apic_verbosity == APIC_QUIET)
1069                 return;
1070
1071         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1072                 smp_processor_id(), hard_smp_processor_id());
1073         v = apic_read(APIC_ID);
1074         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1075         v = apic_read(APIC_LVR);
1076         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1077         ver = GET_APIC_VERSION(v);
1078         maxlvt = get_maxlvt();
1079
1080         v = apic_read(APIC_TASKPRI);
1081         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1082
1083         v = apic_read(APIC_ARBPRI);
1084         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1085                 v & APIC_ARBPRI_MASK);
1086         v = apic_read(APIC_PROCPRI);
1087         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1088
1089         v = apic_read(APIC_EOI);
1090         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1091         v = apic_read(APIC_RRR);
1092         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1093         v = apic_read(APIC_LDR);
1094         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1095         v = apic_read(APIC_DFR);
1096         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1097         v = apic_read(APIC_SPIV);
1098         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1099
1100         printk(KERN_DEBUG "... APIC ISR field:\n");
1101         print_APIC_bitfield(APIC_ISR);
1102         printk(KERN_DEBUG "... APIC TMR field:\n");
1103         print_APIC_bitfield(APIC_TMR);
1104         printk(KERN_DEBUG "... APIC IRR field:\n");
1105         print_APIC_bitfield(APIC_IRR);
1106
1107         v = apic_read(APIC_ESR);
1108         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1109
1110         v = apic_read(APIC_ICR);
1111         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1112         v = apic_read(APIC_ICR2);
1113         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1114
1115         v = apic_read(APIC_LVTT);
1116         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1117
1118         if (maxlvt > 3) {                       /* PC is LVT#4. */
1119                 v = apic_read(APIC_LVTPC);
1120                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1121         }
1122         v = apic_read(APIC_LVT0);
1123         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1124         v = apic_read(APIC_LVT1);
1125         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1126
1127         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1128                 v = apic_read(APIC_LVTERR);
1129                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1130         }
1131
1132         v = apic_read(APIC_TMICT);
1133         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1134         v = apic_read(APIC_TMCCT);
1135         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1136         v = apic_read(APIC_TDCR);
1137         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1138         printk("\n");
1139 }
1140
1141 void print_all_local_APICs (void)
1142 {
1143         on_each_cpu(print_local_APIC, NULL, 1, 1);
1144 }
1145
1146 void __apicdebuginit print_PIC(void)
1147 {
1148         unsigned int v;
1149         unsigned long flags;
1150
1151         if (apic_verbosity == APIC_QUIET)
1152                 return;
1153
1154         printk(KERN_DEBUG "\nprinting PIC contents\n");
1155
1156         spin_lock_irqsave(&i8259A_lock, flags);
1157
1158         v = inb(0xa1) << 8 | inb(0x21);
1159         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1160
1161         v = inb(0xa0) << 8 | inb(0x20);
1162         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1163
1164         outb(0x0b,0xa0);
1165         outb(0x0b,0x20);
1166         v = inb(0xa0) << 8 | inb(0x20);
1167         outb(0x0a,0xa0);
1168         outb(0x0a,0x20);
1169
1170         spin_unlock_irqrestore(&i8259A_lock, flags);
1171
1172         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1173
1174         v = inb(0x4d1) << 8 | inb(0x4d0);
1175         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1176 }
1177
1178 #endif  /*  0  */
1179
1180 static void __init enable_IO_APIC(void)
1181 {
1182         union IO_APIC_reg_01 reg_01;
1183         int i8259_apic, i8259_pin;
1184         int i, apic;
1185         unsigned long flags;
1186
1187         for (i = 0; i < PIN_MAP_SIZE; i++) {
1188                 irq_2_pin[i].pin = -1;
1189                 irq_2_pin[i].next = 0;
1190         }
1191
1192         /*
1193          * The number of IO-APIC IRQ registers (== #pins):
1194          */
1195         for (apic = 0; apic < nr_ioapics; apic++) {
1196                 spin_lock_irqsave(&ioapic_lock, flags);
1197                 reg_01.raw = io_apic_read(apic, 1);
1198                 spin_unlock_irqrestore(&ioapic_lock, flags);
1199                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1200         }
1201         for(apic = 0; apic < nr_ioapics; apic++) {
1202                 int pin;
1203                 /* See if any of the pins is in ExtINT mode */
1204                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1205                         struct IO_APIC_route_entry entry;
1206                         entry = ioapic_read_entry(apic, pin);
1207
1208                         /* If the interrupt line is enabled and in ExtInt mode
1209                          * I have found the pin where the i8259 is connected.
1210                          */
1211                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1212                                 ioapic_i8259.apic = apic;
1213                                 ioapic_i8259.pin  = pin;
1214                                 goto found_i8259;
1215                         }
1216                 }
1217         }
1218  found_i8259:
1219         /* Look to see what if the MP table has reported the ExtINT */
1220         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1221         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1222         /* Trust the MP table if nothing is setup in the hardware */
1223         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1224                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1225                 ioapic_i8259.pin  = i8259_pin;
1226                 ioapic_i8259.apic = i8259_apic;
1227         }
1228         /* Complain if the MP table and the hardware disagree */
1229         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1230                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1231         {
1232                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1233         }
1234
1235         /*
1236          * Do not trust the IO-APIC being empty at bootup
1237          */
1238         clear_IO_APIC();
1239 }
1240
1241 /*
1242  * Not an __init, needed by the reboot code
1243  */
1244 void disable_IO_APIC(void)
1245 {
1246         /*
1247          * Clear the IO-APIC before rebooting:
1248          */
1249         clear_IO_APIC();
1250
1251         /*
1252          * If the i8259 is routed through an IOAPIC
1253          * Put that IOAPIC in virtual wire mode
1254          * so legacy interrupts can be delivered.
1255          */
1256         if (ioapic_i8259.pin != -1) {
1257                 struct IO_APIC_route_entry entry;
1258
1259                 memset(&entry, 0, sizeof(entry));
1260                 entry.mask            = 0; /* Enabled */
1261                 entry.trigger         = 0; /* Edge */
1262                 entry.irr             = 0;
1263                 entry.polarity        = 0; /* High */
1264                 entry.delivery_status = 0;
1265                 entry.dest_mode       = 0; /* Physical */
1266                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1267                 entry.vector          = 0;
1268                 entry.dest          = GET_APIC_ID(apic_read(APIC_ID));
1269
1270                 /*
1271                  * Add it to the IO-APIC irq-routing table:
1272                  */
1273                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1274         }
1275
1276         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1277 }
1278
1279 /*
1280  * There is a nasty bug in some older SMP boards, their mptable lies
1281  * about the timer IRQ. We do the following to work around the situation:
1282  *
1283  *      - timer IRQ defaults to IO-APIC IRQ
1284  *      - if this function detects that timer IRQs are defunct, then we fall
1285  *        back to ISA timer IRQs
1286  */
1287 static int __init timer_irq_works(void)
1288 {
1289         unsigned long t1 = jiffies;
1290
1291         local_irq_enable();
1292         /* Let ten ticks pass... */
1293         mdelay((10 * 1000) / HZ);
1294
1295         /*
1296          * Expect a few ticks at least, to be sure some possible
1297          * glue logic does not lock up after one or two first
1298          * ticks in a non-ExtINT mode.  Also the local APIC
1299          * might have cached one ExtINT interrupt.  Finally, at
1300          * least one tick may be lost due to delays.
1301          */
1302
1303         /* jiffies wrap? */
1304         if (jiffies - t1 > 4)
1305                 return 1;
1306         return 0;
1307 }
1308
1309 /*
1310  * In the SMP+IOAPIC case it might happen that there are an unspecified
1311  * number of pending IRQ events unhandled. These cases are very rare,
1312  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1313  * better to do it this way as thus we do not have to be aware of
1314  * 'pending' interrupts in the IRQ path, except at this point.
1315  */
1316 /*
1317  * Edge triggered needs to resend any interrupt
1318  * that was delayed but this is now handled in the device
1319  * independent code.
1320  */
1321
1322 /*
1323  * Starting up a edge-triggered IO-APIC interrupt is
1324  * nasty - we need to make sure that we get the edge.
1325  * If it is already asserted for some reason, we need
1326  * return 1 to indicate that is was pending.
1327  *
1328  * This is not complete - we should be able to fake
1329  * an edge even if it isn't on the 8259A...
1330  */
1331
1332 static unsigned int startup_ioapic_irq(unsigned int irq)
1333 {
1334         int was_pending = 0;
1335         unsigned long flags;
1336
1337         spin_lock_irqsave(&ioapic_lock, flags);
1338         if (irq < 16) {
1339                 disable_8259A_irq(irq);
1340                 if (i8259A_irq_pending(irq))
1341                         was_pending = 1;
1342         }
1343         __unmask_IO_APIC_irq(irq);
1344         spin_unlock_irqrestore(&ioapic_lock, flags);
1345
1346         return was_pending;
1347 }
1348
1349 static int ioapic_retrigger_irq(unsigned int irq)
1350 {
1351         cpumask_t mask;
1352         unsigned vector;
1353         unsigned long flags;
1354
1355         spin_lock_irqsave(&vector_lock, flags);
1356         vector = irq_vector[irq];
1357         cpus_clear(mask);
1358         cpu_set(first_cpu(irq_domain[irq]), mask);
1359
1360         send_IPI_mask(mask, vector);
1361         spin_unlock_irqrestore(&vector_lock, flags);
1362
1363         return 1;
1364 }
1365
1366 /*
1367  * Level and edge triggered IO-APIC interrupts need different handling,
1368  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1369  * handled with the level-triggered descriptor, but that one has slightly
1370  * more overhead. Level-triggered interrupts cannot be handled with the
1371  * edge-triggered handler, without risking IRQ storms and other ugly
1372  * races.
1373  */
1374
1375 static void ack_apic_edge(unsigned int irq)
1376 {
1377         move_native_irq(irq);
1378         ack_APIC_irq();
1379 }
1380
1381 static void ack_apic_level(unsigned int irq)
1382 {
1383         int do_unmask_irq = 0;
1384
1385 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1386         /* If we are moving the irq we need to mask it */
1387         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1388                 do_unmask_irq = 1;
1389                 mask_IO_APIC_irq(irq);
1390         }
1391 #endif
1392
1393         /*
1394          * We must acknowledge the irq before we move it or the acknowledge will
1395          * not propogate properly.
1396          */
1397         ack_APIC_irq();
1398
1399         /* Now we can move and renable the irq */
1400         move_masked_irq(irq);
1401         if (unlikely(do_unmask_irq))
1402                 unmask_IO_APIC_irq(irq);
1403 }
1404
1405 static struct irq_chip ioapic_chip __read_mostly = {
1406         .name           = "IO-APIC",
1407         .startup        = startup_ioapic_irq,
1408         .mask           = mask_IO_APIC_irq,
1409         .unmask         = unmask_IO_APIC_irq,
1410         .ack            = ack_apic_edge,
1411         .eoi            = ack_apic_level,
1412 #ifdef CONFIG_SMP
1413         .set_affinity   = set_ioapic_affinity_irq,
1414 #endif
1415         .retrigger      = ioapic_retrigger_irq,
1416 };
1417
1418 static inline void init_IO_APIC_traps(void)
1419 {
1420         int irq;
1421
1422         /*
1423          * NOTE! The local APIC isn't very good at handling
1424          * multiple interrupts at the same interrupt level.
1425          * As the interrupt level is determined by taking the
1426          * vector number and shifting that right by 4, we
1427          * want to spread these out a bit so that they don't
1428          * all fall in the same interrupt level.
1429          *
1430          * Also, we've got to be careful not to trash gate
1431          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1432          */
1433         for (irq = 0; irq < NR_IRQS ; irq++) {
1434                 int tmp = irq;
1435                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1436                         /*
1437                          * Hmm.. We don't have an entry for this,
1438                          * so default to an old-fashioned 8259
1439                          * interrupt if we can..
1440                          */
1441                         if (irq < 16)
1442                                 make_8259A_irq(irq);
1443                         else
1444                                 /* Strange. Oh, well.. */
1445                                 irq_desc[irq].chip = &no_irq_chip;
1446                 }
1447         }
1448 }
1449
1450 static void enable_lapic_irq (unsigned int irq)
1451 {
1452         unsigned long v;
1453
1454         v = apic_read(APIC_LVT0);
1455         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1456 }
1457
1458 static void disable_lapic_irq (unsigned int irq)
1459 {
1460         unsigned long v;
1461
1462         v = apic_read(APIC_LVT0);
1463         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1464 }
1465
1466 static void ack_lapic_irq (unsigned int irq)
1467 {
1468         ack_APIC_irq();
1469 }
1470
1471 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1472
1473 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1474         .typename = "local-APIC-edge",
1475         .startup = NULL, /* startup_irq() not used for IRQ0 */
1476         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1477         .enable = enable_lapic_irq,
1478         .disable = disable_lapic_irq,
1479         .ack = ack_lapic_irq,
1480         .end = end_lapic_irq,
1481 };
1482
1483 static void setup_nmi (void)
1484 {
1485         /*
1486          * Dirty trick to enable the NMI watchdog ...
1487          * We put the 8259A master into AEOI mode and
1488          * unmask on all local APICs LVT0 as NMI.
1489          *
1490          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1491          * is from Maciej W. Rozycki - so we do not have to EOI from
1492          * the NMI handler or the timer interrupt.
1493          */
1494         printk(KERN_INFO "activating NMI Watchdog ...");
1495
1496         enable_NMI_through_LVT0(NULL);
1497
1498         printk(" done.\n");
1499 }
1500
1501 /*
1502  * This looks a bit hackish but it's about the only one way of sending
1503  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1504  * not support the ExtINT mode, unfortunately.  We need to send these
1505  * cycles as some i82489DX-based boards have glue logic that keeps the
1506  * 8259A interrupt line asserted until INTA.  --macro
1507  */
1508 static inline void unlock_ExtINT_logic(void)
1509 {
1510         int apic, pin, i;
1511         struct IO_APIC_route_entry entry0, entry1;
1512         unsigned char save_control, save_freq_select;
1513         unsigned long flags;
1514
1515         pin  = find_isa_irq_pin(8, mp_INT);
1516         apic = find_isa_irq_apic(8, mp_INT);
1517         if (pin == -1)
1518                 return;
1519
1520         spin_lock_irqsave(&ioapic_lock, flags);
1521         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1522         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1523         spin_unlock_irqrestore(&ioapic_lock, flags);
1524         clear_IO_APIC_pin(apic, pin);
1525
1526         memset(&entry1, 0, sizeof(entry1));
1527
1528         entry1.dest_mode = 0;                   /* physical delivery */
1529         entry1.mask = 0;                        /* unmask IRQ now */
1530         entry1.dest = hard_smp_processor_id();
1531         entry1.delivery_mode = dest_ExtINT;
1532         entry1.polarity = entry0.polarity;
1533         entry1.trigger = 0;
1534         entry1.vector = 0;
1535
1536         spin_lock_irqsave(&ioapic_lock, flags);
1537         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1538         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1539         spin_unlock_irqrestore(&ioapic_lock, flags);
1540
1541         save_control = CMOS_READ(RTC_CONTROL);
1542         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1543         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1544                    RTC_FREQ_SELECT);
1545         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1546
1547         i = 100;
1548         while (i-- > 0) {
1549                 mdelay(10);
1550                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1551                         i -= 10;
1552         }
1553
1554         CMOS_WRITE(save_control, RTC_CONTROL);
1555         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1556         clear_IO_APIC_pin(apic, pin);
1557
1558         spin_lock_irqsave(&ioapic_lock, flags);
1559         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1560         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1561         spin_unlock_irqrestore(&ioapic_lock, flags);
1562 }
1563
1564 /*
1565  * This code may look a bit paranoid, but it's supposed to cooperate with
1566  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1567  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1568  * fanatically on his truly buggy board.
1569  *
1570  * FIXME: really need to revamp this for modern platforms only.
1571  */
1572 static inline void check_timer(void)
1573 {
1574         int apic1, pin1, apic2, pin2;
1575         int vector;
1576         cpumask_t mask;
1577
1578         /*
1579          * get/set the timer IRQ vector:
1580          */
1581         disable_8259A_irq(0);
1582         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1583
1584         /*
1585          * Subtle, code in do_timer_interrupt() expects an AEOI
1586          * mode for the 8259A whenever interrupts are routed
1587          * through I/O APICs.  Also IRQ0 has to be enabled in
1588          * the 8259A which implies the virtual wire has to be
1589          * disabled in the local APIC.
1590          */
1591         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1592         init_8259A(1);
1593         if (timer_over_8254 > 0)
1594                 enable_8259A_irq(0);
1595
1596         pin1  = find_isa_irq_pin(0, mp_INT);
1597         apic1 = find_isa_irq_apic(0, mp_INT);
1598         pin2  = ioapic_i8259.pin;
1599         apic2 = ioapic_i8259.apic;
1600
1601         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1602                 vector, apic1, pin1, apic2, pin2);
1603
1604         if (pin1 != -1) {
1605                 /*
1606                  * Ok, does IRQ0 through the IOAPIC work?
1607                  */
1608                 unmask_IO_APIC_irq(0);
1609                 if (!no_timer_check && timer_irq_works()) {
1610                         nmi_watchdog_default();
1611                         if (nmi_watchdog == NMI_IO_APIC) {
1612                                 disable_8259A_irq(0);
1613                                 setup_nmi();
1614                                 enable_8259A_irq(0);
1615                         }
1616                         if (disable_timer_pin_1 > 0)
1617                                 clear_IO_APIC_pin(0, pin1);
1618                         return;
1619                 }
1620                 clear_IO_APIC_pin(apic1, pin1);
1621                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1622                                 "connected to IO-APIC\n");
1623         }
1624
1625         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1626                                 "through the 8259A ... ");
1627         if (pin2 != -1) {
1628                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1629                         apic2, pin2);
1630                 /*
1631                  * legacy devices should be connected to IO APIC #0
1632                  */
1633                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1634                 if (timer_irq_works()) {
1635                         apic_printk(APIC_VERBOSE," works.\n");
1636                         nmi_watchdog_default();
1637                         if (nmi_watchdog == NMI_IO_APIC) {
1638                                 setup_nmi();
1639                         }
1640                         return;
1641                 }
1642                 /*
1643                  * Cleanup, just in case ...
1644                  */
1645                 clear_IO_APIC_pin(apic2, pin2);
1646         }
1647         apic_printk(APIC_VERBOSE," failed.\n");
1648
1649         if (nmi_watchdog == NMI_IO_APIC) {
1650                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1651                 nmi_watchdog = 0;
1652         }
1653
1654         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1655
1656         disable_8259A_irq(0);
1657         irq_desc[0].chip = &lapic_irq_type;
1658         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1659         enable_8259A_irq(0);
1660
1661         if (timer_irq_works()) {
1662                 apic_printk(APIC_VERBOSE," works.\n");
1663                 return;
1664         }
1665         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1666         apic_printk(APIC_VERBOSE," failed.\n");
1667
1668         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1669
1670         init_8259A(0);
1671         make_8259A_irq(0);
1672         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1673
1674         unlock_ExtINT_logic();
1675
1676         if (timer_irq_works()) {
1677                 apic_printk(APIC_VERBOSE," works.\n");
1678                 return;
1679         }
1680         apic_printk(APIC_VERBOSE," failed :(.\n");
1681         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1682 }
1683
1684 static int __init notimercheck(char *s)
1685 {
1686         no_timer_check = 1;
1687         return 1;
1688 }
1689 __setup("no_timer_check", notimercheck);
1690
1691 /*
1692  *
1693  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1694  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1695  *   Linux doesn't really care, as it's not actually used
1696  *   for any interrupt handling anyway.
1697  */
1698 #define PIC_IRQS        (1<<2)
1699
1700 void __init setup_IO_APIC(void)
1701 {
1702         enable_IO_APIC();
1703
1704         if (acpi_ioapic)
1705                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1706         else
1707                 io_apic_irqs = ~PIC_IRQS;
1708
1709         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1710
1711         sync_Arb_IDs();
1712         setup_IO_APIC_irqs();
1713         init_IO_APIC_traps();
1714         check_timer();
1715         if (!acpi_ioapic)
1716                 print_IO_APIC();
1717 }
1718
1719 struct sysfs_ioapic_data {
1720         struct sys_device dev;
1721         struct IO_APIC_route_entry entry[0];
1722 };
1723 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1724
1725 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1726 {
1727         struct IO_APIC_route_entry *entry;
1728         struct sysfs_ioapic_data *data;
1729         int i;
1730
1731         data = container_of(dev, struct sysfs_ioapic_data, dev);
1732         entry = data->entry;
1733         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1734                 *entry = ioapic_read_entry(dev->id, i);
1735
1736         return 0;
1737 }
1738
1739 static int ioapic_resume(struct sys_device *dev)
1740 {
1741         struct IO_APIC_route_entry *entry;
1742         struct sysfs_ioapic_data *data;
1743         unsigned long flags;
1744         union IO_APIC_reg_00 reg_00;
1745         int i;
1746
1747         data = container_of(dev, struct sysfs_ioapic_data, dev);
1748         entry = data->entry;
1749
1750         spin_lock_irqsave(&ioapic_lock, flags);
1751         reg_00.raw = io_apic_read(dev->id, 0);
1752         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1753                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1754                 io_apic_write(dev->id, 0, reg_00.raw);
1755         }
1756         spin_unlock_irqrestore(&ioapic_lock, flags);
1757         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1758                 ioapic_write_entry(dev->id, i, entry[i]);
1759
1760         return 0;
1761 }
1762
1763 static struct sysdev_class ioapic_sysdev_class = {
1764         set_kset_name("ioapic"),
1765         .suspend = ioapic_suspend,
1766         .resume = ioapic_resume,
1767 };
1768
1769 static int __init ioapic_init_sysfs(void)
1770 {
1771         struct sys_device * dev;
1772         int i, size, error = 0;
1773
1774         error = sysdev_class_register(&ioapic_sysdev_class);
1775         if (error)
1776                 return error;
1777
1778         for (i = 0; i < nr_ioapics; i++ ) {
1779                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1780                         * sizeof(struct IO_APIC_route_entry);
1781                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1782                 if (!mp_ioapic_data[i]) {
1783                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1784                         continue;
1785                 }
1786                 memset(mp_ioapic_data[i], 0, size);
1787                 dev = &mp_ioapic_data[i]->dev;
1788                 dev->id = i;
1789                 dev->cls = &ioapic_sysdev_class;
1790                 error = sysdev_register(dev);
1791                 if (error) {
1792                         kfree(mp_ioapic_data[i]);
1793                         mp_ioapic_data[i] = NULL;
1794                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1795                         continue;
1796                 }
1797         }
1798
1799         return 0;
1800 }
1801
1802 device_initcall(ioapic_init_sysfs);
1803
1804 /*
1805  * Dynamic irq allocate and deallocation
1806  */
1807 int create_irq(void)
1808 {
1809         /* Allocate an unused irq */
1810         int irq;
1811         int new;
1812         int vector = 0;
1813         unsigned long flags;
1814         cpumask_t mask;
1815
1816         irq = -ENOSPC;
1817         spin_lock_irqsave(&vector_lock, flags);
1818         for (new = (NR_IRQS - 1); new >= 0; new--) {
1819                 if (platform_legacy_irq(new))
1820                         continue;
1821                 if (irq_vector[new] != 0)
1822                         continue;
1823                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1824                 if (likely(vector > 0))
1825                         irq = new;
1826                 break;
1827         }
1828         spin_unlock_irqrestore(&vector_lock, flags);
1829
1830         if (irq >= 0) {
1831                 dynamic_irq_init(irq);
1832         }
1833         return irq;
1834 }
1835
1836 void destroy_irq(unsigned int irq)
1837 {
1838         unsigned long flags;
1839
1840         dynamic_irq_cleanup(irq);
1841
1842         spin_lock_irqsave(&vector_lock, flags);
1843         __clear_irq_vector(irq);
1844         spin_unlock_irqrestore(&vector_lock, flags);
1845 }
1846
1847 /*
1848  * MSI mesage composition
1849  */
1850 #ifdef CONFIG_PCI_MSI
1851 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1852 {
1853         int vector;
1854         unsigned dest;
1855         cpumask_t tmp;
1856
1857         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1858         if (vector >= 0) {
1859                 dest = cpu_mask_to_apicid(tmp);
1860
1861                 msg->address_hi = MSI_ADDR_BASE_HI;
1862                 msg->address_lo =
1863                         MSI_ADDR_BASE_LO |
1864                         ((INT_DEST_MODE == 0) ?
1865                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1866                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1867                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1868                                 MSI_ADDR_REDIRECTION_CPU:
1869                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1870                         MSI_ADDR_DEST_ID(dest);
1871
1872                 msg->data =
1873                         MSI_DATA_TRIGGER_EDGE |
1874                         MSI_DATA_LEVEL_ASSERT |
1875                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1876                                 MSI_DATA_DELIVERY_FIXED:
1877                                 MSI_DATA_DELIVERY_LOWPRI) |
1878                         MSI_DATA_VECTOR(vector);
1879         }
1880         return vector;
1881 }
1882
1883 #ifdef CONFIG_SMP
1884 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1885 {
1886         struct msi_msg msg;
1887         unsigned int dest;
1888         cpumask_t tmp;
1889         int vector;
1890
1891         cpus_and(tmp, mask, cpu_online_map);
1892         if (cpus_empty(tmp))
1893                 tmp = TARGET_CPUS;
1894
1895         cpus_and(mask, tmp, CPU_MASK_ALL);
1896
1897         vector = assign_irq_vector(irq, mask, &tmp);
1898         if (vector < 0)
1899                 return;
1900
1901         dest = cpu_mask_to_apicid(tmp);
1902
1903         read_msi_msg(irq, &msg);
1904
1905         msg.data &= ~MSI_DATA_VECTOR_MASK;
1906         msg.data |= MSI_DATA_VECTOR(vector);
1907         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1908         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1909
1910         write_msi_msg(irq, &msg);
1911         irq_desc[irq].affinity = mask;
1912 }
1913 #endif /* CONFIG_SMP */
1914
1915 /*
1916  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1917  * which implement the MSI or MSI-X Capability Structure.
1918  */
1919 static struct irq_chip msi_chip = {
1920         .name           = "PCI-MSI",
1921         .unmask         = unmask_msi_irq,
1922         .mask           = mask_msi_irq,
1923         .ack            = ack_apic_edge,
1924 #ifdef CONFIG_SMP
1925         .set_affinity   = set_msi_irq_affinity,
1926 #endif
1927         .retrigger      = ioapic_retrigger_irq,
1928 };
1929
1930 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1931 {
1932         struct msi_msg msg;
1933         int irq, ret;
1934         irq = create_irq();
1935         if (irq < 0)
1936                 return irq;
1937
1938         set_irq_msi(irq, desc);
1939         ret = msi_compose_msg(dev, irq, &msg);
1940         if (ret < 0) {
1941                 destroy_irq(irq);
1942                 return ret;
1943         }
1944
1945         write_msi_msg(irq, &msg);
1946
1947         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1948
1949         return irq;
1950 }
1951
1952 void arch_teardown_msi_irq(unsigned int irq)
1953 {
1954         destroy_irq(irq);
1955 }
1956
1957 #endif /* CONFIG_PCI_MSI */
1958
1959 /*
1960  * Hypertransport interrupt support
1961  */
1962 #ifdef CONFIG_HT_IRQ
1963
1964 #ifdef CONFIG_SMP
1965
1966 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1967 {
1968         struct ht_irq_msg msg;
1969         fetch_ht_irq_msg(irq, &msg);
1970
1971         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1972         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1973
1974         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1975         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1976
1977         write_ht_irq_msg(irq, &msg);
1978 }
1979
1980 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1981 {
1982         unsigned int dest;
1983         cpumask_t tmp;
1984         int vector;
1985
1986         cpus_and(tmp, mask, cpu_online_map);
1987         if (cpus_empty(tmp))
1988                 tmp = TARGET_CPUS;
1989
1990         cpus_and(mask, tmp, CPU_MASK_ALL);
1991
1992         vector = assign_irq_vector(irq, mask, &tmp);
1993         if (vector < 0)
1994                 return;
1995
1996         dest = cpu_mask_to_apicid(tmp);
1997
1998         target_ht_irq(irq, dest, vector);
1999         irq_desc[irq].affinity = mask;
2000 }
2001 #endif
2002
2003 static struct irq_chip ht_irq_chip = {
2004         .name           = "PCI-HT",
2005         .mask           = mask_ht_irq,
2006         .unmask         = unmask_ht_irq,
2007         .ack            = ack_apic_edge,
2008 #ifdef CONFIG_SMP
2009         .set_affinity   = set_ht_irq_affinity,
2010 #endif
2011         .retrigger      = ioapic_retrigger_irq,
2012 };
2013
2014 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2015 {
2016         int vector;
2017         cpumask_t tmp;
2018
2019         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2020         if (vector >= 0) {
2021                 struct ht_irq_msg msg;
2022                 unsigned dest;
2023
2024                 dest = cpu_mask_to_apicid(tmp);
2025
2026                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2027
2028                 msg.address_lo =
2029                         HT_IRQ_LOW_BASE |
2030                         HT_IRQ_LOW_DEST_ID(dest) |
2031                         HT_IRQ_LOW_VECTOR(vector) |
2032                         ((INT_DEST_MODE == 0) ?
2033                                 HT_IRQ_LOW_DM_PHYSICAL :
2034                                 HT_IRQ_LOW_DM_LOGICAL) |
2035                         HT_IRQ_LOW_RQEOI_EDGE |
2036                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2037                                 HT_IRQ_LOW_MT_FIXED :
2038                                 HT_IRQ_LOW_MT_ARBITRATED) |
2039                         HT_IRQ_LOW_IRQ_MASKED;
2040
2041                 write_ht_irq_msg(irq, &msg);
2042
2043                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2044                                               handle_edge_irq, "edge");
2045         }
2046         return vector;
2047 }
2048 #endif /* CONFIG_HT_IRQ */
2049
2050 /* --------------------------------------------------------------------------
2051                           ACPI-based IOAPIC Configuration
2052    -------------------------------------------------------------------------- */
2053
2054 #ifdef CONFIG_ACPI
2055
2056 #define IO_APIC_MAX_ID          0xFE
2057
2058 int __init io_apic_get_redir_entries (int ioapic)
2059 {
2060         union IO_APIC_reg_01    reg_01;
2061         unsigned long flags;
2062
2063         spin_lock_irqsave(&ioapic_lock, flags);
2064         reg_01.raw = io_apic_read(ioapic, 1);
2065         spin_unlock_irqrestore(&ioapic_lock, flags);
2066
2067         return reg_01.bits.entries;
2068 }
2069
2070
2071 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2072 {
2073         if (!IO_APIC_IRQ(irq)) {
2074                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2075                         ioapic);
2076                 return -EINVAL;
2077         }
2078
2079         /*
2080          * IRQs < 16 are already in the irq_2_pin[] map
2081          */
2082         if (irq >= 16)
2083                 add_pin_to_irq(irq, ioapic, pin);
2084
2085         setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2086
2087         return 0;
2088 }
2089
2090 #endif /* CONFIG_ACPI */
2091
2092
2093 /*
2094  * This function currently is only a helper for the i386 smp boot process where
2095  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2096  * so mask in all cases should simply be TARGET_CPUS
2097  */
2098 #ifdef CONFIG_SMP
2099 void __init setup_ioapic_dest(void)
2100 {
2101         int pin, ioapic, irq, irq_entry;
2102
2103         if (skip_ioapic_setup == 1)
2104                 return;
2105
2106         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2107                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2108                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2109                         if (irq_entry == -1)
2110                                 continue;
2111                         irq = pin_2_irq(irq_entry, ioapic, pin);
2112
2113                         /* setup_IO_APIC_irqs could fail to get vector for some device
2114                          * when you have too many devices, because at that time only boot
2115                          * cpu is online.
2116                          */
2117                         if(!irq_vector[irq])
2118                                 setup_IO_APIC_irq(ioapic, pin, irq,
2119                                                   irq_trigger(irq_entry),
2120                                                   irq_polarity(irq_entry));
2121                         else
2122                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2123                 }
2124
2125         }
2126 }
2127 #endif