2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
33 #include <acpi/acpi_bus.h>
39 #include <asm/proto.h>
40 #include <asm/mach_apic.h>
45 #define __apicdebuginit __init
47 int sis_apic_bug; /* not actually supported, dummy for compile */
49 static int no_timer_check;
51 int disable_timer_pin_1 __initdata;
53 int timer_over_8254 __initdata = 0;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
62 * # of IRQ routing registers
64 int nr_ioapic_registers[MAX_IO_APICS];
67 * Rough estimation of how many shared IRQs there are, can
70 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
71 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
74 * This is performance-critical, we want to do it O(1)
76 * the indexing order of this array favors 1:1 mappings
77 * between pins and IRQs.
80 static struct irq_pin_list {
81 short apic, pin, next;
82 } irq_2_pin[PIN_MAP_SIZE];
84 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
86 #define vector_to_irq(vector) \
87 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
89 #define vector_to_irq(vector) (vector)
92 #define __DO_ACTION(R, ACTION, FINAL) \
96 struct irq_pin_list *entry = irq_2_pin + irq; \
98 BUG_ON(irq >= NR_IRQS); \
104 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
106 io_apic_modify(entry->apic, reg); \
109 entry = irq_2_pin + entry->next; \
115 struct { u32 w1, w2; };
116 struct IO_APIC_route_entry entry;
119 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
121 union entry_union eu;
123 spin_lock_irqsave(&ioapic_lock, flags);
124 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
125 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
126 spin_unlock_irqrestore(&ioapic_lock, flags);
130 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
133 union entry_union eu;
135 spin_lock_irqsave(&ioapic_lock, flags);
136 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
137 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
138 spin_unlock_irqrestore(&ioapic_lock, flags);
142 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
148 cpus_and(tmp, mask, cpu_online_map);
152 cpus_and(mask, tmp, CPU_MASK_ALL);
154 dest = cpu_mask_to_apicid(mask);
157 * Only the high 8 bits are valid.
159 dest = SET_APIC_LOGICAL_ID(dest);
161 spin_lock_irqsave(&ioapic_lock, flags);
162 __DO_ACTION(1, = dest, )
163 set_irq_info(irq, mask);
164 spin_unlock_irqrestore(&ioapic_lock, flags);
168 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
171 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
172 * shared ISA-space IRQs, so we have to support them. We are super
173 * fast in the common case, and fast for shared ISA-space IRQs.
175 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
177 static int first_free_entry = NR_IRQS;
178 struct irq_pin_list *entry = irq_2_pin + irq;
180 BUG_ON(irq >= NR_IRQS);
182 entry = irq_2_pin + entry->next;
184 if (entry->pin != -1) {
185 entry->next = first_free_entry;
186 entry = irq_2_pin + entry->next;
187 if (++first_free_entry >= PIN_MAP_SIZE)
188 panic("io_apic.c: ran out of irq_2_pin entries!");
195 #define DO_ACTION(name,R,ACTION, FINAL) \
197 static void name##_IO_APIC_irq (unsigned int irq) \
198 __DO_ACTION(R, ACTION, FINAL)
200 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
202 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
205 static void mask_IO_APIC_irq (unsigned int irq)
209 spin_lock_irqsave(&ioapic_lock, flags);
210 __mask_IO_APIC_irq(irq);
211 spin_unlock_irqrestore(&ioapic_lock, flags);
214 static void unmask_IO_APIC_irq (unsigned int irq)
218 spin_lock_irqsave(&ioapic_lock, flags);
219 __unmask_IO_APIC_irq(irq);
220 spin_unlock_irqrestore(&ioapic_lock, flags);
223 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
225 struct IO_APIC_route_entry entry;
227 /* Check delivery_mode to be sure we're not clearing an SMI pin */
228 entry = ioapic_read_entry(apic, pin);
229 if (entry.delivery_mode == dest_SMI)
232 * Disable it in the IO-APIC irq-routing table:
234 memset(&entry, 0, sizeof(entry));
236 ioapic_write_entry(apic, pin, entry);
239 static void clear_IO_APIC (void)
243 for (apic = 0; apic < nr_ioapics; apic++)
244 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
245 clear_IO_APIC_pin(apic, pin);
248 int skip_ioapic_setup;
251 /* dummy parsing: see setup.c */
253 static int __init disable_ioapic_setup(char *str)
255 skip_ioapic_setup = 1;
259 static int __init enable_ioapic_setup(char *str)
262 skip_ioapic_setup = 0;
266 __setup("noapic", disable_ioapic_setup);
267 __setup("apic", enable_ioapic_setup);
269 static int __init setup_disable_8254_timer(char *s)
271 timer_over_8254 = -1;
274 static int __init setup_enable_8254_timer(char *s)
280 __setup("disable_8254_timer", setup_disable_8254_timer);
281 __setup("enable_8254_timer", setup_enable_8254_timer);
283 #include <asm/pci-direct.h>
284 #include <linux/pci_ids.h>
285 #include <linux/pci.h>
290 static int nvidia_hpet_detected __initdata;
292 static int __init nvidia_hpet_check(unsigned long phys, unsigned long size)
294 nvidia_hpet_detected = 1;
299 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
300 off. Check for an Nvidia or VIA PCI bridge and turn it off.
301 Use pci direct infrastructure because this runs before the PCI subsystem.
303 Can be overwritten with "apic"
305 And another hack to disable the IOMMU on VIA chipsets.
307 ... and others. Really should move this somewhere else.
310 void __init check_ioapic(void)
313 /* Poor man's PCI discovery */
314 for (num = 0; num < 32; num++) {
315 for (slot = 0; slot < 32; slot++) {
316 for (func = 0; func < 8; func++) {
320 class = read_pci_config(num,slot,func,
322 if (class == 0xffffffff)
325 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
328 vendor = read_pci_config(num, slot, func,
332 case PCI_VENDOR_ID_VIA:
334 if ((end_pfn > MAX_DMA32_PFN ||
336 !iommu_aperture_allowed) {
338 "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
339 iommu_aperture_disabled = 1;
343 case PCI_VENDOR_ID_NVIDIA:
346 * All timer overrides on Nvidia are
347 * wrong unless HPET is enabled.
349 nvidia_hpet_detected = 0;
350 acpi_table_parse(ACPI_HPET,
352 if (nvidia_hpet_detected == 0) {
353 acpi_skip_timer_override = 1;
354 printk(KERN_INFO "Nvidia board "
355 "detected. Ignoring ACPI "
356 "timer override.\n");
359 /* RED-PEN skip them on mptables too? */
362 /* This should be actually default, but
363 for 2.6.16 let's do it for ATI only where
364 it's really needed. */
365 case PCI_VENDOR_ID_ATI:
366 if (timer_over_8254 == 1) {
369 "ATI board detected. Disabling timer routing over 8254.\n");
375 /* No multi-function device? */
376 type = read_pci_config_byte(num,slot,func,
386 * Find the IRQ entry number of a certain pin.
388 static int find_irq_entry(int apic, int pin, int type)
392 for (i = 0; i < mp_irq_entries; i++)
393 if (mp_irqs[i].mpc_irqtype == type &&
394 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
395 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
396 mp_irqs[i].mpc_dstirq == pin)
403 * Find the pin to which IRQ[irq] (ISA) is connected
405 static int __init find_isa_irq_pin(int irq, int type)
409 for (i = 0; i < mp_irq_entries; i++) {
410 int lbus = mp_irqs[i].mpc_srcbus;
412 if (mp_bus_id_to_type[lbus] == MP_BUS_ISA &&
413 (mp_irqs[i].mpc_irqtype == type) &&
414 (mp_irqs[i].mpc_srcbusirq == irq))
416 return mp_irqs[i].mpc_dstirq;
421 static int __init find_isa_irq_apic(int irq, int type)
425 for (i = 0; i < mp_irq_entries; i++) {
426 int lbus = mp_irqs[i].mpc_srcbus;
428 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA) &&
429 (mp_irqs[i].mpc_irqtype == type) &&
430 (mp_irqs[i].mpc_srcbusirq == irq))
433 if (i < mp_irq_entries) {
435 for(apic = 0; apic < nr_ioapics; apic++) {
436 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
445 * Find a specific PCI IRQ entry.
446 * Not an __init, possibly needed by modules
448 static int pin_2_irq(int idx, int apic, int pin);
450 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
452 int apic, i, best_guess = -1;
454 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
456 if (mp_bus_id_to_pci_bus[bus] == -1) {
457 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
460 for (i = 0; i < mp_irq_entries; i++) {
461 int lbus = mp_irqs[i].mpc_srcbus;
463 for (apic = 0; apic < nr_ioapics; apic++)
464 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
465 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
468 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
469 !mp_irqs[i].mpc_irqtype &&
471 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
472 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
474 if (!(apic || IO_APIC_IRQ(irq)))
477 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
480 * Use the first all-but-pin matching entry as a
481 * best-guess fuzzy result for broken mptables.
487 BUG_ON(best_guess >= NR_IRQS);
491 /* ISA interrupts are always polarity zero edge triggered,
492 * when listed as conforming in the MP table. */
494 #define default_ISA_trigger(idx) (0)
495 #define default_ISA_polarity(idx) (0)
497 /* PCI interrupts are always polarity one level triggered,
498 * when listed as conforming in the MP table. */
500 #define default_PCI_trigger(idx) (1)
501 #define default_PCI_polarity(idx) (1)
503 static int __init MPBIOS_polarity(int idx)
505 int bus = mp_irqs[idx].mpc_srcbus;
509 * Determine IRQ line polarity (high active or low active):
511 switch (mp_irqs[idx].mpc_irqflag & 3)
513 case 0: /* conforms, ie. bus-type dependent polarity */
515 switch (mp_bus_id_to_type[bus])
517 case MP_BUS_ISA: /* ISA pin */
519 polarity = default_ISA_polarity(idx);
522 case MP_BUS_PCI: /* PCI pin */
524 polarity = default_PCI_polarity(idx);
529 printk(KERN_WARNING "broken BIOS!!\n");
536 case 1: /* high active */
541 case 2: /* reserved */
543 printk(KERN_WARNING "broken BIOS!!\n");
547 case 3: /* low active */
552 default: /* invalid */
554 printk(KERN_WARNING "broken BIOS!!\n");
562 static int MPBIOS_trigger(int idx)
564 int bus = mp_irqs[idx].mpc_srcbus;
568 * Determine IRQ trigger mode (edge or level sensitive):
570 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
572 case 0: /* conforms, ie. bus-type dependent */
574 switch (mp_bus_id_to_type[bus])
576 case MP_BUS_ISA: /* ISA pin */
578 trigger = default_ISA_trigger(idx);
581 case MP_BUS_PCI: /* PCI pin */
583 trigger = default_PCI_trigger(idx);
588 printk(KERN_WARNING "broken BIOS!!\n");
600 case 2: /* reserved */
602 printk(KERN_WARNING "broken BIOS!!\n");
611 default: /* invalid */
613 printk(KERN_WARNING "broken BIOS!!\n");
621 static inline int irq_polarity(int idx)
623 return MPBIOS_polarity(idx);
626 static inline int irq_trigger(int idx)
628 return MPBIOS_trigger(idx);
631 static int next_irq = 16;
634 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
635 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
636 * from ACPI, which can reach 800 in large boxen.
638 * Compact the sparse GSI space into a sequential IRQ series and reuse
639 * vectors if possible.
641 int gsi_irq_sharing(int gsi)
643 int i, tries, vector;
645 BUG_ON(gsi >= NR_IRQ_VECTORS);
647 if (platform_legacy_irq(gsi))
650 if (gsi_2_irq[gsi] != 0xFF)
651 return (int)gsi_2_irq[gsi];
655 vector = assign_irq_vector(gsi);
658 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
659 * use of vector and if found, return that IRQ. However, we never want
660 * to share legacy IRQs, which usually have a different trigger mode
663 for (i = 0; i < NR_IRQS; i++)
664 if (IO_APIC_VECTOR(i) == vector)
666 if (platform_legacy_irq(i)) {
668 IO_APIC_VECTOR(i) = 0;
671 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
675 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
681 BUG_ON(i >= NR_IRQS);
683 IO_APIC_VECTOR(i) = vector;
684 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
689 static int pin_2_irq(int idx, int apic, int pin)
692 int bus = mp_irqs[idx].mpc_srcbus;
695 * Debugging check, we are in big trouble if this message pops up!
697 if (mp_irqs[idx].mpc_dstirq != pin)
698 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
700 switch (mp_bus_id_to_type[bus])
702 case MP_BUS_ISA: /* ISA pin */
704 irq = mp_irqs[idx].mpc_srcbusirq;
707 case MP_BUS_PCI: /* PCI pin */
710 * PCI IRQs are mapped in order
714 irq += nr_ioapic_registers[i++];
716 irq = gsi_irq_sharing(irq);
721 printk(KERN_ERR "unknown bus type %d.\n",bus);
726 BUG_ON(irq >= NR_IRQS);
730 static inline int IO_APIC_irq_trigger(int irq)
734 for (apic = 0; apic < nr_ioapics; apic++) {
735 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
736 idx = find_irq_entry(apic,pin,mp_INT);
737 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
738 return irq_trigger(idx);
742 * nonexistent IRQs are edge default
747 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
748 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
750 int assign_irq_vector(int irq)
752 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
756 BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
758 spin_lock_irqsave(&vector_lock, flags);
760 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
761 spin_unlock_irqrestore(&vector_lock, flags);
762 return IO_APIC_VECTOR(irq);
766 if (current_vector == IA32_SYSCALL_VECTOR)
769 if (current_vector >= FIRST_SYSTEM_VECTOR) {
770 /* If we run out of vectors on large boxen, must share them. */
771 offset = (offset + 1) % 8;
772 current_vector = FIRST_DEVICE_VECTOR + offset;
775 vector = current_vector;
776 vector_irq[vector] = irq;
777 if (irq != AUTO_ASSIGN)
778 IO_APIC_VECTOR(irq) = vector;
780 spin_unlock_irqrestore(&vector_lock, flags);
785 extern void (*interrupt[NR_IRQS])(void);
786 static struct hw_interrupt_type ioapic_level_type;
787 static struct hw_interrupt_type ioapic_edge_type;
789 #define IOAPIC_AUTO -1
790 #define IOAPIC_EDGE 0
791 #define IOAPIC_LEVEL 1
793 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
797 idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
799 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
800 trigger == IOAPIC_LEVEL)
801 irq_desc[idx].chip = &ioapic_level_type;
803 irq_desc[idx].chip = &ioapic_edge_type;
804 set_intr_gate(vector, interrupt[idx]);
807 static void __init setup_IO_APIC_irqs(void)
809 struct IO_APIC_route_entry entry;
810 int apic, pin, idx, irq, first_notcon = 1, vector;
813 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
815 for (apic = 0; apic < nr_ioapics; apic++) {
816 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
819 * add it to the IO-APIC irq-routing table:
821 memset(&entry,0,sizeof(entry));
823 entry.delivery_mode = INT_DELIVERY_MODE;
824 entry.dest_mode = INT_DEST_MODE;
825 entry.mask = 0; /* enable IRQ */
826 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
828 idx = find_irq_entry(apic,pin,mp_INT);
831 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
834 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
838 entry.trigger = irq_trigger(idx);
839 entry.polarity = irq_polarity(idx);
841 if (irq_trigger(idx)) {
844 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
847 irq = pin_2_irq(idx, apic, pin);
848 add_pin_to_irq(irq, apic, pin);
850 if (!apic && !IO_APIC_IRQ(irq))
853 if (IO_APIC_IRQ(irq)) {
854 vector = assign_irq_vector(irq);
855 entry.vector = vector;
857 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
858 if (!apic && (irq < 16))
859 disable_8259A_irq(irq);
861 ioapic_write_entry(apic, pin, entry);
863 spin_lock_irqsave(&ioapic_lock, flags);
864 set_native_irq_info(irq, TARGET_CPUS);
865 spin_unlock_irqrestore(&ioapic_lock, flags);
870 apic_printk(APIC_VERBOSE," not connected.\n");
874 * Set up the 8259A-master output pin as broadcast to all
877 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
879 struct IO_APIC_route_entry entry;
882 memset(&entry,0,sizeof(entry));
884 disable_8259A_irq(0);
887 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
890 * We use logical delivery to get the timer IRQ
893 entry.dest_mode = INT_DEST_MODE;
894 entry.mask = 0; /* unmask IRQ now */
895 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
896 entry.delivery_mode = INT_DELIVERY_MODE;
899 entry.vector = vector;
902 * The timer IRQ doesn't have to know that behind the
903 * scene we have a 8259A-master in AEOI mode ...
905 irq_desc[0].chip = &ioapic_edge_type;
908 * Add it to the IO-APIC irq-routing table:
910 spin_lock_irqsave(&ioapic_lock, flags);
911 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
912 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
913 spin_unlock_irqrestore(&ioapic_lock, flags);
918 void __init UNEXPECTED_IO_APIC(void)
922 void __apicdebuginit print_IO_APIC(void)
925 union IO_APIC_reg_00 reg_00;
926 union IO_APIC_reg_01 reg_01;
927 union IO_APIC_reg_02 reg_02;
930 if (apic_verbosity == APIC_QUIET)
933 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
934 for (i = 0; i < nr_ioapics; i++)
935 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
936 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
939 * We are a bit conservative about what we expect. We have to
940 * know about every hardware change ASAP.
942 printk(KERN_INFO "testing the IO APIC.......................\n");
944 for (apic = 0; apic < nr_ioapics; apic++) {
946 spin_lock_irqsave(&ioapic_lock, flags);
947 reg_00.raw = io_apic_read(apic, 0);
948 reg_01.raw = io_apic_read(apic, 1);
949 if (reg_01.bits.version >= 0x10)
950 reg_02.raw = io_apic_read(apic, 2);
951 spin_unlock_irqrestore(&ioapic_lock, flags);
954 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
955 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
956 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
957 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
958 UNEXPECTED_IO_APIC();
960 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
961 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
962 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
963 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
964 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
965 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
966 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
967 (reg_01.bits.entries != 0x2E) &&
968 (reg_01.bits.entries != 0x3F) &&
969 (reg_01.bits.entries != 0x03)
971 UNEXPECTED_IO_APIC();
973 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
974 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
975 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
976 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
977 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
978 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
979 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
980 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
982 UNEXPECTED_IO_APIC();
983 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
984 UNEXPECTED_IO_APIC();
986 if (reg_01.bits.version >= 0x10) {
987 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
988 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
989 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
990 UNEXPECTED_IO_APIC();
993 printk(KERN_DEBUG ".... IRQ redirection table:\n");
995 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
996 " Stat Dest Deli Vect: \n");
998 for (i = 0; i <= reg_01.bits.entries; i++) {
999 struct IO_APIC_route_entry entry;
1001 entry = ioapic_read_entry(apic, i);
1003 printk(KERN_DEBUG " %02x %03X %02X ",
1005 entry.dest.logical.logical_dest,
1006 entry.dest.physical.physical_dest
1009 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1014 entry.delivery_status,
1016 entry.delivery_mode,
1021 if (use_pci_vector())
1022 printk(KERN_INFO "Using vector-based indexing\n");
1023 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1024 for (i = 0; i < NR_IRQS; i++) {
1025 struct irq_pin_list *entry = irq_2_pin + i;
1028 if (use_pci_vector() && !platform_legacy_irq(i))
1029 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1031 printk(KERN_DEBUG "IRQ%d ", i);
1033 printk("-> %d:%d", entry->apic, entry->pin);
1036 entry = irq_2_pin + entry->next;
1041 printk(KERN_INFO ".................................... done.\n");
1048 static __apicdebuginit void print_APIC_bitfield (int base)
1053 if (apic_verbosity == APIC_QUIET)
1056 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1057 for (i = 0; i < 8; i++) {
1058 v = apic_read(base + i*0x10);
1059 for (j = 0; j < 32; j++) {
1069 void __apicdebuginit print_local_APIC(void * dummy)
1071 unsigned int v, ver, maxlvt;
1073 if (apic_verbosity == APIC_QUIET)
1076 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1077 smp_processor_id(), hard_smp_processor_id());
1078 v = apic_read(APIC_ID);
1079 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1080 v = apic_read(APIC_LVR);
1081 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1082 ver = GET_APIC_VERSION(v);
1083 maxlvt = get_maxlvt();
1085 v = apic_read(APIC_TASKPRI);
1086 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1088 v = apic_read(APIC_ARBPRI);
1089 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1090 v & APIC_ARBPRI_MASK);
1091 v = apic_read(APIC_PROCPRI);
1092 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1094 v = apic_read(APIC_EOI);
1095 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1096 v = apic_read(APIC_RRR);
1097 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1098 v = apic_read(APIC_LDR);
1099 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1100 v = apic_read(APIC_DFR);
1101 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1102 v = apic_read(APIC_SPIV);
1103 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1105 printk(KERN_DEBUG "... APIC ISR field:\n");
1106 print_APIC_bitfield(APIC_ISR);
1107 printk(KERN_DEBUG "... APIC TMR field:\n");
1108 print_APIC_bitfield(APIC_TMR);
1109 printk(KERN_DEBUG "... APIC IRR field:\n");
1110 print_APIC_bitfield(APIC_IRR);
1112 v = apic_read(APIC_ESR);
1113 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1115 v = apic_read(APIC_ICR);
1116 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1117 v = apic_read(APIC_ICR2);
1118 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1120 v = apic_read(APIC_LVTT);
1121 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1123 if (maxlvt > 3) { /* PC is LVT#4. */
1124 v = apic_read(APIC_LVTPC);
1125 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1127 v = apic_read(APIC_LVT0);
1128 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1129 v = apic_read(APIC_LVT1);
1130 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1132 if (maxlvt > 2) { /* ERR is LVT#3. */
1133 v = apic_read(APIC_LVTERR);
1134 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1137 v = apic_read(APIC_TMICT);
1138 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1139 v = apic_read(APIC_TMCCT);
1140 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1141 v = apic_read(APIC_TDCR);
1142 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1146 void print_all_local_APICs (void)
1148 on_each_cpu(print_local_APIC, NULL, 1, 1);
1151 void __apicdebuginit print_PIC(void)
1154 unsigned long flags;
1156 if (apic_verbosity == APIC_QUIET)
1159 printk(KERN_DEBUG "\nprinting PIC contents\n");
1161 spin_lock_irqsave(&i8259A_lock, flags);
1163 v = inb(0xa1) << 8 | inb(0x21);
1164 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1166 v = inb(0xa0) << 8 | inb(0x20);
1167 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1171 v = inb(0xa0) << 8 | inb(0x20);
1175 spin_unlock_irqrestore(&i8259A_lock, flags);
1177 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1179 v = inb(0x4d1) << 8 | inb(0x4d0);
1180 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1185 static void __init enable_IO_APIC(void)
1187 union IO_APIC_reg_01 reg_01;
1188 int i8259_apic, i8259_pin;
1190 unsigned long flags;
1192 for (i = 0; i < PIN_MAP_SIZE; i++) {
1193 irq_2_pin[i].pin = -1;
1194 irq_2_pin[i].next = 0;
1198 * The number of IO-APIC IRQ registers (== #pins):
1200 for (apic = 0; apic < nr_ioapics; apic++) {
1201 spin_lock_irqsave(&ioapic_lock, flags);
1202 reg_01.raw = io_apic_read(apic, 1);
1203 spin_unlock_irqrestore(&ioapic_lock, flags);
1204 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1206 for(apic = 0; apic < nr_ioapics; apic++) {
1208 /* See if any of the pins is in ExtINT mode */
1209 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1210 struct IO_APIC_route_entry entry;
1211 entry = ioapic_read_entry(apic, pin);
1213 /* If the interrupt line is enabled and in ExtInt mode
1214 * I have found the pin where the i8259 is connected.
1216 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1217 ioapic_i8259.apic = apic;
1218 ioapic_i8259.pin = pin;
1224 /* Look to see what if the MP table has reported the ExtINT */
1225 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1226 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1227 /* Trust the MP table if nothing is setup in the hardware */
1228 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1229 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1230 ioapic_i8259.pin = i8259_pin;
1231 ioapic_i8259.apic = i8259_apic;
1233 /* Complain if the MP table and the hardware disagree */
1234 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1235 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1237 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1241 * Do not trust the IO-APIC being empty at bootup
1247 * Not an __init, needed by the reboot code
1249 void disable_IO_APIC(void)
1252 * Clear the IO-APIC before rebooting:
1257 * If the i8259 is routed through an IOAPIC
1258 * Put that IOAPIC in virtual wire mode
1259 * so legacy interrupts can be delivered.
1261 if (ioapic_i8259.pin != -1) {
1262 struct IO_APIC_route_entry entry;
1264 memset(&entry, 0, sizeof(entry));
1265 entry.mask = 0; /* Enabled */
1266 entry.trigger = 0; /* Edge */
1268 entry.polarity = 0; /* High */
1269 entry.delivery_status = 0;
1270 entry.dest_mode = 0; /* Physical */
1271 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1273 entry.dest.physical.physical_dest =
1274 GET_APIC_ID(apic_read(APIC_ID));
1277 * Add it to the IO-APIC irq-routing table:
1279 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1282 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1286 * function to set the IO-APIC physical IDs based on the
1287 * values stored in the MPC table.
1289 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1292 static void __init setup_ioapic_ids_from_mpc (void)
1294 union IO_APIC_reg_00 reg_00;
1297 unsigned char old_id;
1298 unsigned long flags;
1301 * Set the IOAPIC ID to the value stored in the MPC table.
1303 for (apic = 0; apic < nr_ioapics; apic++) {
1305 /* Read the register 0 value */
1306 spin_lock_irqsave(&ioapic_lock, flags);
1307 reg_00.raw = io_apic_read(apic, 0);
1308 spin_unlock_irqrestore(&ioapic_lock, flags);
1310 old_id = mp_ioapics[apic].mpc_apicid;
1313 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1317 * We need to adjust the IRQ routing table
1318 * if the ID changed.
1320 if (old_id != mp_ioapics[apic].mpc_apicid)
1321 for (i = 0; i < mp_irq_entries; i++)
1322 if (mp_irqs[i].mpc_dstapic == old_id)
1323 mp_irqs[i].mpc_dstapic
1324 = mp_ioapics[apic].mpc_apicid;
1327 * Read the right value from the MPC table and
1328 * write it into the ID register.
1330 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1331 mp_ioapics[apic].mpc_apicid);
1333 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1334 spin_lock_irqsave(&ioapic_lock, flags);
1335 io_apic_write(apic, 0, reg_00.raw);
1336 spin_unlock_irqrestore(&ioapic_lock, flags);
1341 spin_lock_irqsave(&ioapic_lock, flags);
1342 reg_00.raw = io_apic_read(apic, 0);
1343 spin_unlock_irqrestore(&ioapic_lock, flags);
1344 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1345 printk("could not set ID!\n");
1347 apic_printk(APIC_VERBOSE," ok.\n");
1352 * There is a nasty bug in some older SMP boards, their mptable lies
1353 * about the timer IRQ. We do the following to work around the situation:
1355 * - timer IRQ defaults to IO-APIC IRQ
1356 * - if this function detects that timer IRQs are defunct, then we fall
1357 * back to ISA timer IRQs
1359 static int __init timer_irq_works(void)
1361 unsigned long t1 = jiffies;
1364 /* Let ten ticks pass... */
1365 mdelay((10 * 1000) / HZ);
1368 * Expect a few ticks at least, to be sure some possible
1369 * glue logic does not lock up after one or two first
1370 * ticks in a non-ExtINT mode. Also the local APIC
1371 * might have cached one ExtINT interrupt. Finally, at
1372 * least one tick may be lost due to delays.
1376 if (jiffies - t1 > 4)
1382 * In the SMP+IOAPIC case it might happen that there are an unspecified
1383 * number of pending IRQ events unhandled. These cases are very rare,
1384 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1385 * better to do it this way as thus we do not have to be aware of
1386 * 'pending' interrupts in the IRQ path, except at this point.
1389 * Edge triggered needs to resend any interrupt
1390 * that was delayed but this is now handled in the device
1395 * Starting up a edge-triggered IO-APIC interrupt is
1396 * nasty - we need to make sure that we get the edge.
1397 * If it is already asserted for some reason, we need
1398 * return 1 to indicate that is was pending.
1400 * This is not complete - we should be able to fake
1401 * an edge even if it isn't on the 8259A...
1404 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1406 int was_pending = 0;
1407 unsigned long flags;
1409 spin_lock_irqsave(&ioapic_lock, flags);
1411 disable_8259A_irq(irq);
1412 if (i8259A_irq_pending(irq))
1415 __unmask_IO_APIC_irq(irq);
1416 spin_unlock_irqrestore(&ioapic_lock, flags);
1422 * Once we have recorded IRQ_PENDING already, we can mask the
1423 * interrupt for real. This prevents IRQ storms from unhandled
1426 static void ack_edge_ioapic_irq(unsigned int irq)
1429 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1430 == (IRQ_PENDING | IRQ_DISABLED))
1431 mask_IO_APIC_irq(irq);
1436 * Level triggered interrupts can just be masked,
1437 * and shutting down and starting up the interrupt
1438 * is the same as enabling and disabling them -- except
1439 * with a startup need to return a "was pending" value.
1441 * Level triggered interrupts are special because we
1442 * do not touch any IO-APIC register while handling
1443 * them. We ack the APIC in the end-IRQ handler, not
1444 * in the start-IRQ-handler. Protection against reentrance
1445 * from the same interrupt is still provided, both by the
1446 * generic IRQ layer and by the fact that an unacked local
1447 * APIC does not accept IRQs.
1449 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1451 unmask_IO_APIC_irq(irq);
1453 return 0; /* don't check for pending */
1456 static void end_level_ioapic_irq (unsigned int irq)
1462 #ifdef CONFIG_PCI_MSI
1463 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1465 int irq = vector_to_irq(vector);
1467 return startup_edge_ioapic_irq(irq);
1470 static void ack_edge_ioapic_vector(unsigned int vector)
1472 int irq = vector_to_irq(vector);
1474 move_native_irq(vector);
1475 ack_edge_ioapic_irq(irq);
1478 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1480 int irq = vector_to_irq(vector);
1482 return startup_level_ioapic_irq (irq);
1485 static void end_level_ioapic_vector (unsigned int vector)
1487 int irq = vector_to_irq(vector);
1489 move_native_irq(vector);
1490 end_level_ioapic_irq(irq);
1493 static void mask_IO_APIC_vector (unsigned int vector)
1495 int irq = vector_to_irq(vector);
1497 mask_IO_APIC_irq(irq);
1500 static void unmask_IO_APIC_vector (unsigned int vector)
1502 int irq = vector_to_irq(vector);
1504 unmask_IO_APIC_irq(irq);
1508 static void set_ioapic_affinity_vector (unsigned int vector,
1511 int irq = vector_to_irq(vector);
1513 set_native_irq_info(vector, cpu_mask);
1514 set_ioapic_affinity_irq(irq, cpu_mask);
1516 #endif // CONFIG_SMP
1517 #endif // CONFIG_PCI_MSI
1519 static int ioapic_retrigger(unsigned int irq)
1521 send_IPI_self(IO_APIC_VECTOR(irq));
1527 * Level and edge triggered IO-APIC interrupts need different handling,
1528 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1529 * handled with the level-triggered descriptor, but that one has slightly
1530 * more overhead. Level-triggered interrupts cannot be handled with the
1531 * edge-triggered handler, without risking IRQ storms and other ugly
1535 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1536 .typename = "IO-APIC-edge",
1537 .startup = startup_edge_ioapic,
1538 .shutdown = shutdown_edge_ioapic,
1539 .enable = enable_edge_ioapic,
1540 .disable = disable_edge_ioapic,
1541 .ack = ack_edge_ioapic,
1542 .end = end_edge_ioapic,
1544 .set_affinity = set_ioapic_affinity,
1546 .retrigger = ioapic_retrigger,
1549 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1550 .typename = "IO-APIC-level",
1551 .startup = startup_level_ioapic,
1552 .shutdown = shutdown_level_ioapic,
1553 .enable = enable_level_ioapic,
1554 .disable = disable_level_ioapic,
1555 .ack = mask_and_ack_level_ioapic,
1556 .end = end_level_ioapic,
1558 .set_affinity = set_ioapic_affinity,
1560 .retrigger = ioapic_retrigger,
1563 static inline void init_IO_APIC_traps(void)
1568 * NOTE! The local APIC isn't very good at handling
1569 * multiple interrupts at the same interrupt level.
1570 * As the interrupt level is determined by taking the
1571 * vector number and shifting that right by 4, we
1572 * want to spread these out a bit so that they don't
1573 * all fall in the same interrupt level.
1575 * Also, we've got to be careful not to trash gate
1576 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1578 for (irq = 0; irq < NR_IRQS ; irq++) {
1580 if (use_pci_vector()) {
1581 if (!platform_legacy_irq(tmp))
1582 if ((tmp = vector_to_irq(tmp)) == -1)
1585 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1587 * Hmm.. We don't have an entry for this,
1588 * so default to an old-fashioned 8259
1589 * interrupt if we can..
1592 make_8259A_irq(irq);
1594 /* Strange. Oh, well.. */
1595 irq_desc[irq].chip = &no_irq_type;
1600 static void enable_lapic_irq (unsigned int irq)
1604 v = apic_read(APIC_LVT0);
1605 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1608 static void disable_lapic_irq (unsigned int irq)
1612 v = apic_read(APIC_LVT0);
1613 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1616 static void ack_lapic_irq (unsigned int irq)
1621 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1623 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1624 .typename = "local-APIC-edge",
1625 .startup = NULL, /* startup_irq() not used for IRQ0 */
1626 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1627 .enable = enable_lapic_irq,
1628 .disable = disable_lapic_irq,
1629 .ack = ack_lapic_irq,
1630 .end = end_lapic_irq,
1633 static void setup_nmi (void)
1636 * Dirty trick to enable the NMI watchdog ...
1637 * We put the 8259A master into AEOI mode and
1638 * unmask on all local APICs LVT0 as NMI.
1640 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1641 * is from Maciej W. Rozycki - so we do not have to EOI from
1642 * the NMI handler or the timer interrupt.
1644 printk(KERN_INFO "activating NMI Watchdog ...");
1646 enable_NMI_through_LVT0(NULL);
1652 * This looks a bit hackish but it's about the only one way of sending
1653 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1654 * not support the ExtINT mode, unfortunately. We need to send these
1655 * cycles as some i82489DX-based boards have glue logic that keeps the
1656 * 8259A interrupt line asserted until INTA. --macro
1658 static inline void unlock_ExtINT_logic(void)
1661 struct IO_APIC_route_entry entry0, entry1;
1662 unsigned char save_control, save_freq_select;
1663 unsigned long flags;
1665 pin = find_isa_irq_pin(8, mp_INT);
1666 apic = find_isa_irq_apic(8, mp_INT);
1670 spin_lock_irqsave(&ioapic_lock, flags);
1671 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1672 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1673 spin_unlock_irqrestore(&ioapic_lock, flags);
1674 clear_IO_APIC_pin(apic, pin);
1676 memset(&entry1, 0, sizeof(entry1));
1678 entry1.dest_mode = 0; /* physical delivery */
1679 entry1.mask = 0; /* unmask IRQ now */
1680 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1681 entry1.delivery_mode = dest_ExtINT;
1682 entry1.polarity = entry0.polarity;
1686 spin_lock_irqsave(&ioapic_lock, flags);
1687 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1688 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1689 spin_unlock_irqrestore(&ioapic_lock, flags);
1691 save_control = CMOS_READ(RTC_CONTROL);
1692 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1693 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1695 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1700 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1704 CMOS_WRITE(save_control, RTC_CONTROL);
1705 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1706 clear_IO_APIC_pin(apic, pin);
1708 spin_lock_irqsave(&ioapic_lock, flags);
1709 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1710 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1711 spin_unlock_irqrestore(&ioapic_lock, flags);
1714 int timer_uses_ioapic_pin_0;
1717 * This code may look a bit paranoid, but it's supposed to cooperate with
1718 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1719 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1720 * fanatically on his truly buggy board.
1722 * FIXME: really need to revamp this for modern platforms only.
1724 static inline void check_timer(void)
1726 int apic1, pin1, apic2, pin2;
1730 * get/set the timer IRQ vector:
1732 disable_8259A_irq(0);
1733 vector = assign_irq_vector(0);
1734 set_intr_gate(vector, interrupt[0]);
1737 * Subtle, code in do_timer_interrupt() expects an AEOI
1738 * mode for the 8259A whenever interrupts are routed
1739 * through I/O APICs. Also IRQ0 has to be enabled in
1740 * the 8259A which implies the virtual wire has to be
1741 * disabled in the local APIC.
1743 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1745 if (timer_over_8254 > 0)
1746 enable_8259A_irq(0);
1748 pin1 = find_isa_irq_pin(0, mp_INT);
1749 apic1 = find_isa_irq_apic(0, mp_INT);
1750 pin2 = ioapic_i8259.pin;
1751 apic2 = ioapic_i8259.apic;
1754 timer_uses_ioapic_pin_0 = 1;
1756 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1757 vector, apic1, pin1, apic2, pin2);
1761 * Ok, does IRQ0 through the IOAPIC work?
1763 unmask_IO_APIC_irq(0);
1764 if (!no_timer_check && timer_irq_works()) {
1765 nmi_watchdog_default();
1766 if (nmi_watchdog == NMI_IO_APIC) {
1767 disable_8259A_irq(0);
1769 enable_8259A_irq(0);
1771 if (disable_timer_pin_1 > 0)
1772 clear_IO_APIC_pin(0, pin1);
1775 clear_IO_APIC_pin(apic1, pin1);
1776 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1777 "connected to IO-APIC\n");
1780 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1781 "through the 8259A ... ");
1783 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1786 * legacy devices should be connected to IO APIC #0
1788 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1789 if (timer_irq_works()) {
1790 apic_printk(APIC_VERBOSE," works.\n");
1791 nmi_watchdog_default();
1792 if (nmi_watchdog == NMI_IO_APIC) {
1798 * Cleanup, just in case ...
1800 clear_IO_APIC_pin(apic2, pin2);
1802 apic_printk(APIC_VERBOSE," failed.\n");
1804 if (nmi_watchdog == NMI_IO_APIC) {
1805 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1809 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1811 disable_8259A_irq(0);
1812 irq_desc[0].chip = &lapic_irq_type;
1813 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1814 enable_8259A_irq(0);
1816 if (timer_irq_works()) {
1817 apic_printk(APIC_VERBOSE," works.\n");
1820 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1821 apic_printk(APIC_VERBOSE," failed.\n");
1823 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1827 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1829 unlock_ExtINT_logic();
1831 if (timer_irq_works()) {
1832 apic_printk(APIC_VERBOSE," works.\n");
1835 apic_printk(APIC_VERBOSE," failed :(.\n");
1836 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1839 static int __init notimercheck(char *s)
1844 __setup("no_timer_check", notimercheck);
1848 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1849 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1850 * Linux doesn't really care, as it's not actually used
1851 * for any interrupt handling anyway.
1853 #define PIC_IRQS (1<<2)
1855 void __init setup_IO_APIC(void)
1860 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1862 io_apic_irqs = ~PIC_IRQS;
1864 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1867 * Set up the IO-APIC IRQ routing table.
1870 setup_ioapic_ids_from_mpc();
1872 setup_IO_APIC_irqs();
1873 init_IO_APIC_traps();
1879 struct sysfs_ioapic_data {
1880 struct sys_device dev;
1881 struct IO_APIC_route_entry entry[0];
1883 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1885 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1887 struct IO_APIC_route_entry *entry;
1888 struct sysfs_ioapic_data *data;
1891 data = container_of(dev, struct sysfs_ioapic_data, dev);
1892 entry = data->entry;
1893 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1894 *entry = ioapic_read_entry(dev->id, i);
1899 static int ioapic_resume(struct sys_device *dev)
1901 struct IO_APIC_route_entry *entry;
1902 struct sysfs_ioapic_data *data;
1903 unsigned long flags;
1904 union IO_APIC_reg_00 reg_00;
1907 data = container_of(dev, struct sysfs_ioapic_data, dev);
1908 entry = data->entry;
1910 spin_lock_irqsave(&ioapic_lock, flags);
1911 reg_00.raw = io_apic_read(dev->id, 0);
1912 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1913 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1914 io_apic_write(dev->id, 0, reg_00.raw);
1916 spin_unlock_irqrestore(&ioapic_lock, flags);
1917 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1918 ioapic_write_entry(dev->id, i, entry[i]);
1923 static struct sysdev_class ioapic_sysdev_class = {
1924 set_kset_name("ioapic"),
1925 .suspend = ioapic_suspend,
1926 .resume = ioapic_resume,
1929 static int __init ioapic_init_sysfs(void)
1931 struct sys_device * dev;
1932 int i, size, error = 0;
1934 error = sysdev_class_register(&ioapic_sysdev_class);
1938 for (i = 0; i < nr_ioapics; i++ ) {
1939 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1940 * sizeof(struct IO_APIC_route_entry);
1941 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1942 if (!mp_ioapic_data[i]) {
1943 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1946 memset(mp_ioapic_data[i], 0, size);
1947 dev = &mp_ioapic_data[i]->dev;
1949 dev->cls = &ioapic_sysdev_class;
1950 error = sysdev_register(dev);
1952 kfree(mp_ioapic_data[i]);
1953 mp_ioapic_data[i] = NULL;
1954 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1962 device_initcall(ioapic_init_sysfs);
1964 /* --------------------------------------------------------------------------
1965 ACPI-based IOAPIC Configuration
1966 -------------------------------------------------------------------------- */
1970 #define IO_APIC_MAX_ID 0xFE
1972 int __init io_apic_get_version (int ioapic)
1974 union IO_APIC_reg_01 reg_01;
1975 unsigned long flags;
1977 spin_lock_irqsave(&ioapic_lock, flags);
1978 reg_01.raw = io_apic_read(ioapic, 1);
1979 spin_unlock_irqrestore(&ioapic_lock, flags);
1981 return reg_01.bits.version;
1985 int __init io_apic_get_redir_entries (int ioapic)
1987 union IO_APIC_reg_01 reg_01;
1988 unsigned long flags;
1990 spin_lock_irqsave(&ioapic_lock, flags);
1991 reg_01.raw = io_apic_read(ioapic, 1);
1992 spin_unlock_irqrestore(&ioapic_lock, flags);
1994 return reg_01.bits.entries;
1998 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2000 struct IO_APIC_route_entry entry;
2001 unsigned long flags;
2003 if (!IO_APIC_IRQ(irq)) {
2004 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2010 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2011 * Note that we mask (disable) IRQs now -- these get enabled when the
2012 * corresponding device driver registers for this IRQ.
2015 memset(&entry,0,sizeof(entry));
2017 entry.delivery_mode = INT_DELIVERY_MODE;
2018 entry.dest_mode = INT_DEST_MODE;
2019 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2020 entry.trigger = triggering;
2021 entry.polarity = polarity;
2022 entry.mask = 1; /* Disabled (masked) */
2024 irq = gsi_irq_sharing(irq);
2026 * IRQs < 16 are already in the irq_2_pin[] map
2029 add_pin_to_irq(irq, ioapic, pin);
2031 entry.vector = assign_irq_vector(irq);
2033 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2034 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2035 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2036 triggering, polarity);
2038 ioapic_register_intr(irq, entry.vector, triggering);
2040 if (!ioapic && (irq < 16))
2041 disable_8259A_irq(irq);
2043 ioapic_write_entry(ioapic, pin, entry);
2045 spin_lock_irqsave(&ioapic_lock, flags);
2046 set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2047 spin_unlock_irqrestore(&ioapic_lock, flags);
2052 #endif /* CONFIG_ACPI */
2056 * This function currently is only a helper for the i386 smp boot process where
2057 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2058 * so mask in all cases should simply be TARGET_CPUS
2061 void __init setup_ioapic_dest(void)
2063 int pin, ioapic, irq, irq_entry;
2065 if (skip_ioapic_setup == 1)
2068 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2069 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2070 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2071 if (irq_entry == -1)
2073 irq = pin_2_irq(irq_entry, ioapic, pin);
2074 set_ioapic_affinity_irq(irq, TARGET_CPUS);