2 * (c) 2005, 2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Support : jacob.shin@amd.com
12 * - added support for AMD Family 0x10 processors
14 * All MC4_MISCi registers are shared between multi-cores
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/kobject.h>
22 #include <linux/notifier.h>
23 #include <linux/sched.h>
24 #include <linux/smp.h>
25 #include <linux/sysdev.h>
26 #include <linux/sysfs.h>
30 #include <asm/percpu.h>
33 #define PFX "mce_threshold: "
34 #define VERSION "version 1.1.1"
37 #define THRESHOLD_MAX 0xFFF
38 #define INT_TYPE_APIC 0x00020000
39 #define MASK_VALID_HI 0x80000000
40 #define MASK_CNTP_HI 0x40000000
41 #define MASK_LOCKED_HI 0x20000000
42 #define MASK_LVTOFF_HI 0x00F00000
43 #define MASK_COUNT_EN_HI 0x00080000
44 #define MASK_INT_TYPE_HI 0x00060000
45 #define MASK_OVERFLOW_HI 0x00010000
46 #define MASK_ERR_COUNT_HI 0x00000FFF
47 #define MASK_BLKPTR_LO 0xFF000000
48 #define MCG_XBLK_ADDR 0xC0000400
50 struct threshold_block {
58 struct list_head miscj;
61 /* defaults used early on boot */
62 static struct threshold_block threshold_defaults = {
63 .interrupt_enable = 0,
64 .threshold_limit = THRESHOLD_MAX,
67 struct threshold_bank {
69 struct threshold_block *blocks;
72 static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
75 static unsigned char shared_bank[NR_BANKS] = {
80 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
86 /* must be called with correct cpu affinity */
87 static void threshold_restart_bank(struct threshold_block *b,
88 int reset, u16 old_limit)
90 u32 mci_misc_hi, mci_misc_lo;
92 rdmsr(b->address, mci_misc_lo, mci_misc_hi);
94 if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
95 reset = 1; /* limit cannot be lower than err count */
97 if (reset) { /* reset err count and overflow bit */
99 (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
100 (THRESHOLD_MAX - b->threshold_limit);
101 } else if (old_limit) { /* change limit w/o reset */
102 int new_count = (mci_misc_hi & THRESHOLD_MAX) +
103 (old_limit - b->threshold_limit);
104 mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
105 (new_count & THRESHOLD_MAX);
108 b->interrupt_enable ?
109 (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
110 (mci_misc_hi &= ~MASK_INT_TYPE_HI);
112 mci_misc_hi |= MASK_COUNT_EN_HI;
113 wrmsr(b->address, mci_misc_lo, mci_misc_hi);
116 /* cpu init entry point, called from mce.c with preempt off */
117 void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
119 unsigned int bank, block;
120 unsigned int cpu = smp_processor_id();
121 u32 low = 0, high = 0, address = 0;
123 for (bank = 0; bank < NR_BANKS; ++bank) {
124 for (block = 0; block < NR_BLOCKS; ++block) {
126 address = MSR_IA32_MC0_MISC + bank * 4;
127 else if (block == 1) {
128 address = (low & MASK_BLKPTR_LO) >> 21;
131 address += MCG_XBLK_ADDR;
136 if (rdmsr_safe(address, &low, &high))
139 if (!(high & MASK_VALID_HI)) {
146 if (!(high & MASK_CNTP_HI) ||
147 (high & MASK_LOCKED_HI))
151 per_cpu(bank_map, cpu) |= (1 << bank);
153 if (shared_bank[bank] && c->cpu_core_id)
156 high &= ~MASK_LVTOFF_HI;
157 high |= K8_APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
158 wrmsr(address, low, high);
160 setup_APIC_extened_lvt(K8_APIC_EXT_LVT_ENTRY_THRESHOLD,
161 THRESHOLD_APIC_VECTOR,
162 K8_APIC_EXT_INT_MSG_FIX, 0);
164 threshold_defaults.address = address;
165 threshold_restart_bank(&threshold_defaults, 0, 0);
171 * APIC Interrupt Handler
175 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
176 * the interrupt goes off when error_count reaches threshold_limit.
177 * the handler will simply log mcelog w/ software defined bank number.
179 asmlinkage void mce_threshold_interrupt(void)
181 unsigned int bank, block;
183 u32 low = 0, high = 0, address = 0;
189 memset(&m, 0, sizeof(m));
191 m.cpu = smp_processor_id();
193 /* assume first bank caused it */
194 for (bank = 0; bank < NR_BANKS; ++bank) {
195 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
197 for (block = 0; block < NR_BLOCKS; ++block) {
199 address = MSR_IA32_MC0_MISC + bank * 4;
200 else if (block == 1) {
201 address = (low & MASK_BLKPTR_LO) >> 21;
204 address += MCG_XBLK_ADDR;
209 if (rdmsr_safe(address, &low, &high))
212 if (!(high & MASK_VALID_HI)) {
219 if (!(high & MASK_CNTP_HI) ||
220 (high & MASK_LOCKED_HI))
223 if (high & MASK_OVERFLOW_HI) {
224 rdmsrl(address, m.misc);
225 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
227 m.bank = K8_MCE_THRESHOLD_BASE
243 struct threshold_attr {
244 struct attribute attr;
245 ssize_t(*show) (struct threshold_block *, char *);
246 ssize_t(*store) (struct threshold_block *, const char *, size_t count);
249 static cpumask_t affinity_set(unsigned int cpu)
251 cpumask_t oldmask = current->cpus_allowed;
252 cpumask_t newmask = CPU_MASK_NONE;
253 cpu_set(cpu, newmask);
254 set_cpus_allowed(current, newmask);
258 static void affinity_restore(cpumask_t oldmask)
260 set_cpus_allowed(current, oldmask);
263 #define SHOW_FIELDS(name) \
264 static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
266 return sprintf(buf, "%lx\n", (unsigned long) b->name); \
268 SHOW_FIELDS(interrupt_enable)
269 SHOW_FIELDS(threshold_limit)
271 static ssize_t store_interrupt_enable(struct threshold_block *b,
272 const char *buf, size_t count)
276 unsigned long new = simple_strtoul(buf, &end, 0);
279 b->interrupt_enable = !!new;
281 oldmask = affinity_set(b->cpu);
282 threshold_restart_bank(b, 0, 0);
283 affinity_restore(oldmask);
288 static ssize_t store_threshold_limit(struct threshold_block *b,
289 const char *buf, size_t count)
294 unsigned long new = simple_strtoul(buf, &end, 0);
297 if (new > THRESHOLD_MAX)
301 old = b->threshold_limit;
302 b->threshold_limit = new;
304 oldmask = affinity_set(b->cpu);
305 threshold_restart_bank(b, 0, old);
306 affinity_restore(oldmask);
311 static ssize_t show_error_count(struct threshold_block *b, char *buf)
315 oldmask = affinity_set(b->cpu);
316 rdmsr(b->address, low, high);
317 affinity_restore(oldmask);
318 return sprintf(buf, "%x\n",
319 (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
322 static ssize_t store_error_count(struct threshold_block *b,
323 const char *buf, size_t count)
326 oldmask = affinity_set(b->cpu);
327 threshold_restart_bank(b, 1, 0);
328 affinity_restore(oldmask);
332 #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
333 .attr = {.name = __stringify(_name), .mode = _mode }, \
338 #define RW_ATTR(name) \
339 static struct threshold_attr name = \
340 THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
342 RW_ATTR(interrupt_enable);
343 RW_ATTR(threshold_limit);
344 RW_ATTR(error_count);
346 static struct attribute *default_attrs[] = {
347 &interrupt_enable.attr,
348 &threshold_limit.attr,
353 #define to_block(k) container_of(k, struct threshold_block, kobj)
354 #define to_attr(a) container_of(a, struct threshold_attr, attr)
356 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
358 struct threshold_block *b = to_block(kobj);
359 struct threshold_attr *a = to_attr(attr);
361 ret = a->show ? a->show(b, buf) : -EIO;
365 static ssize_t store(struct kobject *kobj, struct attribute *attr,
366 const char *buf, size_t count)
368 struct threshold_block *b = to_block(kobj);
369 struct threshold_attr *a = to_attr(attr);
371 ret = a->store ? a->store(b, buf, count) : -EIO;
375 static struct sysfs_ops threshold_ops = {
380 static struct kobj_type threshold_ktype = {
381 .sysfs_ops = &threshold_ops,
382 .default_attrs = default_attrs,
385 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
392 struct threshold_block *b = NULL;
394 if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
397 if (rdmsr_safe(address, &low, &high))
400 if (!(high & MASK_VALID_HI)) {
407 if (!(high & MASK_CNTP_HI) ||
408 (high & MASK_LOCKED_HI))
411 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
418 b->address = address;
419 b->interrupt_enable = 0;
420 b->threshold_limit = THRESHOLD_MAX;
422 INIT_LIST_HEAD(&b->miscj);
424 if (per_cpu(threshold_banks, cpu)[bank]->blocks)
426 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
428 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
430 kobject_set_name(&b->kobj, "misc%i", block);
431 b->kobj.parent = &per_cpu(threshold_banks, cpu)[bank]->kobj;
432 b->kobj.ktype = &threshold_ktype;
433 err = kobject_register(&b->kobj);
438 address = (low & MASK_BLKPTR_LO) >> 21;
441 address += MCG_XBLK_ADDR;
445 err = allocate_threshold_blocks(cpu, bank, ++block, address);
453 kobject_unregister(&b->kobj);
459 /* symlinks sibling shared banks to first core. first core owns dir/files. */
460 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
463 struct threshold_bank *b = NULL;
464 cpumask_t oldmask = CPU_MASK_NONE;
467 sprintf(name, "threshold_bank%i", bank);
470 if (cpu_data[cpu].cpu_core_id && shared_bank[bank]) { /* symlink */
471 i = first_cpu(cpu_core_map[cpu]);
473 /* first core not up yet */
474 if (cpu_data[i].cpu_core_id)
478 if (per_cpu(threshold_banks, cpu)[bank])
481 b = per_cpu(threshold_banks, i)[bank];
486 err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
491 b->cpus = cpu_core_map[cpu];
492 per_cpu(threshold_banks, cpu)[bank] = b;
497 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
503 kobject_set_name(&b->kobj, "threshold_bank%i", bank);
504 b->kobj.parent = &per_cpu(device_mce, cpu).kobj;
506 b->cpus = CPU_MASK_ALL;
508 b->cpus = cpu_core_map[cpu];
510 err = kobject_register(&b->kobj);
514 per_cpu(threshold_banks, cpu)[bank] = b;
516 oldmask = affinity_set(cpu);
517 err = allocate_threshold_blocks(cpu, bank, 0,
518 MSR_IA32_MC0_MISC + bank * 4);
519 affinity_restore(oldmask);
524 for_each_cpu_mask(i, b->cpus) {
528 err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
533 per_cpu(threshold_banks, i)[bank] = b;
539 per_cpu(threshold_banks, cpu)[bank] = NULL;
545 /* create dir/files for all valid threshold banks */
546 static __cpuinit int threshold_create_device(unsigned int cpu)
551 for (bank = 0; bank < NR_BANKS; ++bank) {
552 if (!(per_cpu(bank_map, cpu) & 1 << bank))
554 err = threshold_create_bank(cpu, bank);
563 * let's be hotplug friendly.
564 * in case of multiple core processors, the first core always takes ownership
565 * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
568 static void deallocate_threshold_block(unsigned int cpu,
571 struct threshold_block *pos = NULL;
572 struct threshold_block *tmp = NULL;
573 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
578 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
579 kobject_unregister(&pos->kobj);
580 list_del(&pos->miscj);
584 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
585 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
588 static void threshold_remove_bank(unsigned int cpu, int bank)
591 struct threshold_bank *b;
594 b = per_cpu(threshold_banks, cpu)[bank];
602 sprintf(name, "threshold_bank%i", bank);
605 /* sibling symlink */
606 if (shared_bank[bank] && b->blocks->cpu != cpu) {
607 sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
608 per_cpu(threshold_banks, cpu)[bank] = NULL;
613 /* remove all sibling symlinks before unregistering */
614 for_each_cpu_mask(i, b->cpus) {
618 sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
619 per_cpu(threshold_banks, i)[bank] = NULL;
622 deallocate_threshold_block(cpu, bank);
625 kobject_unregister(&b->kobj);
627 per_cpu(threshold_banks, cpu)[bank] = NULL;
630 static void threshold_remove_device(unsigned int cpu)
634 for (bank = 0; bank < NR_BANKS; ++bank) {
635 if (!(per_cpu(bank_map, cpu) & 1 << bank))
637 threshold_remove_bank(cpu, bank);
641 /* get notified when a cpu comes on/off */
642 static int threshold_cpu_callback(struct notifier_block *nfb,
643 unsigned long action, void *hcpu)
645 /* cpu was unsigned int to begin with */
646 unsigned int cpu = (unsigned long)hcpu;
653 threshold_create_device(cpu);
656 threshold_remove_device(cpu);
665 static struct notifier_block threshold_cpu_notifier = {
666 .notifier_call = threshold_cpu_callback,
669 static __init int threshold_init_device(void)
673 /* to hit CPUs online before the notifier is up */
674 for_each_online_cpu(lcpu) {
675 int err = threshold_create_device(lcpu);
679 register_hotcpu_notifier(&threshold_cpu_notifier);
683 device_initcall(threshold_init_device);