arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/nmi.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cpumask.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30 #include <asm/intel_arch_perfmon.h>
  31
  32 int unknown_nmi_panic;
  33 int nmi_watchdog_enabled;
  34 int panic_on_unrecovered_nmi;
  35
  36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  37  * evtsel_nmi_owner tracks the ownership of the event selection
  38  * - different performance counters/ event selection may be reserved for
  39  *   different subsystems this reservation system just tries to coordinate
  40  *   things a little
  41  */
  42 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
  43 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
  44
  45 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  46
  47 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  48  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  49  */
  50 #define NMI_MAX_COUNTER_BITS 66
  51
  52 /* nmi_active:
  53  * >0: the lapic NMI watchdog is active, but can be disabled
  54  * <0: the lapic NMI watchdog has not been set up, and cannot
  55  *     be enabled
  56  *  0: the lapic NMI watchdog is disabled, but can be enabled
  57  */
  58 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  59 int panic_on_timeout;
  60
  61 unsigned int nmi_watchdog = NMI_DEFAULT;
  62 static unsigned int nmi_hz = HZ;
  63
  64 struct nmi_watchdog_ctlblk {
  65         int enabled;
  66         u64 check_bit;
  67         unsigned int cccr_msr;
  68         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  69         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  70 };
  71 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  72
  73 /* local prototypes */
  74 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  75
  76 /* converts an msr to an appropriate reservation bit */
  77 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  78 {
  79         /* returns the bit offset of the performance counter register */
  80         switch (boot_cpu_data.x86_vendor) {
  81         case X86_VENDOR_AMD:
  82                 return (msr - MSR_K7_PERFCTR0);
  83         case X86_VENDOR_INTEL:
  84                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  85                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  86                 else
  87                         return (msr - MSR_P4_BPU_PERFCTR0);
  88         }
  89         return 0;
  90 }
  91
  92 /* converts an msr to an appropriate reservation bit */
  93 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  94 {
  95         /* returns the bit offset of the event selection register */
  96         switch (boot_cpu_data.x86_vendor) {
  97         case X86_VENDOR_AMD:
  98                 return (msr - MSR_K7_EVNTSEL0);
  99         case X86_VENDOR_INTEL:
 100                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 101                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 102                 else
 103                         return (msr - MSR_P4_BSU_ESCR0);
 104         }
 105         return 0;
 106 }
 107
 108 /* checks for a bit availability (hack for oprofile) */
 109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 110 {
 111         int cpu;
 112         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 113         for_each_possible_cpu (cpu) {
 114                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 115                         return 0;
 116         }
 117         return 1;
 118 }
 119
 120 /* checks the an msr for availability */
 121 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 122 {
 123         unsigned int counter;
 124         int cpu;
 125
 126         counter = nmi_perfctr_msr_to_bit(msr);
 127         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 128
 129         for_each_possible_cpu (cpu) {
 130                 if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 131                         return 0;
 132         }
 133         return 1;
 134 }
 135
 136 static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
 137 {
 138         unsigned int counter;
 139         if (cpu < 0)
 140                 cpu = smp_processor_id();
 141
 142         counter = nmi_perfctr_msr_to_bit(msr);
 143         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 144
 145         if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
 146                 return 1;
 147         return 0;
 148 }
 149
 150 static void __release_perfctr_nmi(int cpu, unsigned int msr)
 151 {
 152         unsigned int counter;
 153         if (cpu < 0)
 154                 cpu = smp_processor_id();
 155
 156         counter = nmi_perfctr_msr_to_bit(msr);
 157         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 158
 159         clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu));
 160 }
 161
 162 int reserve_perfctr_nmi(unsigned int msr)
 163 {
 164         int cpu, i;
 165         for_each_possible_cpu (cpu) {
 166                 if (!__reserve_perfctr_nmi(cpu, msr)) {
 167                         for_each_possible_cpu (i) {
 168                                 if (i >= cpu)
 169                                         break;
 170                                 __release_perfctr_nmi(i, msr);
 171                         }
 172                         return 0;
 173                 }
 174         }
 175         return 1;
 176 }
 177
 178 void release_perfctr_nmi(unsigned int msr)
 179 {
 180         int cpu;
 181         for_each_possible_cpu (cpu)
 182                 __release_perfctr_nmi(cpu, msr);
 183 }
 184
 185 int __reserve_evntsel_nmi(int cpu, unsigned int msr)
 186 {
 187         unsigned int counter;
 188         if (cpu < 0)
 189                 cpu = smp_processor_id();
 190
 191         counter = nmi_evntsel_msr_to_bit(msr);
 192         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 193
 194         if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
 195                 return 1;
 196         return 0;
 197 }
 198
 199 static void __release_evntsel_nmi(int cpu, unsigned int msr)
 200 {
 201         unsigned int counter;
 202         if (cpu < 0)
 203                 cpu = smp_processor_id();
 204
 205         counter = nmi_evntsel_msr_to_bit(msr);
 206         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 207
 208         clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
 209 }
 210
 211 int reserve_evntsel_nmi(unsigned int msr)
 212 {
 213         int cpu, i;
 214         for_each_possible_cpu (cpu) {
 215                 if (!__reserve_evntsel_nmi(cpu, msr)) {
 216                         for_each_possible_cpu (i) {
 217                                 if (i >= cpu)
 218                                         break;
 219                                 __release_evntsel_nmi(i, msr);
 220                         }
 221                         return 0;
 222                 }
 223         }
 224         return 1;
 225 }
 226
 227 void release_evntsel_nmi(unsigned int msr)
 228 {
 229         int cpu;
 230         for_each_possible_cpu (cpu) {
 231                 __release_evntsel_nmi(cpu, msr);
 232         }
 233 }
 234
 235 static __cpuinit inline int nmi_known_cpu(void)
 236 {
 237         switch (boot_cpu_data.x86_vendor) {
 238         case X86_VENDOR_AMD:
 239                 return boot_cpu_data.x86 == 15 || boot_cpu_data.x86 == 16;
 240         case X86_VENDOR_INTEL:
 241                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 242                         return 1;
 243                 else
 244                         return (boot_cpu_data.x86 == 15);
 245         }
 246         return 0;
 247 }
 248
 249 /* Run after command line and cpu_init init, but before all other checks */
 250 void nmi_watchdog_default(void)
 251 {
 252         if (nmi_watchdog != NMI_DEFAULT)
 253                 return;
 254         nmi_watchdog = NMI_NONE;
 255 }
 256
 257 static int endflag __initdata = 0;
 258
 259 #ifdef CONFIG_SMP
 260 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 261  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 262  * CPUs during the test make them busy.
 263  */
 264 static __init void nmi_cpu_busy(void *data)
 265 {
 266         local_irq_enable_in_hardirq();
 267         /* Intentionally don't use cpu_relax here. This is
 268            to make sure that the performance counter really ticks,
 269            even if there is a simulator or similar that catches the
 270            pause instruction. On a real HT machine this is fine because
 271            all other CPUs are busy with "useless" delay loops and don't
 272            care if they get somewhat less cycles. */
 273         while (endflag == 0)
 274                 mb();
 275 }
 276 #endif
 277
 278 static unsigned int adjust_for_32bit_ctr(unsigned int hz)
 279 {
 280         unsigned int retval = hz;
 281
 282         /*
 283          * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
 284          * are writable, with higher bits sign extending from bit 31.
 285          * So, we can only program the counter with 31 bit values and
 286          * 32nd bit should be 1, for 33.. to be 1.
 287          * Find the appropriate nmi_hz
 288          */
 289         if ((((u64)cpu_khz * 1000) / retval) > 0x7fffffffULL) {
 290                 retval = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
 291         }
 292         return retval;
 293 }
 294
 295 int __init check_nmi_watchdog (void)
 296 {
 297         int *counts;
 298         int cpu;
 299
 300         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 301                 return 0;
 302
 303         if (!atomic_read(&nmi_active))
 304                 return 0;
 305
 306         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 307         if (!counts)
 308                 return -1;
 309
 310         printk(KERN_INFO "testing NMI watchdog ... ");
 311
 312 #ifdef CONFIG_SMP
 313         if (nmi_watchdog == NMI_LOCAL_APIC)
 314                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 315 #endif
 316
 317         for (cpu = 0; cpu < NR_CPUS; cpu++)
 318                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 319         local_irq_enable();
 320         mdelay((20*1000)/nmi_hz); // wait 20 ticks
 321
 322         for_each_online_cpu(cpu) {
 323                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 324                         continue;
 325                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 326                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 327                                cpu,
 328                                counts[cpu],
 329                                cpu_pda(cpu)->__nmi_count);
 330                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 331                         atomic_dec(&nmi_active);
 332                 }
 333         }
 334         if (!atomic_read(&nmi_active)) {
 335                 kfree(counts);
 336                 atomic_set(&nmi_active, -1);
 337                 endflag = 1;
 338                 return -1;
 339         }
 340         endflag = 1;
 341         printk("OK.\n");
 342
 343         /* now that we know it works we can reduce NMI frequency to
 344            something more reasonable; makes a difference in some configs */
 345         if (nmi_watchdog == NMI_LOCAL_APIC) {
 346                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 347
 348                 nmi_hz = 1;
 349                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0)
 350                         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 351         }
 352
 353         kfree(counts);
 354         return 0;
 355 }
 356
 357 int __init setup_nmi_watchdog(char *str)
 358 {
 359         int nmi;
 360
 361         if (!strncmp(str,"panic",5)) {
 362                 panic_on_timeout = 1;
 363                 str = strchr(str, ',');
 364                 if (!str)
 365                         return 1;
 366                 ++str;
 367         }
 368
 369         get_option(&str, &nmi);
 370
 371         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 372                 return 0;
 373
 374         nmi_watchdog = nmi;
 375         return 1;
 376 }
 377
 378 __setup("nmi_watchdog=", setup_nmi_watchdog);
 379
 380 static void disable_lapic_nmi_watchdog(void)
 381 {
 382         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 383
 384         if (atomic_read(&nmi_active) <= 0)
 385                 return;
 386
 387         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 388
 389         BUG_ON(atomic_read(&nmi_active) != 0);
 390 }
 391
 392 static void enable_lapic_nmi_watchdog(void)
 393 {
 394         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 395
 396         /* are we already enabled */
 397         if (atomic_read(&nmi_active) != 0)
 398                 return;
 399
 400         /* are we lapic aware */
 401         if (nmi_known_cpu() <= 0)
 402                 return;
 403
 404         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 405         touch_nmi_watchdog();
 406 }
 407
 408 void disable_timer_nmi_watchdog(void)
 409 {
 410         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 411
 412         if (atomic_read(&nmi_active) <= 0)
 413                 return;
 414
 415         disable_irq(0);
 416         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 417
 418         BUG_ON(atomic_read(&nmi_active) != 0);
 419 }
 420
 421 void enable_timer_nmi_watchdog(void)
 422 {
 423         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 424
 425         if (atomic_read(&nmi_active) == 0) {
 426                 touch_nmi_watchdog();
 427                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 428                 enable_irq(0);
 429         }
 430 }
 431
 432 static void __acpi_nmi_disable(void *__unused)
 433 {
 434         apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
 435 }
 436
 437 /*
 438  * Disable timer based NMIs on all CPUs:
 439  */
 440 void acpi_nmi_disable(void)
 441 {
 442         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 443                 on_each_cpu(__acpi_nmi_disable, NULL, 0, 1);
 444 }
 445
 446 static void __acpi_nmi_enable(void *__unused)
 447 {
 448         apic_write(APIC_LVT0, APIC_DM_NMI);
 449 }
 450
 451 /*
 452  * Enable timer based NMIs on all CPUs:
 453  */
 454 void acpi_nmi_enable(void)
 455 {
 456         if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
 457                 on_each_cpu(__acpi_nmi_enable, NULL, 0, 1);
 458 }
 459 #ifdef CONFIG_PM
 460
 461 static int nmi_pm_active; /* nmi_active before suspend */
 462
 463 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 464 {
 465         /* only CPU0 goes here, other CPUs should be offline */
 466         nmi_pm_active = atomic_read(&nmi_active);
 467         stop_apic_nmi_watchdog(NULL);
 468         BUG_ON(atomic_read(&nmi_active) != 0);
 469         return 0;
 470 }
 471
 472 static int lapic_nmi_resume(struct sys_device *dev)
 473 {
 474         /* only CPU0 goes here, other CPUs should be offline */
 475         if (nmi_pm_active > 0) {
 476                 setup_apic_nmi_watchdog(NULL);
 477                 touch_nmi_watchdog();
 478         }
 479         return 0;
 480 }
 481
 482 static struct sysdev_class nmi_sysclass = {
 483         set_kset_name("lapic_nmi"),
 484         .resume         = lapic_nmi_resume,
 485         .suspend        = lapic_nmi_suspend,
 486 };
 487
 488 static struct sys_device device_lapic_nmi = {
 489         .id             = 0,
 490         .cls    = &nmi_sysclass,
 491 };
 492
 493 static int __init init_lapic_nmi_sysfs(void)
 494 {
 495         int error;
 496
 497         /* should really be a BUG_ON but b/c this is an
 498          * init call, it just doesn't work.  -dcz
 499          */
 500         if (nmi_watchdog != NMI_LOCAL_APIC)
 501                 return 0;
 502
 503         if ( atomic_read(&nmi_active) < 0 )
 504                 return 0;
 505
 506         error = sysdev_class_register(&nmi_sysclass);
 507         if (!error)
 508                 error = sysdev_register(&device_lapic_nmi);
 509         return error;
 510 }
 511 /* must come after the local APIC's device_initcall() */
 512 late_initcall(init_lapic_nmi_sysfs);
 513
 514 #endif  /* CONFIG_PM */
 515
 516 /*
 517  * Activate the NMI watchdog via the local APIC.
 518  * Original code written by Keith Owens.
 519  */
 520
 521 /* Note that these events don't tick when the CPU idles. This means
 522    the frequency varies with CPU load. */
 523
 524 #define K7_EVNTSEL_ENABLE       (1 << 22)
 525 #define K7_EVNTSEL_INT          (1 << 20)
 526 #define K7_EVNTSEL_OS           (1 << 17)
 527 #define K7_EVNTSEL_USR          (1 << 16)
 528 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 529 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 530
 531 static int setup_k7_watchdog(void)
 532 {
 533         unsigned int perfctr_msr, evntsel_msr;
 534         unsigned int evntsel;
 535         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 536
 537         perfctr_msr = MSR_K7_PERFCTR0;
 538         evntsel_msr = MSR_K7_EVNTSEL0;
 539         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 540                 goto fail;
 541
 542         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 543                 goto fail1;
 544
 545         /* Simulator may not support it */
 546         if (checking_wrmsrl(evntsel_msr, 0UL))
 547                 goto fail2;
 548         wrmsrl(perfctr_msr, 0UL);
 549
 550         evntsel = K7_EVNTSEL_INT
 551                 | K7_EVNTSEL_OS
 552                 | K7_EVNTSEL_USR
 553                 | K7_NMI_EVENT;
 554
 555         /* setup the timer */
 556         wrmsr(evntsel_msr, evntsel, 0);
 557         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 558         apic_write(APIC_LVTPC, APIC_DM_NMI);
 559         evntsel |= K7_EVNTSEL_ENABLE;
 560         wrmsr(evntsel_msr, evntsel, 0);
 561
 562         wd->perfctr_msr = perfctr_msr;
 563         wd->evntsel_msr = evntsel_msr;
 564         wd->cccr_msr = 0;  //unused
 565         wd->check_bit = 1ULL<<63;
 566         return 1;
 567 fail2:
 568         __release_evntsel_nmi(-1, evntsel_msr);
 569 fail1:
 570         __release_perfctr_nmi(-1, perfctr_msr);
 571 fail:
 572         return 0;
 573 }
 574
 575 static void stop_k7_watchdog(void)
 576 {
 577         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 578
 579         wrmsr(wd->evntsel_msr, 0, 0);
 580
 581         __release_evntsel_nmi(-1, wd->evntsel_msr);
 582         __release_perfctr_nmi(-1, wd->perfctr_msr);
 583 }
 584
 585 /* Note that these events don't tick when the CPU idles. This means
 586    the frequency varies with CPU load. */
 587
 588 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 589 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 590 #define P4_ESCR_OS              (1<<3)
 591 #define P4_ESCR_USR             (1<<2)
 592 #define P4_CCCR_OVF_PMI0        (1<<26)
 593 #define P4_CCCR_OVF_PMI1        (1<<27)
 594 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 595 #define P4_CCCR_COMPLEMENT      (1<<19)
 596 #define P4_CCCR_COMPARE         (1<<18)
 597 #define P4_CCCR_REQUIRED        (3<<16)
 598 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 599 #define P4_CCCR_ENABLE          (1<<12)
 600 #define P4_CCCR_OVF             (1<<31)
 601 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 602    CRU_ESCR0 (with any non-null event selector) through a complemented
 603    max threshold. [IA32-Vol3, Section 14.9.9] */
 604
 605 static int setup_p4_watchdog(void)
 606 {
 607         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 608         unsigned int evntsel, cccr_val;
 609         unsigned int misc_enable, dummy;
 610         unsigned int ht_num;
 611         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 612
 613         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 614         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 615                 return 0;
 616
 617 #ifdef CONFIG_SMP
 618         /* detect which hyperthread we are on */
 619         if (smp_num_siblings == 2) {
 620                 unsigned int ebx, apicid;
 621
 622                 ebx = cpuid_ebx(1);
 623                 apicid = (ebx >> 24) & 0xff;
 624                 ht_num = apicid & 1;
 625         } else
 626 #endif
 627                 ht_num = 0;
 628
 629         /* performance counters are shared resources
 630          * assign each hyperthread its own set
 631          * (re-use the ESCR0 register, seems safe
 632          * and keeps the cccr_val the same)
 633          */
 634         if (!ht_num) {
 635                 /* logical cpu 0 */
 636                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 637                 evntsel_msr = MSR_P4_CRU_ESCR0;
 638                 cccr_msr = MSR_P4_IQ_CCCR0;
 639                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 640         } else {
 641                 /* logical cpu 1 */
 642                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 643                 evntsel_msr = MSR_P4_CRU_ESCR0;
 644                 cccr_msr = MSR_P4_IQ_CCCR1;
 645                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 646         }
 647
 648         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 649                 goto fail;
 650
 651         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 652                 goto fail1;
 653
 654         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 655                 | P4_ESCR_OS
 656                 | P4_ESCR_USR;
 657
 658         cccr_val |= P4_CCCR_THRESHOLD(15)
 659                  | P4_CCCR_COMPLEMENT
 660                  | P4_CCCR_COMPARE
 661                  | P4_CCCR_REQUIRED;
 662
 663         wrmsr(evntsel_msr, evntsel, 0);
 664         wrmsr(cccr_msr, cccr_val, 0);
 665         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 666         apic_write(APIC_LVTPC, APIC_DM_NMI);
 667         cccr_val |= P4_CCCR_ENABLE;
 668         wrmsr(cccr_msr, cccr_val, 0);
 669
 670         wd->perfctr_msr = perfctr_msr;
 671         wd->evntsel_msr = evntsel_msr;
 672         wd->cccr_msr = cccr_msr;
 673         wd->check_bit = 1ULL<<39;
 674         return 1;
 675 fail1:
 676         __release_perfctr_nmi(-1, perfctr_msr);
 677 fail:
 678         return 0;
 679 }
 680
 681 static void stop_p4_watchdog(void)
 682 {
 683         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 684
 685         wrmsr(wd->cccr_msr, 0, 0);
 686         wrmsr(wd->evntsel_msr, 0, 0);
 687
 688         __release_evntsel_nmi(-1, wd->evntsel_msr);
 689         __release_perfctr_nmi(-1, wd->perfctr_msr);
 690 }
 691
 692 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 693 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 694
 695 static int setup_intel_arch_watchdog(void)
 696 {
 697         unsigned int ebx;
 698         union cpuid10_eax eax;
 699         unsigned int unused;
 700         unsigned int perfctr_msr, evntsel_msr;
 701         unsigned int evntsel;
 702         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 703
 704         /*
 705          * Check whether the Architectural PerfMon supports
 706          * Unhalted Core Cycles Event or not.
 707          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 708          */
 709         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 710         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 711             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 712                 goto fail;
 713
 714         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 715         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 716
 717         if (!__reserve_perfctr_nmi(-1, perfctr_msr))
 718                 goto fail;
 719
 720         if (!__reserve_evntsel_nmi(-1, evntsel_msr))
 721                 goto fail1;
 722
 723         wrmsrl(perfctr_msr, 0UL);
 724
 725         evntsel = ARCH_PERFMON_EVENTSEL_INT
 726                 | ARCH_PERFMON_EVENTSEL_OS
 727                 | ARCH_PERFMON_EVENTSEL_USR
 728                 | ARCH_PERFMON_NMI_EVENT_SEL
 729                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 730
 731         /* setup the timer */
 732         wrmsr(evntsel_msr, evntsel, 0);
 733
 734         nmi_hz = adjust_for_32bit_ctr(nmi_hz);
 735         wrmsr(perfctr_msr, (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 736
 737         apic_write(APIC_LVTPC, APIC_DM_NMI);
 738         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 739         wrmsr(evntsel_msr, evntsel, 0);
 740
 741         wd->perfctr_msr = perfctr_msr;
 742         wd->evntsel_msr = evntsel_msr;
 743         wd->cccr_msr = 0;  //unused
 744         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 745         return 1;
 746 fail1:
 747         __release_perfctr_nmi(-1, perfctr_msr);
 748 fail:
 749         return 0;
 750 }
 751
 752 static void stop_intel_arch_watchdog(void)
 753 {
 754         unsigned int ebx;
 755         union cpuid10_eax eax;
 756         unsigned int unused;
 757         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 758
 759         /*
 760          * Check whether the Architectural PerfMon supports
 761          * Unhalted Core Cycles Event or not.
 762          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 763          */
 764         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 765         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 766             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 767                 return;
 768
 769         wrmsr(wd->evntsel_msr, 0, 0);
 770
 771         __release_evntsel_nmi(-1, wd->evntsel_msr);
 772         __release_perfctr_nmi(-1, wd->perfctr_msr);
 773 }
 774
 775 void setup_apic_nmi_watchdog(void *unused)
 776 {
 777         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 778
 779         /* only support LOCAL and IO APICs for now */
 780         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 781             (nmi_watchdog != NMI_IO_APIC))
 782                 return;
 783
 784         if (wd->enabled == 1)
 785                 return;
 786
 787         /* cheap hack to support suspend/resume */
 788         /* if cpu0 is not active neither should the other cpus */
 789         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 790                 return;
 791
 792         if (nmi_watchdog == NMI_LOCAL_APIC) {
 793                 switch (boot_cpu_data.x86_vendor) {
 794                 case X86_VENDOR_AMD:
 795                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 796                                 return;
 797                         if (!setup_k7_watchdog())
 798                                 return;
 799                         break;
 800                 case X86_VENDOR_INTEL:
 801                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 802                                 if (!setup_intel_arch_watchdog())
 803                                         return;
 804                                 break;
 805                         }
 806                         if (!setup_p4_watchdog())
 807                                 return;
 808                         break;
 809                 default:
 810                         return;
 811                 }
 812         }
 813         wd->enabled = 1;
 814         atomic_inc(&nmi_active);
 815 }
 816
 817 void stop_apic_nmi_watchdog(void *unused)
 818 {
 819         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 820
 821         /* only support LOCAL and IO APICs for now */
 822         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 823             (nmi_watchdog != NMI_IO_APIC))
 824                 return;
 825
 826         if (wd->enabled == 0)
 827                 return;
 828
 829         if (nmi_watchdog == NMI_LOCAL_APIC) {
 830                 switch (boot_cpu_data.x86_vendor) {
 831                 case X86_VENDOR_AMD:
 832                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 833                                 return;
 834                         stop_k7_watchdog();
 835                         break;
 836                 case X86_VENDOR_INTEL:
 837                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 838                                 stop_intel_arch_watchdog();
 839                                 break;
 840                         }
 841                         stop_p4_watchdog();
 842                         break;
 843                 default:
 844                         return;
 845                 }
 846         }
 847         wd->enabled = 0;
 848         atomic_dec(&nmi_active);
 849 }
 850
 851 /*
 852  * the best way to detect whether a CPU has a 'hard lockup' problem
 853  * is to check it's local APIC timer IRQ counts. If they are not
 854  * changing then that CPU has some problem.
 855  *
 856  * as these watchdog NMI IRQs are generated on every CPU, we only
 857  * have to check the current processor.
 858  */
 859
 860 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 861 static DEFINE_PER_CPU(local_t, alert_counter);
 862 static DEFINE_PER_CPU(int, nmi_touch);
 863
 864 void touch_nmi_watchdog (void)
 865 {
 866         if (nmi_watchdog > 0) {
 867                 unsigned cpu;
 868
 869                 /*
 870                  * Tell other CPUs to reset their alert counters. We cannot
 871                  * do it ourselves because the alert count increase is not
 872                  * atomic.
 873                  */
 874                 for_each_present_cpu (cpu)
 875                         per_cpu(nmi_touch, cpu) = 1;
 876         }
 877
 878         touch_softlockup_watchdog();
 879 }
 880
 881 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 882 {
 883         int sum;
 884         int touched = 0;
 885         int cpu = smp_processor_id();
 886         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 887         u64 dummy;
 888         int rc=0;
 889
 890         /* check for other users first */
 891         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 892                         == NOTIFY_STOP) {
 893                 rc = 1;
 894                 touched = 1;
 895         }
 896
 897         sum = read_pda(apic_timer_irqs);
 898         if (__get_cpu_var(nmi_touch)) {
 899                 __get_cpu_var(nmi_touch) = 0;
 900                 touched = 1;
 901         }
 902
 903         if (cpu_isset(cpu, backtrace_mask)) {
 904                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 905
 906                 spin_lock(&lock);
 907                 printk("NMI backtrace for cpu %d\n", cpu);
 908                 dump_stack();
 909                 spin_unlock(&lock);
 910                 cpu_clear(cpu, backtrace_mask);
 911         }
 912
 913 #ifdef CONFIG_X86_MCE
 914         /* Could check oops_in_progress here too, but it's safer
 915            not too */
 916         if (atomic_read(&mce_entry) > 0)
 917                 touched = 1;
 918 #endif
 919         /* if the apic timer isn't firing, this cpu isn't doing much */
 920         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 921                 /*
 922                  * Ayiee, looks like this CPU is stuck ...
 923                  * wait a few IRQs (5 seconds) before doing the oops ...
 924                  */
 925                 local_inc(&__get_cpu_var(alert_counter));
 926                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
 927                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
 928                                 panic_on_timeout);
 929         } else {
 930                 __get_cpu_var(last_irq_sum) = sum;
 931                 local_set(&__get_cpu_var(alert_counter), 0);
 932         }
 933
 934         /* see if the nmi watchdog went off */
 935         if (wd->enabled) {
 936                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 937                         rdmsrl(wd->perfctr_msr, dummy);
 938                         if (dummy & wd->check_bit){
 939                                 /* this wasn't a watchdog timer interrupt */
 940                                 goto done;
 941                         }
 942
 943                         /* only Intel uses the cccr msr */
 944                         if (wd->cccr_msr != 0) {
 945                                 /*
 946                                  * P4 quirks:
 947                                  * - An overflown perfctr will assert its interrupt
 948                                  *   until the OVF flag in its CCCR is cleared.
 949                                  * - LVTPC is masked on interrupt and must be
 950                                  *   unmasked by the LVTPC handler.
 951                                  */
 952                                 rdmsrl(wd->cccr_msr, dummy);
 953                                 dummy &= ~P4_CCCR_OVF;
 954                                 wrmsrl(wd->cccr_msr, dummy);
 955                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 956                                 /* start the cycle over again */
 957                                 wrmsrl(wd->perfctr_msr,
 958                                        -((u64)cpu_khz * 1000 / nmi_hz));
 959                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 960                                 /*
 961                                  * ArchPerfom/Core Duo needs to re-unmask
 962                                  * the apic vector
 963                                  */
 964                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 965                                 /* ARCH_PERFMON has 32 bit counter writes */
 966                                 wrmsr(wd->perfctr_msr,
 967                                      (u32)(-((u64)cpu_khz * 1000 / nmi_hz)), 0);
 968                         } else {
 969                                 /* start the cycle over again */
 970                                 wrmsrl(wd->perfctr_msr,
 971                                        -((u64)cpu_khz * 1000 / nmi_hz));
 972                         }
 973                         rc = 1;
 974                 } else  if (nmi_watchdog == NMI_IO_APIC) {
 975                         /* don't know how to accurately check for this.
 976                          * just assume it was a watchdog timer interrupt
 977                          * This matches the old behaviour.
 978                          */
 979                         rc = 1;
 980                 } else
 981                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 982         }
 983 done:
 984         return rc;
 985 }
 986
 987 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 988 {
 989         nmi_enter();
 990         add_pda(__nmi_count,1);
 991         default_do_nmi(regs);
 992         nmi_exit();
 993 }
 994
 995 int do_nmi_callback(struct pt_regs * regs, int cpu)
 996 {
 997 #ifdef CONFIG_SYSCTL
 998         if (unknown_nmi_panic)
 999                 return unknown_nmi_panic_callback(regs, cpu);
1000 #endif
1001         return 0;
1002 }
1003
1004 #ifdef CONFIG_SYSCTL
1005
1006 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
1007 {
1008         unsigned char reason = get_nmi_reason();
1009         char buf[64];
1010
1011         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
1012         die_nmi(buf, regs, 1);  /* Always panic here */
1013         return 0;
1014 }
1015
1016 /*
1017  * proc handler for /proc/sys/kernel/nmi
1018  */
1019 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
1020                         void __user *buffer, size_t *length, loff_t *ppos)
1021 {
1022         int old_state;
1023
1024         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
1025         old_state = nmi_watchdog_enabled;
1026         proc_dointvec(table, write, file, buffer, length, ppos);
1027         if (!!old_state == !!nmi_watchdog_enabled)
1028                 return 0;
1029
1030         if (atomic_read(&nmi_active) < 0) {
1031                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
1032                 return -EIO;
1033         }
1034
1035         /* if nmi_watchdog is not set yet, then set it */
1036         nmi_watchdog_default();
1037
1038         if (nmi_watchdog == NMI_LOCAL_APIC) {
1039                 if (nmi_watchdog_enabled)
1040                         enable_lapic_nmi_watchdog();
1041                 else
1042                         disable_lapic_nmi_watchdog();
1043         } else {
1044                 printk( KERN_WARNING
1045                         "NMI watchdog doesn't know what hardware to touch\n");
1046                 return -EIO;
1047         }
1048         return 0;
1049 }
1050
1051 #endif
1052
1053 void __trigger_all_cpu_backtrace(void)
1054 {
1055         int i;
1056
1057         backtrace_mask = cpu_online_map;
1058         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
1059         for (i = 0; i < 10 * 1000; i++) {
1060                 if (cpus_empty(backtrace_mask))
1061                         break;
1062                 mdelay(1);
1063         }
1064 }
1065
1066 EXPORT_SYMBOL(nmi_active);
1067 EXPORT_SYMBOL(nmi_watchdog);
1068 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
1069 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
1070 EXPORT_SYMBOL(reserve_perfctr_nmi);
1071 EXPORT_SYMBOL(release_perfctr_nmi);
1072 EXPORT_SYMBOL(reserve_evntsel_nmi);
1073 EXPORT_SYMBOL(release_evntsel_nmi);
1074 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
1075 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
1076 EXPORT_SYMBOL(touch_nmi_watchdog);