git.rot13.org Git - goodfet/blob - client/GoodFETAT91X40.py

   1 from GoodFETARM7 import *
   2 import ATMEL_USART as usart
   3 """
   4 This is the ARM7 series of microcontrollers from Atmel, including:
   5 * AT91M40800
   6 * AT91R40807
   7 * AT91M40807
   8 * AT91R40008
   9
  10 """
  11 ##### FLASH UPLOADER CODE
  12 EBI_BASE =       0xFFE00000
  13 EBI_OFF_CSR0 =   0x0
  14 EBI_OFF_CSR1 =   0x4
  15 EBI_OFF_CSR2 =   0x8
  16 EBI_OFF_CSR3 =   0xc
  17 EBI_OFF_CSR4 =   0x10
  18 EBI_OFF_CSR5 =   0x14
  19 EBI_OFF_CSR6 =   0x18
  20 EBI_OFF_CSR7 =   0x1c
  21 EBI_CSR0_MASK =  0xFFFF0000
  22 EBI_OFF_RCR =    0x20
  23 EBI_OFF_MCR =    0x24
  24
  25 EBI_CSR0 =      EBI_BASE + EBI_OFF_CSR0
  26 EBI_CSR1 =      EBI_BASE + EBI_OFF_CSR1
  27 EBI_CSR2 =      EBI_BASE + EBI_OFF_CSR2
  28 EBI_CSR3 =      EBI_BASE + EBI_OFF_CSR3
  29 EBI_CSR4 =      EBI_BASE + EBI_OFF_CSR4
  30 EBI_CSR5 =      EBI_BASE + EBI_OFF_CSR5
  31 EBI_CSR6 =      EBI_BASE + EBI_OFF_CSR6
  32 EBI_CSR7 =      EBI_BASE + EBI_OFF_CSR7
  33 EBI_MCR =       EBI_BASE + EBI_OFF_MCR
  34
  35 REMAP_CMD =      0x00000001
  36 MEM_CTRL_VAL =   0x00000006
  37
  38
  39 SF_CHIP_ID =     0xFFF00000         # AT91R40 series, not sure on others
  40 SF_CIDR_MASK =   0x0FFFFF00
  41
  42 PS_BASE =        0xFFFF4000
  43 PS_CR =          PS_BASE
  44 PS_PCER =        PS_BASE + 0x4
  45 PS_PCDR =        PS_BASE + 0x8
  46 PS_PCSR =        PS_BASE + 0xC
  47 PS_US0 =         1<<2
  48 PS_US1 =         1<<3
  49 PS_TC0 =         1<<4
  50 PS_TC1 =         1<<5
  51 PS_TC2 =         1<<6
  52 PS_PIO =         1<<8
  53
  54 AIC_INT_SOURCES = (
  55         ("FIQ","Fast Interrupt"),
  56         ("SWIRQ","Software Interrupt"),
  57         ("US0IRQ","USART Channel 0 Interrupt"),
  58         ("US1IRQ","USART Channel 1 Interrupt"),
  59         ("TC0IRQ","Timer Channel 0 Interrupt"),
  60         ("TC1IRQ","Timer Channel 1 Interrupt"),
  61         ("TC2IRQ","Timer Channel 2 Interrupt"),
  62         ("WDIRQ", "Watchdog Interrupt"),
  63         ("PIOIRQ","Parallel I/O Controller Interrupt"),
  64         (None,None),
  65         (None,None),
  66         (None,None),
  67         (None,None),
  68         (None,None),
  69         (None,None),
  70         (None,None),
  71         ("IRQ0","External Interrupt 0"),
  72         ("IRQ1","External Interrupt 0"),
  73         ("IRQ0","External Interrupt 0"),
  74         (None,None),
  75         (None,None),
  76         (None,None),
  77         (None,None),
  78         (None,None),
  79         (None,None),
  80         (None,None),
  81         (None,None),
  82         (None,None),
  83         (None,None),
  84         (None,None),
  85         (None,None),
  86         (None,None),
  87         )
  88
  89 def aic_smr_decode(smr):
  90     output = ["Interrupt Priority: %s"%(smr&7),
  91             "Interrupt Source Type: %s"%("Low Level Sensitive","Negative Edge Triggered","High Level Sensitive","Positive Edge Triggered")[(smr>>5)],
  92             ]
  93     return "\n".join(output)
  94
  95 AIC_BASE = 0xFFFFF000
  96 AIC_SMR = [(AIC_BASE+(x*4), "Source Mode Register %d"%x)  for x in xrange(32)]
  97 AIC_SVR = [(AIC_BASE+0x80+(x*4), "Source Vector Register %d"%x)  for x in xrange(32)]
  98 AIC_IVR = AIC_BASE + 0x100
  99 AIC_FVR = AIC_BASE + 0x104
 100 AIC_ISR = AIC_BASE + 0x108
 101 AIC_IPR = AIC_BASE + 0x10c
 102 AIC_IMR = AIC_BASE + 0x110
 103 AIC_CISR = AIC_BASE + 0x114
 104 AIC_IECR = AIC_BASE + 0x120
 105 AIC_IDCR = AIC_BASE + 0x124
 106 AIC_ICCR = AIC_BASE + 0x128
 107 AIC_ISCR = AIC_BASE + 0x12c
 108 AIC_EOICR = AIC_BASE + 0x130
 109 AIC_SPU = AIC_BASE + 0x134
 110
 111
 112 PIO_BASE = 0xFFFF0000
 113 PIO_PER =   PIO_BASE + 0x0
 114 PIO_PDR =   PIO_BASE + 0x4
 115 PIO_PSR =   PIO_BASE + 0x8
 116 PIO_OER =   PIO_BASE + 0x10
 117 PIO_ODR =   PIO_BASE + 0x14
 118 PIO_OSR =   PIO_BASE + 0x18
 119 PIO_SODR =  PIO_BASE + 0x30
 120 PIO_CODR =  PIO_BASE + 0x34
 121 PIO_ODSR =  PIO_BASE + 0x38
 122 PIO_CDSR =  PIO_BASE + 0x3c
 123 PIO_IER =   PIO_BASE + 0x40
 124 PIO_IDR =   PIO_BASE + 0x44
 125 PIO_IMR =   PIO_BASE + 0x48
 126 PIO_ISR =   PIO_BASE + 0x4c
 127
 128 WD_BASE = 0xFFFF8000
 129 WD_OMR  =   WD_BASE + 0x0
 130 WD_CMR  =   WD_BASE + 0x4
 131 WD_CR   =   WD_BASE + 0x8
 132 WD_SR   =   WD_BASE + 0xc
 133
 134 SF_BASE = 0xFFF00000
 135 SF_CIDR =   SF_BASE + 0x0
 136 SF_EXID =   SF_BASE + 0x4
 137 SF_RSR =    SF_BASE + 0x8
 138 SF_MMR =    SF_BASE + 0xC
 139 SF_PMR =    SF_BASE + 0x18
 140
 141 #* Flash
 142 FLASH_BASE_ADDR =    0x1000000
 143 WAIT =               300000
 144 FLASH_CODE_MASK =    0x000000FF
 145
 146 #*Flash AT49 codes
 147 ATMEL_MANUFACTURED =         0x001F
 148 FLASH_AT49BV_UNKNOW =        0xFFFF
 149 FLASH_AT49BV8011 =           0x00CB
 150 FLASH_AT49BV8011T =          0x004A
 151 FLASH_AT49BV16x4 =           0x00C0
 152 FLASH_AT49BV16x4T =          0x00C2
 153
 154 #*Flash AT29 codes
 155 FLASH_AT29LV1024 =               0X26
 156 FLASH_AT29C020 =                 0XDA
 157
 158 #* Flash Program information
 159 FLASH_PRG_SIZE =     0x800   #* 2Kbytes
 160 FLASH_PRG_DEST =     0x20    #* Address on the target
 161 START_PRG =          0x20
 162
 163 #* Parameter for Flash_XV_Send_Data functions
 164 ERASE =  1
 165 PROGRAM =0
 166
 167 MIRROR =     1
 168 NO_MIRROR =  0
 169
 170 ERASE_DATA = 0
 171
 172 #* Load program parameters
 173 NB_REG =     13
 174 SIZE_DATA =  4
 175
 176 #* Flash LV Send Data parameters
 177 SIZE_256_BYTES = 0x100
 178 PACKET_SIZE =64
 179
 180 NB_PRG =     3
 181
 182 #* Periph
 183 EBI =    0
 184 PLL =    1
 185
 186 #* Targets
 187 EB40 =   0x04080700
 188 EB40A =  0x04000800
 189 EB42 =   0x04280000
 190 EB55 =   0x05580000
 191 EB63 =   0x06320000
 192 EBMASK = 0x0fffff00
 193
 194 NB_TARGET_SUPPORTED =    6
 195
 196 #* Flash type
 197 FLASH_LV =   0
 198 FLASH_BV =   1
 199
 200 #* Flash Program Address
 201 FLASH_LV_PRG =   0x01018000
 202 FLASH_BV_PRG =   0x0101A000
 203
 204 EBI_READ    = 4
 205 EBI_WRITE   = 2
 206
 207 ebi_memory_map_items = {
 208         EBI_OFF_CSR0:("Chip Select Register 0", "EBI_CSR0", EBI_READ|EBI_WRITE,0x0000203e),
 209         EBI_OFF_CSR1:("Chip Select Register 1", "EBI_CSR1", EBI_READ|EBI_WRITE,0x10000000),
 210         EBI_OFF_CSR2:("Chip Select Register 2", "EBI_CSR2", EBI_READ|EBI_WRITE,0x20000000),
 211         EBI_OFF_CSR3:("Chip Select Register 3", "EBI_CSR3", EBI_READ|EBI_WRITE,0x30000000),
 212         EBI_OFF_CSR4:("Chip Select Register 4", "EBI_CSR4", EBI_READ|EBI_WRITE,0x40000000),
 213         EBI_OFF_CSR5:("Chip Select Register 5", "EBI_CSR5", EBI_READ|EBI_WRITE,0x50000000),
 214         EBI_OFF_CSR6:("Chip Select Register 6", "EBI_CSR6", EBI_READ|EBI_WRITE,0x60000000),
 215         EBI_OFF_CSR7:("Chip Select Register 7", "EBI_CSR7", EBI_READ|EBI_WRITE,0x70000000),
 216         EBI_OFF_MCR: ("Memory Control Register","EBI_MCR",  EBI_READ|EBI_WRITE,0),
 217         }
 218
 219 def ebi_csr_decode(reg):
 220     addr = reg>>20
 221     csen = (reg>>13)&1
 222     bat =  (reg>>12)&1
 223     tdf =  (reg>>9)&7
 224     pages =(reg>>7)&3
 225     wse =  (reg>>5)&1
 226     nws =  (reg>>2)&7
 227     dbw =  (reg&3)
 228     return [ addr, csen, bat, tdf, pages, wse, nws, dbw]
 229
 230 def ebi_csr_decode_str(reg):
 231     (addr,
 232     csen,
 233     bat,
 234     tdf,
 235     pages,
 236     wse,
 237     nws,
 238     dbw) = ebi_csr_decode(reg)
 239     output = ["(register: %x)"%reg,
 240             "Base Address: %s"%hex(addr<<20),
 241             "Chip Select: %s"%("False","True")[csen],
 242             "Byte Access Type: %s"%("Byte-Write","Byte-Access")[bat],
 243             "Data Float Output Time: %d cycles added"%tdf,
 244             "Page Size: %d MB"%(1,4,16,64)[pages],
 245             "Wait State: %s"%("disabled","enabled")[wse],
 246             "Wait States: %d"%nws,
 247             "Data Bus Size: %d bits"%(0,16,8,0)[dbw],
 248             ]
 249     return "\n".join(output)
 250
 251 mcr_ale = {
 252         0: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 253         1: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 254         2: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 255         3: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 256         4: ("A20,A21,A22", 8, "CS4", "EBI_ALE_8M"),
 257         5: ("A20,A21", 4, "CS4,CS5", "EBI_ALE_4M"),
 258         6: ("A20", 2, "CS4,CS5,CS6", "EBI_ALE_2M"),
 259         7: ("None", 1, "CS4,CS5,CS6,CS7", "EBI_ALE_1M"),
 260         }
 261
 262 def mcr_decode(mcr):
 263     validAddrBits,maxAddrSpace,validCS,codeLabel = mcr_ale[mcr&7]
 264     drp = mcr>>4
 265     #print hex(drp)
 266     if drp and drp != 1:
 267         drp = 2
 268         return (validAddrBits, maxAddrSpace, validCS, codeLabel, drp)
 269
 270 def mcr_decode_str(mcr):
 271     ( validAddrBits, maxAddrSpace, validCS, codeLabel, drp) = mcr_decode(mcr)
 272     output = [
 273             "(register: %x)"%mcr,
 274             "Valid Address Bits: %s"%validAddrBits,
 275             "Maximum Address Space: 0x%x MB"%maxAddrSpace,
 276             "Valid Chip Select: %s"%validCS,
 277             "Code Label:  %s"%codeLabel,
 278             ("Standard Read Protocol for all external memory devices enabled (EBI_DRP_STANDARD)","Early Read Protocol for all external memory devices enabled (EBI_DRP_EARLY)","Invalid mcr")[drp]
 279             ]
 280     return "\n".join(output)
 281
 282 def wd_omr_decode(omr):
 283         return (omr>>4, (omr>>3)&1, (omr>>2)&1, (omr>>1)&1, omr&1)
 284
 285 def wd_omr_decode_str(omr):
 286     ( okey, esig, int, rst, wdog ) = wd_omr_decode(omr)
 287     return "\n".join([
 288             "Overflow Access Key (OKEY): %x"%(okey),
 289             "External Signal (EXTEN): %s"%("disabled","enabled")[esig],
 290             "Interrupt (IRQEN): %s"%("disabled","enabled")[int],
 291             "Reset (RSTEN): %s"%("disabled","enabled")[rst],
 292             "Watch Dog (WDEN): %s"%("disabled","enabled")[wdog],
 293             ])
 294
 295 def wd_cmr_decode(cmr):
 296     return "MCK/%d"%(8,32,128,1024)[(cmr>>2)&0xf]
 297
 298
 299
 300
 301
 302 class GoodFETAT91X40(GoodFETARM7):
 303     def __init__(self):
 304         GoodFETARM7.__init__(self)
 305         self.usart0 = usart.USART(usart.USART0_BASE)
 306         self.usart1 = usart.USART(usart.USART1_BASE)
 307
 308     def halt(self, disableWD=True):
 309         GoodFETARM7.halt(self)
 310         if not disableWD: return
 311
 312         #Disable Watch Dog
 313         self.disableWatchDog()
 314
 315     def resume(self, enableWD=False):
 316         GoodFETARM7.resume(self)
 317         if not enableWD: return
 318
 319         self.enableWatchDog()
 320
 321     def getChipSelectReg(self, chipnum):
 322         addr = EBI_BASE + (chipnum*4)
 323         reg, = self.ARMreadChunk(addr,1)
 324         return reg
 325     def getChipSelectRegstr(self, chipnum):
 326         return ebi_csr_decode_str(self.getChipSelectReg(chipnum))
 327     def getChipSelectReglist(self, chipnum):
 328         return ebi_csr_decode(self.getChipSelectReg(chipnum))
 329     def setChipSelectReg(self, chipnum, value):
 330         addr = EBI_BASE + (chipnum*4)
 331         self.ARMwriteChunk(addr,[value])
 332
 333     def getEBIMemoryMap(self):
 334         keys = ebi_memory_map_items.keys()
 335         keys.sort()
 336         output = [ "EBI Memory Map"]
 337         for x in xrange(8):
 338             desc,name,rw,default = ebi_memory_map_items[x*4]
 339             output.append("\nMAP: %s (%s) - default: %x\n%s"%(name,desc,default,self.getChipSelectRegstr(x)))
 340         return "\n".join(output)
 341     def setRemap(self):
 342         self.ARMwriteChunk(EBI_BASE + EBI_OFF_RCR,[REMAP_CMD])
 343     def getMemoryControlRegister(self):
 344         mcr, = self.ARMreadMem(EBI_MCR)
 345         return mcr
 346     def getMemoryControlRegisterstr(self):
 347         return mcr_decode_str(self.getMemoryControlRegister())
 348     def getEBIMCR(self):
 349         print "EBI Memory Control Register\n"
 350         print self.getMemoryControlRegisterstr()
 351
 352     def getInterruptSourceModeReg(self, regnum):
 353         regval = self.ARMreadMem(AIC_SMR[regnum][0])
 354         return retval
 355     def getInterruptSourceModeRegstr(self, regnum):
 356         return aic_smr_decode(self.getInterruptSourceModeReg(regnum))
 357     def setInterruptSourceModeReg(self, regnum, val):
 358         self.ARMwriteMem(AIC_SMR[regnum][0], val)
 359
 360     def getInterruptSourceVectorReg(self, regnum):
 361         regval = self.ARMreadMem(AIC_SVR[regnum][0])
 362         return retval
 363     def setInterruptSourceModeReg(self, regnum, val):
 364         self.ARMwriteMem(AIC_SVR[regnum][0], val)
 365
 366     def getIRQVectorReg(self):
 367         return self.ARMreadMem(AIC_IVR)
 368     def getFIQVectorReg(self):
 369         return self.ARMreadMem(AIC_FVR)
 370
 371     def getInterruptStatusReg(self):
 372         return self.ARMreadMem(AIC_ISR)
 373     def getInterruptPendingReg(self):
 374         return self.ARMreadMem(AIC_FSR)
 375     def getInterruptMaskReg(self):
 376         return self.ARMreadMem(AIC_IMR)
 377     def getCoreInterruptStatusReg(self):
 378         return self.ARMreadMem(AIC_CISR)
 379     def enableInterrupt(self, interrupt):
 380         self.ARMwriteMem(AIC_IECR, 1<<interrupt)
 381     def disableInterrupt(self, interrupt):
 382         self.ARMwriteMem(AIC_IDCR, 1<<interrupt)
 383     def setInterruptCommandReg(self, interrupt):
 384         self.ARMwriteMem(AIC_ISCR, 1<<interrupt)
 385     def clearInterruptCommandReg(self, interrupt):
 386         self.ARMwriteMem(AIC_ICCR, 1<<interrupt)
 387     def clearCurrentInterrupt(self):
 388         self.ARMwriteMem(AIC_EOICR, 1<<interrupt)
 389     def getSpuriousVectorReg(self):
 390         return self.ARMreadMem(AIC_SPU)
 391     def setSpuriousVectorReg(self, val):
 392         return self.ARMreadMem(AIC_SPU)
 393
 394     def enablePIOpin(self, mask):
 395         self.ARMwriteMem(PIO_PER, mask)
 396     def disablePIOpin(self, mask):
 397         self.ARMwriteMem(PIO_PDR, mask)
 398     def getPIOstatus(self):
 399         return self.ARMreadMem(PIO_PSR)
 400     def enablePIOoutput(self,mask):
 401         self.ARMwriteMem(PIO_OER, mask)
 402     def disablePIOoutput(self,mask):
 403         self.ARMwriteMem(PIO_ODR, mask)
 404     def getPIOoutputStatus(self):
 405         return self.ARMreadMem(PIO_OSR)
 406
 407     def setOutputPin(self,mask):
 408         self.ARMwriteMem(PIO_SODR, mask)
 409     def clearOutputPin(self,mask):
 410         self.ARMwriteMem(PIO_CODR, mask)
 411     def getOutputDataStatusReg(self):
 412         return self.ARMreadMem(PIO_ODSR)
 413     def getPinDataStatusReg(self):
 414         return self.ARMreadMem(PIO_PDSR)
 415     def enablePIOinterrupt(self, mask):
 416         self.ARMwriteMem(PIO_IER, mask)
 417     def disablePIOinterrupt(self, mask):
 418         self.ARMwriteMem(PIO_IDR, mask)
 419     def getPIOinterruptMaskReg(self):
 420         return self.ARMreadMem(PIO_IMR)
 421     def getPIOinteruptStatusReg(self):
 422         return self.ARMreadMem(PIO_ODSR)
 423
 424
 425     def getWatchDogOverflowModeReg(self):
 426         return self.ARMreadMem(WD_OMR)
 427     def getWatchDogOverflowModeStr(self):
 428         return wd_omr_decode_str(self.getWatchDogOverflowModeReg()[0])
 429     def setWatchDogOverflowModeReg(self, mode=0x00002340):
 430         self.ARMwriteMem(WD_OMR, [mode])
 431     def getWatchDogClockModeReg(self):
 432         return self.ARMreadMem(WD_CMR)[0]
 433     def setWatchDogClockModeReg(self, mode=0x06e):
 434         self.ARMwriteMem(WD_CMR, [mode])
 435     def setWatchDogControlReg(self, mode=0xC071):
 436         self.ARMwriteMem(WD_CR, [mode])
 437     def getWatchDogStatusReg(self):
 438         return self.ARMreadMem(WD_SR)[0]
 439     def disableWatchDog(self):
 440         # 0x234 in OKEY enables writing and 0 in lowest nibble disables
 441         self.setWatchDogOverflowModeReg()
 442     def enableWatchDog(self):
 443         # Initialize the WD Clock Mode Register
 444         self.setWatchDogClockModeReg(mode=0x0000373c)
 445         # Restart the timer
 446         self.setWatchDogControlReg(mode=0x0000c071)
 447         # Enable the watchdog
 448         self.setWatchDogOverflowModeReg(mode=0x00002340)
 449     def statWatchDog(self):
 450         print "Status Watch Dog:"
 451         print "Register Value: 0b%s" % '{0:032b}'.format(self.getWatchDogOverflowModeReg()[0])
 452         print self.getWatchDogOverflowModeStr()
 453         print "Clock Mode Reg: %x" % self.getWatchDogClockModeReg()
 454         print "Status Reg: %x" % self.getWatchDogStatusReg()
 455     def checkWatchDog(self):
 456         return self.getWatchDogOverflowModeStr()
 457
 458
 459     def getChipID(self):
 460         chipid = self.ARMreadMem(SF_CIDR,1)
 461         return chipid[0]
 462     def getResetStatusReg(self):
 463         return self.ARMreadMem(SF_RSR)
 464     def getMemoryModeReg(self):
 465         return self.ARMreadMem(SF_MMR)
 466     def setMemoryModeReg(self, val=0):
 467         self.ARMwriteMem(SF_MMR, val)
 468     def getProtectModeReg(self):
 469         return self.ARMreadMem(SF_PMR)
 470     def setProtectModeReg(self, val=0x27a80000):
 471         self.ARMwriteMem(SF_PMR, val)
 472
 473
 474
 475
 476
 477
 478
 479     def ARMwriteFirmware(self, firmware):
 480         self.halt()
 481         chipid = self.ARMgetChipID()
 482         # FIXME: initialize PLL or EBI
 483         self.ARMmassErase(chipid)
 484         self.ARMset_regCPSR(PM_svc)   # set supervisor mode
 485         # FIXME: download the "flash identifier" program into target RAM
 486         self.ARMsetPC(PROGGYBASE)
 487         self.release()
 488         # get manufacturer crap through DCC (really??  screw this...)
 489         self.halt()
 490         if (self.ARMget_regCPSR() & PM_svc != PM_svc):
 491             raise Exception("No longer in Supervisor mode after firmware upload")
 492         # FIXME: download the downloader program into target RAM
 493         self.ARMsetPC(PROGGYBASE)
 494         self.release()
 495         # FIXME: use DCC to upload the new firmware
 496
 497     def clearFlash(self):
 498         pass
 499
 500     def readPages(self, addr, pagecount, pagesz=(1024*1024)):
 501         global pages;
 502         pages = []
 503         for page in xrange(pagecount):
 504             pages.append(self.ARMreadChunk(addr+(pagesz*page), pagesz))
 505         return pages
 506
 507
 508 ######### command line stuff #########
 509
 510 from GoodFETARM7 import *
 511
 512 def at91x40_main():
 513     ''' this function should be called from command line app '''
 514     #Initialize FET and set baud rate
 515     client=GoodFETAT91X40()
 516     client.serInit()
 517
 518     client.setup()
 519     client.start()
 520
 521     at91x40_cli_handler(client, sys.argv)
 522
 523 def at91x40_cli_handler(client, argv):
 524
 525     if(argv[1]=="chipRegStr"):
 526         client.halt()
 527         print "#####"
 528         print client.getChipSelectRegstr(int(argv[2]))
 529         print "#####"
 530         client.resume()
 531
 532     if(argv[1]=="chipRegList"):
 533         client.halt()
 534         print "#####"
 535         print client.getChipSelectReglist(int(argv[2]))
 536         print "#####"
 537         client.resume()
 538
 539     if(argv[1]=="chipRegValue"):
 540         client.halt()
 541         print "#####"
 542         print "Chip Register Value:",hex(client.getChipSelectReg(int(argv[2])))
 543         print "#####"
 544
 545     if(argv[1]=="ecdump"):
 546         f = argv[2]
 547         start=0x00000000
 548         stop=0xFFFFFFFF
 549         if(len(argv)>3):
 550             start=int(argv[3],16)
 551         if(len(argv)>4):
 552             stop=int(argv[4],16)
 553
 554         ##############################3
 555         # Error checking requires a special register
 556         # Should an error occur while reading from the chip's memory
 557         # These values will help to test if the chip is working and
 558         # the memory is mapped properly before continuing
 559         # Use the chipRegStr verb to determine the value of the
 560         # Special Register when the chip is operating normally
 561         # Example: ./goodfet.at91x40 chipRegValue 1
 562         ##############################3
 563         # user$ ./goodfet.at91x40 chipRegValue 1
 564         # Identifying Target:
 565         # # DEBUG 0x120
 566         # Chip IDCODE: 0x1f0f0f0f
 567         #     ver: 1
 568         #     partno: f0f0
 569         #     mfgid: 787
 570         #
 571         # Debug Status:   Interrupts Enabled (or not?)
 572         #
 573         # #####
 574         # Chip Register Value: 0x10000000
 575         # #####
 576         ##############################
 577         special_reg_num=1
 578         special_addr=0x010000000
 579         if(len(argv)>5):
 580             # Yes, this requires that you set the start and stop addresses
 581             special_reg_num=int(argv[5])
 582             special_addr=int(argv[6],16)
 583
 584         print "Dumping from %04x to %04x as %s." % (start,stop,f)
 585         #h = IntelHex16bit(None)
 586         # FIXME: get mcu state and return it to that state
 587         client.halt()
 588
 589         h = IntelHex(None)
 590         i=start
 591         while i<=stop:
 592             err_cnt = 0
 593             #data=client.ARMreadMem(i, 48)
 594             try:
 595                 data=client.ARMreadChunk(i, 48, verbose=0)
 596                 print "Dumped %06x."%i
 597                 for dword in data:
 598                     if i<=stop and dword != 0xdeadbeef:
 599                         h.puts( i, struct.pack("<I", dword) )
 600                         err_cnt = 0
 601                     i+=4
 602             # FIXME: get mcu state and return it to that state
 603             except:
 604                 # Handle exceptions by counting errors after pausing to let ARM settle
 605                 err_cnt = 1
 606                 fail = 0
 607                 while err_cnt:
 608                     time.sleep(.25)
 609                     if err_cnt == 100:
 610                         print "Unknown error occurred at least 100 times. Resync did not work. Writing incomplete data to file."
 611                         fail = 1
 612                         break
 613                     else:
 614                         try:
 615                             print "Unknown error during read. Resync and retry."
 616
 617                             # If we error out several times then reset the chip and restart
 618                             # This uses a special register value from a Chip Select Register
 619                             # to test that the chip is in the operation state we expect
 620                             if not ((err_cnt+1) % 2):
 621                                 reset_cnt = 0
 622                                 while True:
 623                                     print "    Reset:",reset_cnt
 624                                     check_addr = client.getChipSelectReg(special_reg_num)
 625                                     print "    Special Addr:",hex(special_addr)
 626                                     print "    Check Addr:",hex(check_addr)
 627                                     if (special_addr == check_addr):
 628                                         break
 629                                     if reset_cnt == 10:
 630                                         reset_cnt = 0
 631                                         print "    Resetting Target"
 632                                         client.ARMresettarget(1000)
 633                                         client.halt()
 634                                     reset_cnt += 1
 635                                     time.sleep(.25)
 636                             else:
 637                                 #Resync ARM and Watch Dog
 638                                 client.resume()
 639                                 client.halt()
 640
 641                             #Disable Watch Dog
 642                             if client.checkWatchDog():
 643                                 client.disableWatchDog()
 644                             err_cnt = 0
 645                         except:
 646                             err_cnt += 1
 647                             pass
 648                 if fail:
 649                     break
 650
 651         client.resume()
 652         h.write_hex_file(f)
 653
 654
 655
 656     if(argv[1]=="memorymap"):
 657         client.halt()
 658         print client.getEBIMCR()
 659         print ""
 660         print client.getEBIMemoryMap()
 661         client.resume()
 662
 663     if(argv[1]=="memorycontrolreg"):
 664         client.halt()
 665         print client.getEBIMCR()
 666         client.resume()
 667
 668
 669
 670     if(argv[1]=="stat_watchdog"):
 671         client.halt()
 672         print "Watch Dog Status:"
 673         print "--"
 674         client.statWatchDog()
 675         client.resume()
 676
 677     if(argv[1]=="test_disable_watchdog"):
 678         client.halt()
 679         print "Status Watch Dog:"
 680         client.statWatchDog()
 681         print "--"
 682         print "Disabling Watchdog Timer:"
 683         client.disableWatchDog()
 684         time.sleep(2) # pause to settle
 685         print "\nChecking:"
 686         client.statWatchDog()
 687         print "--"
 688         print "Done. Resume may re-enable Watch Dog."
 689         client.resume()
 690
 691     # anything we didn't provide from arm7:
 692     arm7_cli_handler(client, argv)
 693
 694     #client.ARMreleasecpu()
 695     #client.ARMstop()
 696
 697
 698 if __name__ == "__main__":
 699     if(len(sys.argv)==1):
 700         at91x40_syntax()
 701
 702     else:
 703         at91x40_main()
 704
 705