git.rot13.org Git - goodfet/blob - client/GoodFETAT91X40.py

   1 from GoodFETARM7 import *
   2 """
   3 This is the ARM7 series of microcontrollers from Atmel, including:
   4 * AT91M40800
   5 * AT91R40807
   6 * AT91M40807
   7 * AT91R40008
   8
   9 """
  10 ##### FLASH UPLOADER CODE
  11 EBI_BASE =       0xFFE00000
  12 EBI_OFF_CSR0 =   0x0
  13 EBI_OFF_CSR1 =   0x4
  14 EBI_OFF_CSR2 =   0x8
  15 EBI_OFF_CSR3 =   0xc
  16 EBI_OFF_CSR4 =   0x10
  17 EBI_OFF_CSR5 =   0x14
  18 EBI_OFF_CSR6 =   0x18
  19 EBI_OFF_CSR7 =   0x1c
  20 EBI_CSR0_MASK =  0xFFFF0000
  21 EBI_OFF_RCR =    0x20
  22 EBI_OFF_MCR =    0x24
  23
  24 EBI_CSR0 =      EBI_BASE + EBI_OFF_CSR0
  25 EBI_CSR1 =      EBI_BASE + EBI_OFF_CSR1
  26 EBI_CSR2 =      EBI_BASE + EBI_OFF_CSR2
  27 EBI_CSR3 =      EBI_BASE + EBI_OFF_CSR3
  28 EBI_CSR4 =      EBI_BASE + EBI_OFF_CSR4
  29 EBI_CSR5 =      EBI_BASE + EBI_OFF_CSR5
  30 EBI_CSR6 =      EBI_BASE + EBI_OFF_CSR6
  31 EBI_CSR7 =      EBI_BASE + EBI_OFF_CSR7
  32 EBI_MCR =       EBI_BASE + EBI_OFF_MCR
  33
  34 REMAP_CMD =      0x00000001
  35 MEM_CTRL_VAL =   0x00000006
  36
  37
  38 SF_CHIP_ID =     0xFFF00000         # AT91R40 series, not sure on others
  39 SF_CIDR_MASK =   0x0FFFFF00
  40
  41 PS_BASE =        0xFFFF4000
  42 PS_CR =          PS_BASE
  43 PS_PCER =        PS_BASE + 0x4
  44 PS_PCDR =        PS_BASE + 0x8
  45 PS_PCSR =        PS_BASE + 0xC
  46 PS_US0 =         1<<2
  47 PS_US1 =         1<<3
  48 PS_TC0 =         1<<4
  49 PS_TC1 =         1<<5
  50 PS_TC2 =         1<<6
  51 PS_PIO =         1<<8
  52
  53 AIC_INT_SOURCES = (
  54         ("FIQ","Fast Interrupt"),
  55         ("SWIRQ","Software Interrupt"),
  56         ("US0IRQ","USART Channel 0 Interrupt"),
  57         ("US1IRQ","USART Channel 1 Interrupt"),
  58         ("TC0IRQ","Timer Channel 0 Interrupt"),
  59         ("TC1IRQ","Timer Channel 1 Interrupt"),
  60         ("TC2IRQ","Timer Channel 2 Interrupt"),
  61         ("WDIRQ", "Watchdog Interrupt"),
  62         ("PIOIRQ","Parallel I/O Controller Interrupt"),
  63         (None,None),
  64         (None,None),
  65         (None,None),
  66         (None,None),
  67         (None,None),
  68         (None,None),
  69         (None,None),
  70         ("IRQ0","External Interrupt 0"),
  71         ("IRQ1","External Interrupt 0"),
  72         ("IRQ0","External Interrupt 0"),
  73         (None,None),
  74         (None,None),
  75         (None,None),
  76         (None,None),
  77         (None,None),
  78         (None,None),
  79         (None,None),
  80         (None,None),
  81         (None,None),
  82         (None,None),
  83         (None,None),
  84         (None,None),
  85         (None,None),
  86         )
  87
  88 def aic_smr_decode(smr):
  89     output = ["Interrupt Priority: %s"%(smr&7),
  90             "Interrupt Source Type: %s"%("Low Level Sensitive","Negative Edge Triggered","High Level Sensitive","Positive Edge Triggered")[(smr>>5)],
  91             ]
  92     return "\n".join(output)
  93
  94 AIC_BASE = 0xFFFFF000
  95 AIC_SMR = [(AIC_BASE+(x*4), "Source Mode Register %d"%x)  for x in xrange(32)]
  96 AIC_SVR = [(AIC_BASE+0x80+(x*4), "Source Vector Register %d"%x)  for x in xrange(32)]
  97 AIC_IVR = AIC_BASE + 0x100
  98 AIC_FVR = AIC_BASE + 0x104
  99 AIC_ISR = AIC_BASE + 0x108
 100 AIC_IPR = AIC_BASE + 0x10c
 101 AIC_IMR = AIC_BASE + 0x110
 102 AIC_CISR = AIC_BASE + 0x114
 103 AIC_IECR = AIC_BASE + 0x120
 104 AIC_IDCR = AIC_BASE + 0x124
 105 AIC_ICCR = AIC_BASE + 0x128
 106 AIC_ISCR = AIC_BASE + 0x12c
 107 AIC_EOICR = AIC_BASE + 0x130
 108 AIC_SPU = AIC_BASE + 0x134
 109
 110
 111 PIO_BASE = 0xFFFF0000
 112 PIO_PER =   PIO_BASE + 0x0
 113 PIO_PDR =   PIO_BASE + 0x4
 114 PIO_PSR =   PIO_BASE + 0x8
 115 PIO_OER =   PIO_BASE + 0x10
 116 PIO_ODR =   PIO_BASE + 0x14
 117 PIO_OSR =   PIO_BASE + 0x18
 118 PIO_SODR =  PIO_BASE + 0x30
 119 PIO_CODR =  PIO_BASE + 0x34
 120 PIO_ODSR =  PIO_BASE + 0x38
 121 PIO_CDSR =  PIO_BASE + 0x3c
 122 PIO_IER =   PIO_BASE + 0x40
 123 PIO_IDR =   PIO_BASE + 0x44
 124 PIO_IMR =   PIO_BASE + 0x48
 125 PIO_ISR =   PIO_BASE + 0x4c
 126
 127 WD_BASE = 0xFFFF8000
 128 WD_OMR  =   WD_BASE + 0x0
 129 WD_CMR  =   WD_BASE + 0x4
 130 WD_CR   =   WD_BASE + 0x8
 131 WD_SR   =   WD_BASE + 0xc
 132
 133 SF_BASE = 0xFFF00000
 134 SF_CIDR =   SF_BASE + 0x0
 135 SF_EXID =   SF_BASE + 0x4
 136 SF_RSR =    SF_BASE + 0x8
 137 SF_MMR =    SF_BASE + 0xC
 138 SF_PMR =    SF_BASE + 0x18
 139
 140 #* Flash
 141 FLASH_BASE_ADDR =    0x1000000
 142 WAIT =               300000
 143 FLASH_CODE_MASK =    0x000000FF
 144
 145 #*Flash AT49 codes
 146 ATMEL_MANUFACTURED =         0x001F
 147 FLASH_AT49BV_UNKNOW =        0xFFFF
 148 FLASH_AT49BV8011 =           0x00CB
 149 FLASH_AT49BV8011T =          0x004A
 150 FLASH_AT49BV16x4 =           0x00C0
 151 FLASH_AT49BV16x4T =          0x00C2
 152
 153 #*Flash AT29 codes
 154 FLASH_AT29LV1024 =               0X26
 155 FLASH_AT29C020 =                 0XDA
 156
 157 #* Flash Program information
 158 FLASH_PRG_SIZE =     0x800   #* 2Kbytes
 159 FLASH_PRG_DEST =     0x20    #* Address on the target
 160 START_PRG =          0x20
 161
 162 #* Parameter for Flash_XV_Send_Data functions
 163 ERASE =  1
 164 PROGRAM =0
 165
 166 MIRROR =     1
 167 NO_MIRROR =  0
 168
 169 ERASE_DATA = 0
 170
 171 #* Load program parameters
 172 NB_REG =     13
 173 SIZE_DATA =  4
 174
 175 #* Flash LV Send Data parameters
 176 SIZE_256_BYTES = 0x100
 177 PACKET_SIZE =64
 178
 179 NB_PRG =     3
 180
 181 #* Periph
 182 EBI =    0
 183 PLL =    1
 184
 185 #* Targets
 186 EB40 =   0x04080700
 187 EB40A =  0x04000800
 188 EB42 =   0x04280000
 189 EB55 =   0x05580000
 190 EB63 =   0x06320000
 191 EBMASK = 0x0fffff00
 192
 193 NB_TARGET_SUPPORTED =    6
 194
 195 #* Flash type
 196 FLASH_LV =   0
 197 FLASH_BV =   1
 198
 199 #* Flash Program Address
 200 FLASH_LV_PRG =   0x01018000
 201 FLASH_BV_PRG =   0x0101A000
 202
 203 EBI_READ    = 4
 204 EBI_WRITE   = 2
 205
 206 ebi_memory_map_items = {
 207         EBI_OFF_CSR0:("Chip Select Register 0", "EBI_CSR0", EBI_READ|EBI_WRITE,0x0000203e),
 208         EBI_OFF_CSR1:("Chip Select Register 1", "EBI_CSR1", EBI_READ|EBI_WRITE,0x10000000),
 209         EBI_OFF_CSR2:("Chip Select Register 2", "EBI_CSR2", EBI_READ|EBI_WRITE,0x20000000),
 210         EBI_OFF_CSR3:("Chip Select Register 3", "EBI_CSR3", EBI_READ|EBI_WRITE,0x30000000),
 211         EBI_OFF_CSR4:("Chip Select Register 4", "EBI_CSR4", EBI_READ|EBI_WRITE,0x40000000),
 212         EBI_OFF_CSR5:("Chip Select Register 5", "EBI_CSR5", EBI_READ|EBI_WRITE,0x50000000),
 213         EBI_OFF_CSR6:("Chip Select Register 6", "EBI_CSR6", EBI_READ|EBI_WRITE,0x60000000),
 214         EBI_OFF_CSR7:("Chip Select Register 7", "EBI_CSR7", EBI_READ|EBI_WRITE,0x70000000),
 215         EBI_OFF_MCR: ("Memory Control Register","EBI_MCR",  EBI_READ|EBI_WRITE,0),
 216         }
 217
 218 def ebi_csr_decode(reg):
 219     addr = reg>>20
 220     csen = (reg>>13)&1
 221     bat =  (reg>>12)&1
 222     tdf =  (reg>>9)&7
 223     pages =(reg>>7)&3
 224     wse =  (reg>>5)&1
 225     nws =  (reg>>2)&7
 226     dbw =  (reg&3)
 227     output = ["Base Address: %s"%hex(addr),
 228             "Chip Select: %s"%("False","True")[csen],
 229             "Byte Access Type: %s"%("Byte-Write","Byte-Access")[bat],
 230             "Data Float Output Time: %d cycles added"%tdf,
 231             "Page Size: %d MB"%(1,4,16,64)[pages],
 232             "Wait State: %s"%("disabled","enabled")[wse],
 233             "Wait States: %d"%nws,
 234             "Data Bus Size: %d bits"%dbw,
 235             ]
 236     return "\n".join(output)
 237
 238 mcr_ale = {
 239         0: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 240         1: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 241         2: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 242         3: ("A20,A21,A22,A23", 16, "None", "EBI_ALE_16M"),
 243         4: ("A20,A21,A22", 8, "CS4", "EBI_ALE_8M"),
 244         5: ("A20,A21", 4, "CS4,CS5", "EBI_ALE_4M"),
 245         6: ("A20", 2, "CS4,CS5,CS6", "EBI_ALE_2M"),
 246         7: ("None", 1, "CS4,CS5,CS6,CS7", "EBI_ALE_1M"),
 247         }
 248
 249 def mcr_decode(mcr):
 250     validAddrBits,maxAddrSpace,validCS,codeLabel = mcr_decode[mcr&7]
 251     drp = mcr>>4
 252     output = ["Valid Address Bits: %s"%validAddrBits,
 253             "Maximum Address Space: %xMB"%maxAddrSpace,
 254             "Valid Chip Select: %s"%validCS,
 255             "Code Label:  %s"%codeLabel,
 256             ("Standard Read Protocol for all external memory devices enabled (EBI_DRP_STANDARD)","Early Read Protocol for all external memory devices enabled (EBI_DRP_EARLY)")[drp]
 257             ]
 258     return "\n".join(output)
 259
 260 def wd_omr_decode(omr):
 261     return "\n".join(["External Signal: %s"%("disabled","enabled")[(omr>>3)&1],
 262             "External Signal: %s"%("disabled","enabled")[(omr>>3)&1],
 263             "Interrupt: %s"%("disabled","enabled")[(omr>>2)&1],
 264             "Reset: %s"%("disabled","enabled")[(omr>>1)&1],
 265             "Watch Dog: %s"%("disabled","enabled")[(omr)&1],
 266             ])
 267 def wd_cmr_decode(cmr):
 268     return "MCK/%d"%(8,32,128,1024)[(cmr>>2)&0xf]
 269
 270
 271
 272
 273
 274 class GoodFETAT91X40(GoodFETARM):
 275     def getChipSelectReg(self, chipnum):
 276         addr = EBI_BASE + (chipnum*4)
 277         reg, = self.ARMreadMem(addr,1)
 278         return reg
 279     def getChipSelectRegstr(self, chipnum):
 280         return ebi_csr_decode(self.getChipSelectReg(chipnum))
 281
 282     def getEBIMemoryMap(self):
 283         keys = ebi_memory_map_items.keys()
 284         keys.sort()
 285         output = [ "EBI Memory Map"]
 286         for x in xrange(8):
 287             desc,name,rw,default = ebi_memory_map_items[x*4]
 288             output.append("\nMAP: %s (%s) - default: %x\n%s"%(name,desc,default,self.getChipSelectRegstr(x)))
 289         return "\n".join(output)
 290     def getMemoryControlRegister(self):
 291         mcr = self.ARMreadMem(EBI_MCR)
 292         return mcr
 293     def getMemoryControlRegisterstr(self):
 294         return mcr_decode(self.getMemoryControlRegister())
 295
 296     def getInterruptSourceModeReg(self, regnum):
 297         regval = self.ARMreadMem(AIC_SMR[regnum][0])
 298         return retval
 299     def getInterruptSourceModeRegstr(self, regnum):
 300         return aic_smr_decode(self.getInterruptSourceModeReg(regnum))
 301     def setInterruptSourceModeReg(self, regnum, val):
 302         self.ARMwriteMem(AIC_SMR[regnum][0], val)
 303
 304     def getInterruptSourceVectorReg(self, regnum):
 305         regval = self.ARMreadMem(AIC_SVR[regnum][0])
 306         return retval
 307     def setInterruptSourceModeReg(self, regnum, val):
 308         self.ARMwriteMem(AIC_SVR[regnum][0], val)
 309
 310     def getIRQVectorReg(self):
 311         return self.ARMreadMem(AIC_IVR)
 312     def getFIQVectorReg(self):
 313         return self.ARMreadMem(AIC_FVR)
 314
 315     def getInterruptStatusReg(self):
 316         return self.ARMreadMem(AIC_ISR)
 317     def getInterruptPendingReg(self):
 318         return self.ARMreadMem(AIC_FSR)
 319     def getInterruptMaskReg(self):
 320         return self.ARMreadMem(AIC_IMR)
 321     def getCoreInterruptStatusReg(self):
 322         return self.ARMreadMem(AIC_CISR)
 323     def enableInterrupt(self, interrupt):
 324         self.ARMwriteMem(AIC_IECR, 1<<interrupt)
 325     def disableInterrupt(self, interrupt):
 326         self.ARMwriteMem(AIC_IDCR, 1<<interrupt)
 327     def setInterruptCommandReg(self, interrupt):
 328         self.ARMwriteMem(AIC_ISCR, 1<<interrupt)
 329     def clearInterruptCommandReg(self, interrupt):
 330         self.ARMwriteMem(AIC_ICCR, 1<<interrupt)
 331     def clearCurrentInterrupt(self):
 332         self.ARMwriteMem(AIC_EOICR, 1<<interrupt)
 333     def getSpuriousVectorReg(self):
 334         return self.ARMreadMem(AIC_SPU)
 335     def setSpuriousVectorReg(self, val):
 336         return self.ARMreadMem(AIC_SPU)
 337
 338     def enablePIOpin(self, mask):
 339         self.ARMwriteMem(PIO_PER, mask)
 340     def disablePIOpin(self, mask):
 341         self.ARMwriteMem(PIO_PDR, mask)
 342     def getPIOstatus(self):
 343         return self.ARMreadMem(PIO_PSR)
 344     def enablePIOoutput(self,mask):
 345         self.ARMwriteMem(PIO_OER, mask)
 346     def disablePIOoutput(self,mask):
 347         self.ARMwriteMem(PIO_ODR, mask)
 348     def getPIOoutputStatus(self):
 349         return self.ARMreadMem(PIO_OSR)
 350
 351     def setOutputPin(self,mask):
 352         self.ARMwriteMem(PIO_SODR, mask)
 353     def clearOutputPin(self,mask):
 354         self.ARMwriteMem(PIO_CODR, mask)
 355     def getOutputDataStatusReg(self):
 356         return self.ARMreadMem(PIO_ODSR)
 357     def getPinDataStatusReg(self):
 358         return self.ARMreadMem(PIO_PDSR)
 359     def enablePIOinterrupt(self, mask):
 360         self.ARMwriteMem(PIO_IER, mask)
 361     def disablePIOinterrupt(self, mask):
 362         self.ARMwriteMem(PIO_IDR, mask)
 363     def getPIOinterruptMaskReg(self):
 364         return self.ARMreadMem(PIO_IMR)
 365     def getPIOinteruptStatusReg(self):
 366         return self.ARMreadMem(PIO_ODSR)
 367
 368
 369     def getWatchDogOverflowModeReg(self):
 370         return self.ARMreadMem(WD_OMR)
 371     def getWatchDogOverflowModeStr(self):
 372         return wd_omr_decode(self.getWatchDogOverflowModeReg())
 373     def setWatchDogOverflowModeReg(self, mode=0x2340):
 374         self.ARMwriteMem(WD_OMR, mode)
 375     def getWatchDogClockModeReg(self):
 376         return self.ARMreadMem(WD_CMR)
 377     def setWatchDogClockModeReg(self, mode=0x06e):
 378         self.ARMwriteMem(WD_CMR, mode)
 379     def setWatchDogControlReg(self, mode=0xC071):
 380         self.ARMwriteMem(WD_CR, mode)
 381     def getWatchDogStatusReg(self):
 382         return self.ARMreadMem(WD_SR)
 383
 384     def getChipID(self):
 385         chipid = self.ARMreadMem(SF_CIDR,1)
 386         return chipid[0]
 387     def getResetStatusReg(self):
 388         return self.ARMreadMem(SF_RSR)
 389     def getMemoryModeReg(self):
 390         return self.ARMreadMem(SF_MMR)
 391     def setMemoryModeReg(self, val=0):
 392         self.ARMwriteMem(SF_MMR, val)
 393     def getProtectModeReg(self):
 394         return self.ARMreadMem(SF_PMR)
 395     def setProtectModeReg(self, val=0x27a80000):
 396         self.ARMwriteMem(SF_PMR, val)
 397
 398
 399
 400
 401
 402
 403
 404     def ARMwriteFirmware(self, firmware):
 405         self.halt()
 406         chipid = self.ARMgetChipID()
 407         # FIXME: initialize PLL or EBI
 408         self.ARMmassErase(chipid)
 409         self.ARMset_regCPSR(PM_svc)   # set supervisor mode
 410         # FIXME: download the "flash identifier" program into target RAM
 411         self.ARMsetPC(PROGGYBASE)
 412         self.release()
 413         # get manufacturer crap through DCC (really??  screw this...)
 414         self.halt()
 415         if (self.ARMget_regCPSR() & PM_svc != PM_svc):
 416             raise Exception("No longer in Supervisor mode after firmware upload")
 417         # FIXME: download the downloader program into target RAM
 418         self.ARMsetPC(PROGGYBASE)
 419         self.release()
 420         # FIXME: use DCC to upload the new firmware