2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 * An ATA driver for the legacy ATA ports.
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
34 * on PC class systems. There are three hybrid devices that are exceptions
35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
39 * opti82c465mv/promise 20230c/20630
41 * Use the autospeed and pio_mask options with:
42 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
45 * Winbond W83759A, Promise PDC20230-B
47 * For now use autospeed and pio_mask as above with the W83759A. This may
51 * Merge existing pata_qdi driver
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/ata.h>
63 #include <linux/libata.h>
64 #include <linux/platform_device.h>
66 #define DRV_NAME "pata_legacy"
67 #define DRV_VERSION "0.5.3"
71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
72 static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 };
79 struct platform_device *platform_dev;
83 static struct legacy_data legacy_data[NR_HOST];
84 static struct ata_host *legacy_host[NR_HOST];
85 static int nr_legacy_host;
88 static int probe_all; /* Set to check all ISA port ranges */
89 static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */
90 static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */
91 static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */
92 static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */
93 static int autospeed; /* Chip present which snoops speed changes */
94 static int pio_mask = 0x1F; /* PIO range for autospeed devices */
97 * legacy_set_mode - mode setting
99 * @unused: Device that failed when error is returned
101 * Use a non standard set_mode function. We don't want to be tuned.
103 * The BIOS configured everything. Our job is not to fiddle. Just use
104 * whatever PIO the hardware is using and leave it at that. When we
105 * get some kind of nice user driven API for control then we can
106 * expand on this as per hdparm in the base kernel.
109 static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused)
113 for (i = 0; i < ATA_MAX_DEVICES; i++) {
114 struct ata_device *dev = &ap->device[i];
115 if (ata_dev_enabled(dev)) {
116 dev->pio_mode = XFER_PIO_0;
117 dev->xfer_mode = XFER_PIO_0;
118 dev->xfer_shift = ATA_SHIFT_PIO;
119 dev->flags |= ATA_DFLAG_PIO;
125 static struct scsi_host_template legacy_sht = {
126 .module = THIS_MODULE,
128 .ioctl = ata_scsi_ioctl,
129 .queuecommand = ata_scsi_queuecmd,
130 .can_queue = ATA_DEF_QUEUE,
131 .this_id = ATA_SHT_THIS_ID,
132 .sg_tablesize = LIBATA_MAX_PRD,
133 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
134 .emulated = ATA_SHT_EMULATED,
135 .use_clustering = ATA_SHT_USE_CLUSTERING,
136 .proc_name = DRV_NAME,
137 .dma_boundary = ATA_DMA_BOUNDARY,
138 .slave_configure = ata_scsi_slave_config,
139 .slave_destroy = ata_scsi_slave_destroy,
140 .bios_param = ata_std_bios_param,
144 * These ops are used if the user indicates the hardware
145 * snoops the commands to decide on the mode and handles the
146 * mode selection "magically" itself. Several legacy controllers
147 * do this. The mode range can be set if it is not 0x1F by setting
151 static struct ata_port_operations simple_port_ops = {
152 .port_disable = ata_port_disable,
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
159 .freeze = ata_bmdma_freeze,
160 .thaw = ata_bmdma_thaw,
161 .error_handler = ata_bmdma_error_handler,
162 .post_internal_cmd = ata_bmdma_post_internal_cmd,
164 .qc_prep = ata_qc_prep,
165 .qc_issue = ata_qc_issue_prot,
167 .data_xfer = ata_pio_data_xfer_noirq,
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
172 .port_start = ata_port_start,
175 static struct ata_port_operations legacy_port_ops = {
176 .set_mode = legacy_set_mode,
178 .port_disable = ata_port_disable,
179 .tf_load = ata_tf_load,
180 .tf_read = ata_tf_read,
181 .check_status = ata_check_status,
182 .exec_command = ata_exec_command,
183 .dev_select = ata_std_dev_select,
185 .error_handler = ata_bmdma_error_handler,
187 .qc_prep = ata_qc_prep,
188 .qc_issue = ata_qc_issue_prot,
190 .data_xfer = ata_pio_data_xfer_noirq,
192 .irq_handler = ata_interrupt,
193 .irq_clear = ata_bmdma_irq_clear,
195 .port_start = ata_port_start,
199 * Promise 20230C and 20620 support
201 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to
202 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
203 * controller and PIO'd to the host and not supported.
206 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
209 int pio = adev->pio_mode - XFER_PIO_0;
213 /* Safe as UP only. Force I/Os to occur together */
215 local_irq_save(flags);
217 /* Unlock the control interface */
221 outb(inb(0x1F2) | 0x80, 0x1F2);
228 while((inb(0x1F2) & 0x80) && --tries);
230 local_irq_restore(flags);
232 outb(inb(0x1F4) & 0x07, 0x1F4);
235 rt &= 0x07 << (3 * adev->devno);
237 rt |= (1 + 3 * pio) << (3 * adev->devno);
240 outb(inb(0x1F2) | 0x01, 0x1F2);
246 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
248 struct ata_port *ap = adev->ap;
249 int slop = buflen & 3;
252 if (ata_id_has_dword_io(adev->id)) {
253 local_irq_save(flags);
255 /* Perform the 32bit I/O synchronization sequence */
256 inb(ap->ioaddr.nsect_addr);
257 inb(ap->ioaddr.nsect_addr);
258 inb(ap->ioaddr.nsect_addr);
263 outsl(ap->ioaddr.data_addr, buf, buflen >> 2);
265 insl(ap->ioaddr.data_addr, buf, buflen >> 2);
267 if (unlikely(slop)) {
270 memcpy(&pad, buf + buflen - slop, slop);
271 outl(le32_to_cpu(pad), ap->ioaddr.data_addr);
273 pad = cpu_to_le16(inl(ap->ioaddr.data_addr));
274 memcpy(buf + buflen - slop, &pad, slop);
277 local_irq_restore(flags);
280 ata_pio_data_xfer_noirq(adev, buf, buflen, write_data);
283 static struct ata_port_operations pdc20230_port_ops = {
284 .set_piomode = pdc20230_set_piomode,
286 .port_disable = ata_port_disable,
287 .tf_load = ata_tf_load,
288 .tf_read = ata_tf_read,
289 .check_status = ata_check_status,
290 .exec_command = ata_exec_command,
291 .dev_select = ata_std_dev_select,
293 .error_handler = ata_bmdma_error_handler,
295 .qc_prep = ata_qc_prep,
296 .qc_issue = ata_qc_issue_prot,
298 .data_xfer = pdc_data_xfer_vlb,
300 .irq_handler = ata_interrupt,
301 .irq_clear = ata_bmdma_irq_clear,
303 .port_start = ata_port_start,
307 * Holtek 6560A support
309 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings
313 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
318 /* Get the timing data in cycles. For now play safe at 50Mhz */
319 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
321 active = FIT(t.active, 2, 15);
322 recover = FIT(t.recover, 4, 15);
329 outb(recover << 4 | active, ap->ioaddr.device_addr);
330 inb(ap->ioaddr.status_addr);
333 static struct ata_port_operations ht6560a_port_ops = {
334 .set_piomode = ht6560a_set_piomode,
336 .port_disable = ata_port_disable,
337 .tf_load = ata_tf_load,
338 .tf_read = ata_tf_read,
339 .check_status = ata_check_status,
340 .exec_command = ata_exec_command,
341 .dev_select = ata_std_dev_select,
343 .error_handler = ata_bmdma_error_handler,
345 .qc_prep = ata_qc_prep,
346 .qc_issue = ata_qc_issue_prot,
348 .data_xfer = ata_pio_data_xfer, /* Check vlb/noirq */
350 .irq_handler = ata_interrupt,
351 .irq_clear = ata_bmdma_irq_clear,
353 .port_start = ata_port_start,
357 * Holtek 6560B support
359 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
360 * unless we see an ATAPI device in which case we force it off.
362 * FIXME: need to implement 2nd channel support.
365 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
370 /* Get the timing data in cycles. For now play safe at 50Mhz */
371 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
373 active = FIT(t.active, 2, 15);
374 recover = FIT(t.recover, 2, 16);
382 outb(recover << 4 | active, ap->ioaddr.device_addr);
384 if (adev->class != ATA_DEV_ATA) {
385 u8 rconf = inb(0x3E6);
391 inb(ap->ioaddr.status_addr);
394 static struct ata_port_operations ht6560b_port_ops = {
395 .set_piomode = ht6560b_set_piomode,
397 .port_disable = ata_port_disable,
398 .tf_load = ata_tf_load,
399 .tf_read = ata_tf_read,
400 .check_status = ata_check_status,
401 .exec_command = ata_exec_command,
402 .dev_select = ata_std_dev_select,
404 .error_handler = ata_bmdma_error_handler,
406 .qc_prep = ata_qc_prep,
407 .qc_issue = ata_qc_issue_prot,
409 .data_xfer = ata_pio_data_xfer, /* FIXME: Check 32bit and noirq */
411 .irq_handler = ata_interrupt,
412 .irq_clear = ata_bmdma_irq_clear,
414 .port_start = ata_port_start,
418 * Opti core chipset helpers
422 * opti_syscfg - read OPTI chipset configuration
423 * @reg: Configuration register to read
425 * Returns the value of an OPTI system board configuration register.
428 static u8 opti_syscfg(u8 reg)
433 /* Uniprocessor chipset and must force cycles adjancent */
434 local_irq_save(flags);
437 local_irq_restore(flags);
444 * This controller supports PIO0 to PIO3.
447 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
449 u8 active, recover, setup;
451 struct ata_device *pair = ata_dev_pair(adev);
453 int khz[4] = { 50000, 40000, 33000, 25000 };
456 /* Enter configuration mode */
457 inw(ap->ioaddr.error_addr);
458 inw(ap->ioaddr.error_addr);
459 outb(3, ap->ioaddr.nsect_addr);
461 /* Read VLB clock strapping */
462 clock = 1000000000 / khz[inb(ap->ioaddr.lbah_addr) & 0x03];
464 /* Get the timing data in cycles */
465 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
467 /* Setup timing is shared */
469 struct ata_timing tp;
470 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
472 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
475 active = FIT(t.active, 2, 17) - 2;
476 recover = FIT(t.recover, 1, 16) - 1;
477 setup = FIT(t.setup, 1, 4) - 1;
479 /* Select the right timing bank for write timing */
480 rc = inb(ap->ioaddr.lbal_addr);
482 rc |= (adev->devno << 7);
483 outb(rc, ap->ioaddr.lbal_addr);
485 /* Write the timings */
486 outb(active << 4 | recover, ap->ioaddr.error_addr);
488 /* Select the right bank for read timings, also
489 load the shared timings for address */
490 rc = inb(ap->ioaddr.device_addr);
492 rc |= adev->devno; /* Index select */
493 rc |= (setup << 4) | 0x04;
494 outb(rc, ap->ioaddr.device_addr);
496 /* Load the read timings */
497 outb(active << 4 | recover, ap->ioaddr.data_addr);
499 /* Ensure the timing register mode is right */
500 rc = inb (ap->ioaddr.lbal_addr);
503 outb(rc, ap->ioaddr.lbal_addr);
505 /* Exit command mode */
506 outb(0x83, ap->ioaddr.nsect_addr);
510 static struct ata_port_operations opti82c611a_port_ops = {
511 .set_piomode = opti82c611a_set_piomode,
513 .port_disable = ata_port_disable,
514 .tf_load = ata_tf_load,
515 .tf_read = ata_tf_read,
516 .check_status = ata_check_status,
517 .exec_command = ata_exec_command,
518 .dev_select = ata_std_dev_select,
520 .error_handler = ata_bmdma_error_handler,
522 .qc_prep = ata_qc_prep,
523 .qc_issue = ata_qc_issue_prot,
525 .data_xfer = ata_pio_data_xfer,
527 .irq_handler = ata_interrupt,
528 .irq_clear = ata_bmdma_irq_clear,
530 .port_start = ata_port_start,
536 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
537 * version is dual channel but doesn't have a lot of unique registers.
540 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
542 u8 active, recover, setup;
544 struct ata_device *pair = ata_dev_pair(adev);
546 int khz[4] = { 50000, 40000, 33000, 25000 };
551 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
553 /* Enter configuration mode */
554 inw(ap->ioaddr.error_addr);
555 inw(ap->ioaddr.error_addr);
556 outb(3, ap->ioaddr.nsect_addr);
558 /* Read VLB clock strapping */
559 clock = 1000000000 / khz[sysclk];
561 /* Get the timing data in cycles */
562 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
564 /* Setup timing is shared */
566 struct ata_timing tp;
567 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
569 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
572 active = FIT(t.active, 2, 17) - 2;
573 recover = FIT(t.recover, 1, 16) - 1;
574 setup = FIT(t.setup, 1, 4) - 1;
576 /* Select the right timing bank for write timing */
577 rc = inb(ap->ioaddr.lbal_addr);
579 rc |= (adev->devno << 7);
580 outb(rc, ap->ioaddr.lbal_addr);
582 /* Write the timings */
583 outb(active << 4 | recover, ap->ioaddr.error_addr);
585 /* Select the right bank for read timings, also
586 load the shared timings for address */
587 rc = inb(ap->ioaddr.device_addr);
589 rc |= adev->devno; /* Index select */
590 rc |= (setup << 4) | 0x04;
591 outb(rc, ap->ioaddr.device_addr);
593 /* Load the read timings */
594 outb(active << 4 | recover, ap->ioaddr.data_addr);
596 /* Ensure the timing register mode is right */
597 rc = inb (ap->ioaddr.lbal_addr);
600 outb(rc, ap->ioaddr.lbal_addr);
602 /* Exit command mode */
603 outb(0x83, ap->ioaddr.nsect_addr);
605 /* We need to know this for quad device on the MVB */
606 ap->host->private_data = ap;
610 * opt82c465mv_qc_issue_prot - command issue
611 * @qc: command pending
613 * Called when the libata layer is about to issue a command. We wrap
614 * this interface so that we can load the correct ATA timings. The
615 * MVB has a single set of timing registers and these are shared
616 * across channels. As there are two registers we really ought to
617 * track the last two used values as a sort of register window. For
618 * now we just reload on a channel switch. On the single channel
619 * setup this condition never fires so we do nothing extra.
621 * FIXME: dual channel needs ->serialize support
624 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
626 struct ata_port *ap = qc->ap;
627 struct ata_device *adev = qc->dev;
629 /* If timings are set and for the wrong channel (2nd test is
630 due to a libata shortcoming and will eventually go I hope) */
631 if (ap->host->private_data != ap->host
632 && ap->host->private_data != NULL)
633 opti82c46x_set_piomode(ap, adev);
635 return ata_qc_issue_prot(qc);
638 static struct ata_port_operations opti82c46x_port_ops = {
639 .set_piomode = opti82c46x_set_piomode,
641 .port_disable = ata_port_disable,
642 .tf_load = ata_tf_load,
643 .tf_read = ata_tf_read,
644 .check_status = ata_check_status,
645 .exec_command = ata_exec_command,
646 .dev_select = ata_std_dev_select,
648 .error_handler = ata_bmdma_error_handler,
650 .qc_prep = ata_qc_prep,
651 .qc_issue = opti82c46x_qc_issue_prot,
653 .data_xfer = ata_pio_data_xfer,
655 .irq_handler = ata_interrupt,
656 .irq_clear = ata_bmdma_irq_clear,
658 .port_start = ata_port_start,
663 * legacy_init_one - attach a legacy interface
665 * @io: I/O port start
666 * @ctrl: control port
667 * @irq: interrupt line
669 * Register an ISA bus IDE interface. Such interfaces are PIO and we
670 * assume do not support IRQ sharing.
673 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
675 struct legacy_data *ld = &legacy_data[nr_legacy_host];
676 struct ata_probe_ent ae;
677 struct platform_device *pdev;
678 struct ata_port_operations *ops = &legacy_port_ops;
679 int pio_modes = pio_mask;
680 u32 mask = (1 << port);
683 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
685 return PTR_ERR(pdev);
688 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
689 devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
692 if (ht6560a & mask) {
693 ops = &ht6560a_port_ops;
696 if (ht6560b & mask) {
697 ops = &ht6560b_port_ops;
700 if (opti82c611a & mask) {
701 ops = &opti82c611a_port_ops;
704 if (opti82c46x & mask) {
705 ops = &opti82c46x_port_ops;
709 /* Probe for automatically detectable controllers */
711 if (io == 0x1F0 && ops == &legacy_port_ops) {
714 local_irq_save(flags);
718 outb(inb(0x1F2) | 0x80, 0x1F2);
725 if ((inb(0x1F2) & 0x80) == 0) {
726 /* PDC20230c or 20630 ? */
727 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
729 ops = &pdc20230_port_ops;
736 if (inb(0x1F2) == 0x00) {
737 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
740 local_irq_restore(flags);
744 /* Chip does mode setting by command snooping */
745 if (ops == &legacy_port_ops && (autospeed & mask))
746 ops = &simple_port_ops;
747 memset(&ae, 0, sizeof(struct ata_probe_ent));
748 INIT_LIST_HEAD(&ae.node);
751 ae.sht = &legacy_sht;
753 ae.pio_mask = pio_modes;
756 ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
757 ae.port[0].cmd_addr = io;
758 ae.port[0].altstatus_addr = ctrl;
759 ae.port[0].ctl_addr = ctrl;
760 ata_std_ports(&ae.port[0]);
761 ae.private_data = ld;
764 if (!ata_device_add(&ae))
767 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
768 ld->platform_dev = pdev;
772 platform_device_unregister(pdev);
777 * legacy_check_special_cases - ATA special cases
778 * @p: PCI device to check
779 * @master: set this if we find an ATA master
780 * @master: set this if we find an ATA secondary
782 * A small number of vendors implemented early PCI ATA interfaces on bridge logic
783 * without the ATA interface being PCI visible. Where we have a matching PCI driver
784 * we must skip the relevant device here. If we don't know about it then the legacy
785 * driver is the right driver anyway.
788 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
790 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
791 if (p->vendor == 0x1078 && p->device == 0x0000) {
792 *primary = *secondary = 1;
795 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
796 if (p->vendor == 0x1078 && p->device == 0x0002) {
797 *primary = *secondary = 1;
800 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
801 if (p->vendor == 0x8086 && p->device == 0x1234) {
803 pci_read_config_word(p, 0x6C, &r);
804 if (r & 0x8000) { /* ATA port enabled */
816 * legacy_init - attach legacy interfaces
818 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
819 * Right now we do not scan the ide0 and ide1 address but should do so
820 * for non PCI systems or systems with no PCI IDE legacy mode devices.
821 * If you fix that note there are special cases to consider like VLB
822 * drivers and CS5510/20.
825 static __init int legacy_init(void)
831 int last_port = NR_HOST;
833 struct pci_dev *p = NULL;
835 for_each_pci_dev(p) {
837 /* Check for any overlap of the system ATA mappings. Native mode controllers
838 stuck on these addresses or some devices in 'raid' mode won't be found by
839 the storage class test */
840 for (r = 0; r < 6; r++) {
841 if (pci_resource_start(p, r) == 0x1f0)
843 if (pci_resource_start(p, r) == 0x170)
846 /* Check for special cases */
847 legacy_check_special_cases(p, &primary, &secondary);
849 /* If PCI bus is present then don't probe for tertiary legacy ports */
854 /* If an OPTI 82C46X is present find out where the channels are */
856 static const char *optis[4] = {
861 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
863 opti82c46x = 3; /* Assume master and slave first */
864 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
866 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
867 ctrl = opti_syscfg(0xAC);
868 /* Check enabled and this port is the 465MV port. On the
869 MVB we may have two channels */
872 opti82c46x = 2; /* Slave */
874 opti82c46x = 1; /* Master */
876 opti82c46x = 3; /* Master and Slave */
882 for (i = 0; i < last_port; i++) {
883 /* Skip primary if we have seen a PCI one */
884 if (i == 0 && primary == 1)
886 /* Skip secondary if we have seen a PCI one */
887 if (i == 1 && secondary == 1)
889 if (legacy_init_one(i, legacy_port[i],
890 legacy_port[i] + 0x0206,
899 static __exit void legacy_exit(void)
903 for (i = 0; i < nr_legacy_host; i++) {
904 struct legacy_data *ld = &legacy_data[i];
906 ata_host_detach(legacy_host[i]);
907 platform_device_unregister(ld->platform_dev);
909 release_region(ld->timing, 2);
913 MODULE_AUTHOR("Alan Cox");
914 MODULE_DESCRIPTION("low-level driver for legacy ATA");
915 MODULE_LICENSE("GPL");
916 MODULE_VERSION(DRV_VERSION);
918 module_param(probe_all, int, 0);
919 module_param(autospeed, int, 0);
920 module_param(ht6560a, int, 0);
921 module_param(ht6560b, int, 0);
922 module_param(opti82c611a, int, 0);
923 module_param(opti82c46x, int, 0);
924 module_param(pio_mask, int, 0);
926 module_init(legacy_init);
927 module_exit(legacy_exit);