5 * Semi-public control interfaces
13 #define MOXA_GETDATACOUNT (MOXA + 23)
14 #define MOXA_GET_CONF (MOXA + 35)
15 #define MOXA_DIAGNOSE (MOXA + 50)
16 #define MOXA_CHKPORTENABLE (MOXA + 60)
17 #define MOXA_HighSpeedOn (MOXA + 61)
18 #define MOXA_GET_MAJOR (MOXA + 63)
19 #define MOXA_GET_CUMAJOR (MOXA + 64)
20 #define MOXA_GETMSTATUS (MOXA + 65)
21 #define MOXA_SET_OP_MODE (MOXA + 66)
22 #define MOXA_GET_OP_MODE (MOXA + 67)
25 #define RS485_2WIRE_MODE 1
27 #define RS485_4WIRE_MODE 3
28 #define OP_MODE_MASK 3
30 #define MOXA_SDS_RSTICOUNTER (MOXA + 69)
31 #define MOXA_ASPP_OQUEUE (MOXA + 70)
32 #define MOXA_ASPP_MON (MOXA + 73)
33 #define MOXA_ASPP_LSTATUS (MOXA + 74)
34 #define MOXA_ASPP_MON_EXT (MOXA + 75)
35 #define MOXA_SET_BAUD_METHOD (MOXA + 76)
37 /* --------------------------------------------------- */
39 #define NPPI_NOTIFY_PARITY 0x01
40 #define NPPI_NOTIFY_FRAMING 0x02
41 #define NPPI_NOTIFY_HW_OVERRUN 0x04
42 #define NPPI_NOTIFY_SW_OVERRUN 0x08
43 #define NPPI_NOTIFY_BREAK 0x10
45 #define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
46 #define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
47 #define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
48 #define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
50 /* follow just for Moxa Must chip define. */
52 /* when LCR register (offset 0x03) write following value, */
53 /* the Must chip will enter enchance mode. And write value */
54 /* on EFR (offset 0x02) bit 6,7 to change bank. */
55 #define MOXA_MUST_ENTER_ENCHANCE 0xBF
57 /* when enhance mode enable, access on general bank register */
58 #define MOXA_MUST_GDL_REGISTER 0x07
59 #define MOXA_MUST_GDL_MASK 0x7F
60 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
62 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
63 /* enchance register bank select and enchance mode setting register */
64 /* when LCR register equal to 0xBF */
65 #define MOXA_MUST_EFR_REGISTER 0x02
66 /* enchance mode enable */
67 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10
68 /* enchance reister bank set 0, 1, 2 */
69 #define MOXA_MUST_EFR_BANK0 0x00
70 #define MOXA_MUST_EFR_BANK1 0x40
71 #define MOXA_MUST_EFR_BANK2 0x80
72 #define MOXA_MUST_EFR_BANK3 0xC0
73 #define MOXA_MUST_EFR_BANK_MASK 0xC0
75 /* set XON1 value register, when LCR=0xBF and change to bank0 */
76 #define MOXA_MUST_XON1_REGISTER 0x04
78 /* set XON2 value register, when LCR=0xBF and change to bank0 */
79 #define MOXA_MUST_XON2_REGISTER 0x05
81 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
82 #define MOXA_MUST_XOFF1_REGISTER 0x06
84 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
85 #define MOXA_MUST_XOFF2_REGISTER 0x07
87 #define MOXA_MUST_RBRTL_REGISTER 0x04
88 #define MOXA_MUST_RBRTH_REGISTER 0x05
89 #define MOXA_MUST_RBRTI_REGISTER 0x06
90 #define MOXA_MUST_THRTL_REGISTER 0x07
91 #define MOXA_MUST_ENUM_REGISTER 0x04
92 #define MOXA_MUST_HWID_REGISTER 0x05
93 #define MOXA_MUST_ECR_REGISTER 0x06
94 #define MOXA_MUST_CSR_REGISTER 0x07
96 /* good data mode enable */
97 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
98 /* only good data put into RxFIFO */
99 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
101 /* enable CTS interrupt */
102 #define MOXA_MUST_IER_ECTSI 0x80
103 /* enable RTS interrupt */
104 #define MOXA_MUST_IER_ERTSI 0x40
105 /* enable Xon/Xoff interrupt */
106 #define MOXA_MUST_IER_XINT 0x20
107 /* enable GDA interrupt */
108 #define MOXA_MUST_IER_EGDAI 0x10
110 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
112 /* GDA interrupt pending */
113 #define MOXA_MUST_IIR_GDA 0x1C
114 #define MOXA_MUST_IIR_RDA 0x04
115 #define MOXA_MUST_IIR_RTO 0x0C
116 #define MOXA_MUST_IIR_LSR 0x06
118 /* recieved Xon/Xoff or specical interrupt pending */
119 #define MOXA_MUST_IIR_XSC 0x10
121 /* RTS/CTS change state interrupt pending */
122 #define MOXA_MUST_IIR_RTSCTS 0x20
123 #define MOXA_MUST_IIR_MASK 0x3E
125 #define MOXA_MUST_MCR_XON_FLAG 0x40
126 #define MOXA_MUST_MCR_XON_ANY 0x80
127 #define MOXA_MUST_MCR_TX_XON 0x08
129 /* software flow control on chip mask value */
130 #define MOXA_MUST_EFR_SF_MASK 0x0F
131 /* send Xon1/Xoff1 */
132 #define MOXA_MUST_EFR_SF_TX1 0x08
133 /* send Xon2/Xoff2 */
134 #define MOXA_MUST_EFR_SF_TX2 0x04
135 /* send Xon1,Xon2/Xoff1,Xoff2 */
136 #define MOXA_MUST_EFR_SF_TX12 0x0C
137 /* don't send Xon/Xoff */
138 #define MOXA_MUST_EFR_SF_TX_NO 0x00
139 /* Tx software flow control mask */
140 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C
141 /* don't receive Xon/Xoff */
142 #define MOXA_MUST_EFR_SF_RX_NO 0x00
143 /* receive Xon1/Xoff1 */
144 #define MOXA_MUST_EFR_SF_RX1 0x02
145 /* receive Xon2/Xoff2 */
146 #define MOXA_MUST_EFR_SF_RX2 0x01
147 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148 #define MOXA_MUST_EFR_SF_RX12 0x03
149 /* Rx software flow control mask */
150 #define MOXA_MUST_EFR_SF_RX_MASK 0x03
152 #define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
153 u8 __oldlcr, __efr; \
154 __oldlcr = inb((baseio)+UART_LCR); \
155 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
156 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
157 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
158 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
159 outb(__oldlcr, (baseio)+UART_LCR); \
162 #define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
163 u8 __oldlcr, __efr; \
164 __oldlcr = inb((baseio)+UART_LCR); \
165 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
166 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
167 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
168 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
169 outb(__oldlcr, (baseio)+UART_LCR); \
172 #define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
173 u8 __oldlcr, __efr; \
174 __oldlcr = inb((baseio)+UART_LCR); \
175 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
176 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
177 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
178 __efr |= MOXA_MUST_EFR_BANK0; \
179 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
180 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
181 outb(__oldlcr, (baseio)+UART_LCR); \
184 #define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
185 u8 __oldlcr, __efr; \
186 __oldlcr = inb((baseio)+UART_LCR); \
187 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
188 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
189 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
190 __efr |= MOXA_MUST_EFR_BANK0; \
191 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
192 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
193 outb(__oldlcr, (baseio)+UART_LCR); \
196 #define SET_MOXA_MUST_FIFO_VALUE(info) do { \
197 u8 __oldlcr, __efr; \
198 __oldlcr = inb((info)->ioaddr+UART_LCR); \
199 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
200 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
201 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
202 __efr |= MOXA_MUST_EFR_BANK1; \
203 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
204 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
205 MOXA_MUST_RBRTH_REGISTER); \
206 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
207 MOXA_MUST_RBRTI_REGISTER); \
208 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
209 MOXA_MUST_RBRTL_REGISTER); \
210 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
213 #define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
214 u8 __oldlcr, __efr; \
215 __oldlcr = inb((baseio)+UART_LCR); \
216 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
217 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
218 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
219 __efr |= MOXA_MUST_EFR_BANK2; \
220 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
221 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
222 outb(__oldlcr, (baseio)+UART_LCR); \
225 #define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
226 u8 __oldlcr, __efr; \
227 __oldlcr = inb((baseio)+UART_LCR); \
228 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
229 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
230 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
231 __efr |= MOXA_MUST_EFR_BANK2; \
232 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
233 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
234 outb(__oldlcr, (baseio)+UART_LCR); \
237 #define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
238 u8 __oldlcr, __efr; \
239 __oldlcr = inb((baseio)+UART_LCR); \
240 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
241 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
242 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
243 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
244 outb(__oldlcr, (baseio)+UART_LCR); \
247 #define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
248 u8 __oldlcr, __efr; \
249 __oldlcr = inb((baseio)+UART_LCR); \
250 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
251 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
252 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
253 __efr |= MOXA_MUST_EFR_SF_TX1; \
254 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
255 outb(__oldlcr, (baseio)+UART_LCR); \
258 #define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
259 u8 __oldlcr, __efr; \
260 __oldlcr = inb((baseio)+UART_LCR); \
261 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
262 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
263 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
264 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
265 outb(__oldlcr, (baseio)+UART_LCR); \
268 #define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
269 u8 __oldlcr, __efr; \
270 __oldlcr = inb((baseio)+UART_LCR); \
271 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
272 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
273 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
274 __efr |= MOXA_MUST_EFR_SF_RX1; \
275 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
276 outb(__oldlcr, (baseio)+UART_LCR); \
279 #define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
280 u8 __oldlcr, __efr; \
281 __oldlcr = inb((baseio)+UART_LCR); \
282 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
283 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
284 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
285 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
286 outb(__oldlcr, (baseio)+UART_LCR); \