drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gfp.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/spinlock.h>
  32
  33 #include <asm/page.h>
  34 #include <asm/system.h>
  35
  36 #include "fw-ohci.h"
  37 #include "fw-transaction.h"
  38
  39 #define DESCRIPTOR_OUTPUT_MORE          0
  40 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  41 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  42 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  43 #define DESCRIPTOR_STATUS               (1 << 11)
  44 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  45 #define DESCRIPTOR_PING                 (1 << 7)
  46 #define DESCRIPTOR_YY                   (1 << 6)
  47 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  48 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  49 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  50 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  51 #define DESCRIPTOR_WAIT                 (3 << 0)
  52
  53 struct descriptor {
  54         __le16 req_count;
  55         __le16 control;
  56         __le32 data_address;
  57         __le32 branch_address;
  58         __le16 res_count;
  59         __le16 transfer_status;
  60 } __attribute__((aligned(16)));
  61
  62 struct db_descriptor {
  63         __le16 first_size;
  64         __le16 control;
  65         __le16 second_req_count;
  66         __le16 first_req_count;
  67         __le32 branch_address;
  68         __le16 second_res_count;
  69         __le16 first_res_count;
  70         __le32 reserved0;
  71         __le32 first_buffer;
  72         __le32 second_buffer;
  73         __le32 reserved1;
  74 } __attribute__((aligned(16)));
  75
  76 #define CONTROL_SET(regs)       (regs)
  77 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  78 #define COMMAND_PTR(regs)       ((regs) + 12)
  79 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  80
  81 struct ar_buffer {
  82         struct descriptor descriptor;
  83         struct ar_buffer *next;
  84         __le32 data[0];
  85 };
  86
  87 struct ar_context {
  88         struct fw_ohci *ohci;
  89         struct ar_buffer *current_buffer;
  90         struct ar_buffer *last_buffer;
  91         void *pointer;
  92         u32 regs;
  93         struct tasklet_struct tasklet;
  94 };
  95
  96 struct context;
  97
  98 typedef int (*descriptor_callback_t)(struct context *ctx,
  99                                      struct descriptor *d,
 100                                      struct descriptor *last);
 101 struct context {
 102         struct fw_ohci *ohci;
 103         u32 regs;
 104
 105         struct descriptor *buffer;
 106         dma_addr_t buffer_bus;
 107         size_t buffer_size;
 108         struct descriptor *head_descriptor;
 109         struct descriptor *tail_descriptor;
 110         struct descriptor *tail_descriptor_last;
 111         struct descriptor *prev_descriptor;
 112
 113         descriptor_callback_t callback;
 114
 115         struct tasklet_struct tasklet;
 116 };
 117
 118 #define IT_HEADER_SY(v)          ((v) <<  0)
 119 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 120 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 121 #define IT_HEADER_TAG(v)         ((v) << 14)
 122 #define IT_HEADER_SPEED(v)       ((v) << 16)
 123 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 124
 125 struct iso_context {
 126         struct fw_iso_context base;
 127         struct context context;
 128         void *header;
 129         size_t header_length;
 130 };
 131
 132 #define CONFIG_ROM_SIZE 1024
 133
 134 struct fw_ohci {
 135         struct fw_card card;
 136
 137         u32 version;
 138         __iomem char *registers;
 139         dma_addr_t self_id_bus;
 140         __le32 *self_id_cpu;
 141         struct tasklet_struct bus_reset_tasklet;
 142         int node_id;
 143         int generation;
 144         int request_generation;
 145         u32 bus_seconds;
 146
 147         /*
 148          * Spinlock for accessing fw_ohci data.  Never call out of
 149          * this driver with this lock held.
 150          */
 151         spinlock_t lock;
 152         u32 self_id_buffer[512];
 153
 154         /* Config rom buffers */
 155         __be32 *config_rom;
 156         dma_addr_t config_rom_bus;
 157         __be32 *next_config_rom;
 158         dma_addr_t next_config_rom_bus;
 159         u32 next_header;
 160
 161         struct ar_context ar_request_ctx;
 162         struct ar_context ar_response_ctx;
 163         struct context at_request_ctx;
 164         struct context at_response_ctx;
 165
 166         u32 it_context_mask;
 167         struct iso_context *it_context_list;
 168         u32 ir_context_mask;
 169         struct iso_context *ir_context_list;
 170 };
 171
 172 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 173 {
 174         return container_of(card, struct fw_ohci, card);
 175 }
 176
 177 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 178 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 179 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 180 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 181 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 182 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 183
 184 #define CONTEXT_RUN     0x8000
 185 #define CONTEXT_WAKE    0x1000
 186 #define CONTEXT_DEAD    0x0800
 187 #define CONTEXT_ACTIVE  0x0400
 188
 189 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 190 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 191 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 192
 193 #define FW_OHCI_MAJOR                   240
 194 #define OHCI1394_REGISTER_SIZE          0x800
 195 #define OHCI_LOOP_COUNT                 500
 196 #define OHCI1394_PCI_HCI_Control        0x40
 197 #define SELF_ID_BUF_SIZE                0x800
 198 #define OHCI_TCODE_PHY_PACKET           0x0e
 199 #define OHCI_VERSION_1_1                0x010010
 200 #define ISO_BUFFER_SIZE                 (64 * 1024)
 201 #define AT_BUFFER_SIZE                  4096
 202
 203 static char ohci_driver_name[] = KBUILD_MODNAME;
 204
 205 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 206 {
 207         writel(data, ohci->registers + offset);
 208 }
 209
 210 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 211 {
 212         return readl(ohci->registers + offset);
 213 }
 214
 215 static inline void flush_writes(const struct fw_ohci *ohci)
 216 {
 217         /* Do a dummy read to flush writes. */
 218         reg_read(ohci, OHCI1394_Version);
 219 }
 220
 221 static int
 222 ohci_update_phy_reg(struct fw_card *card, int addr,
 223                     int clear_bits, int set_bits)
 224 {
 225         struct fw_ohci *ohci = fw_ohci(card);
 226         u32 val, old;
 227
 228         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 229         flush_writes(ohci);
 230         msleep(2);
 231         val = reg_read(ohci, OHCI1394_PhyControl);
 232         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 233                 fw_error("failed to set phy reg bits.\n");
 234                 return -EBUSY;
 235         }
 236
 237         old = OHCI1394_PhyControl_ReadData(val);
 238         old = (old & ~clear_bits) | set_bits;
 239         reg_write(ohci, OHCI1394_PhyControl,
 240                   OHCI1394_PhyControl_Write(addr, old));
 241
 242         return 0;
 243 }
 244
 245 static int ar_context_add_page(struct ar_context *ctx)
 246 {
 247         struct device *dev = ctx->ohci->card.device;
 248         struct ar_buffer *ab;
 249         dma_addr_t ab_bus;
 250         size_t offset;
 251
 252         ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
 253         if (ab == NULL)
 254                 return -ENOMEM;
 255
 256         ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
 257         if (dma_mapping_error(ab_bus)) {
 258                 free_page((unsigned long) ab);
 259                 return -ENOMEM;
 260         }
 261
 262         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 263         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 264                                                     DESCRIPTOR_STATUS |
 265                                                     DESCRIPTOR_BRANCH_ALWAYS);
 266         offset = offsetof(struct ar_buffer, data);
 267         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 268         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 269         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 270         ab->descriptor.branch_address = 0;
 271
 272         dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 273
 274         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 275         ctx->last_buffer->next = ab;
 276         ctx->last_buffer = ab;
 277
 278         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 279         flush_writes(ctx->ohci);
 280
 281         return 0;
 282 }
 283
 284 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 285 {
 286         struct fw_ohci *ohci = ctx->ohci;
 287         struct fw_packet p;
 288         u32 status, length, tcode;
 289
 290         p.header[0] = le32_to_cpu(buffer[0]);
 291         p.header[1] = le32_to_cpu(buffer[1]);
 292         p.header[2] = le32_to_cpu(buffer[2]);
 293
 294         tcode = (p.header[0] >> 4) & 0x0f;
 295         switch (tcode) {
 296         case TCODE_WRITE_QUADLET_REQUEST:
 297         case TCODE_READ_QUADLET_RESPONSE:
 298                 p.header[3] = (__force __u32) buffer[3];
 299                 p.header_length = 16;
 300                 p.payload_length = 0;
 301                 break;
 302
 303         case TCODE_READ_BLOCK_REQUEST :
 304                 p.header[3] = le32_to_cpu(buffer[3]);
 305                 p.header_length = 16;
 306                 p.payload_length = 0;
 307                 break;
 308
 309         case TCODE_WRITE_BLOCK_REQUEST:
 310         case TCODE_READ_BLOCK_RESPONSE:
 311         case TCODE_LOCK_REQUEST:
 312         case TCODE_LOCK_RESPONSE:
 313                 p.header[3] = le32_to_cpu(buffer[3]);
 314                 p.header_length = 16;
 315                 p.payload_length = p.header[3] >> 16;
 316                 break;
 317
 318         case TCODE_WRITE_RESPONSE:
 319         case TCODE_READ_QUADLET_REQUEST:
 320         case OHCI_TCODE_PHY_PACKET:
 321                 p.header_length = 12;
 322                 p.payload_length = 0;
 323                 break;
 324         }
 325
 326         p.payload = (void *) buffer + p.header_length;
 327
 328         /* FIXME: What to do about evt_* errors? */
 329         length = (p.header_length + p.payload_length + 3) / 4;
 330         status = le32_to_cpu(buffer[length]);
 331
 332         p.ack        = ((status >> 16) & 0x1f) - 16;
 333         p.speed      = (status >> 21) & 0x7;
 334         p.timestamp  = status & 0xffff;
 335         p.generation = ohci->request_generation;
 336
 337         /*
 338          * The OHCI bus reset handler synthesizes a phy packet with
 339          * the new generation number when a bus reset happens (see
 340          * section 8.4.2.3).  This helps us determine when a request
 341          * was received and make sure we send the response in the same
 342          * generation.  We only need this for requests; for responses
 343          * we use the unique tlabel for finding the matching
 344          * request.
 345          */
 346
 347         if (p.ack + 16 == 0x09)
 348                 ohci->request_generation = (buffer[2] >> 16) & 0xff;
 349         else if (ctx == &ohci->ar_request_ctx)
 350                 fw_core_handle_request(&ohci->card, &p);
 351         else
 352                 fw_core_handle_response(&ohci->card, &p);
 353
 354         return buffer + length + 1;
 355 }
 356
 357 static void ar_context_tasklet(unsigned long data)
 358 {
 359         struct ar_context *ctx = (struct ar_context *)data;
 360         struct fw_ohci *ohci = ctx->ohci;
 361         struct ar_buffer *ab;
 362         struct descriptor *d;
 363         void *buffer, *end;
 364
 365         ab = ctx->current_buffer;
 366         d = &ab->descriptor;
 367
 368         if (d->res_count == 0) {
 369                 size_t size, rest, offset;
 370
 371                 /*
 372                  * This descriptor is finished and we may have a
 373                  * packet split across this and the next buffer. We
 374                  * reuse the page for reassembling the split packet.
 375                  */
 376
 377                 offset = offsetof(struct ar_buffer, data);
 378                 dma_unmap_single(ohci->card.device,
 379                         le32_to_cpu(ab->descriptor.data_address) - offset,
 380                         PAGE_SIZE, DMA_BIDIRECTIONAL);
 381
 382                 buffer = ab;
 383                 ab = ab->next;
 384                 d = &ab->descriptor;
 385                 size = buffer + PAGE_SIZE - ctx->pointer;
 386                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 387                 memmove(buffer, ctx->pointer, size);
 388                 memcpy(buffer + size, ab->data, rest);
 389                 ctx->current_buffer = ab;
 390                 ctx->pointer = (void *) ab->data + rest;
 391                 end = buffer + size + rest;
 392
 393                 while (buffer < end)
 394                         buffer = handle_ar_packet(ctx, buffer);
 395
 396                 free_page((unsigned long)buffer);
 397                 ar_context_add_page(ctx);
 398         } else {
 399                 buffer = ctx->pointer;
 400                 ctx->pointer = end =
 401                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 402
 403                 while (buffer < end)
 404                         buffer = handle_ar_packet(ctx, buffer);
 405         }
 406 }
 407
 408 static int
 409 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 410 {
 411         struct ar_buffer ab;
 412
 413         ctx->regs        = regs;
 414         ctx->ohci        = ohci;
 415         ctx->last_buffer = &ab;
 416         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 417
 418         ar_context_add_page(ctx);
 419         ar_context_add_page(ctx);
 420         ctx->current_buffer = ab.next;
 421         ctx->pointer = ctx->current_buffer->data;
 422
 423         return 0;
 424 }
 425
 426 static void ar_context_run(struct ar_context *ctx)
 427 {
 428         struct ar_buffer *ab = ctx->current_buffer;
 429         dma_addr_t ab_bus;
 430         size_t offset;
 431
 432         offset = offsetof(struct ar_buffer, data);
 433         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 434
 435         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 436         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 437         flush_writes(ctx->ohci);
 438 }
 439
 440 static void context_tasklet(unsigned long data)
 441 {
 442         struct context *ctx = (struct context *) data;
 443         struct fw_ohci *ohci = ctx->ohci;
 444         struct descriptor *d, *last;
 445         u32 address;
 446         int z;
 447
 448         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
 449                                 ctx->buffer_size, DMA_TO_DEVICE);
 450
 451         d    = ctx->tail_descriptor;
 452         last = ctx->tail_descriptor_last;
 453
 454         while (last->branch_address != 0) {
 455                 address = le32_to_cpu(last->branch_address);
 456                 z = address & 0xf;
 457                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
 458                 last = (z == 2) ? d : d + z - 1;
 459
 460                 if (!ctx->callback(ctx, d, last))
 461                         break;
 462
 463                 ctx->tail_descriptor      = d;
 464                 ctx->tail_descriptor_last = last;
 465         }
 466 }
 467
 468 static int
 469 context_init(struct context *ctx, struct fw_ohci *ohci,
 470              size_t buffer_size, u32 regs,
 471              descriptor_callback_t callback)
 472 {
 473         ctx->ohci = ohci;
 474         ctx->regs = regs;
 475         ctx->buffer_size = buffer_size;
 476         ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
 477         if (ctx->buffer == NULL)
 478                 return -ENOMEM;
 479
 480         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 481         ctx->callback = callback;
 482
 483         ctx->buffer_bus =
 484                 dma_map_single(ohci->card.device, ctx->buffer,
 485                                buffer_size, DMA_TO_DEVICE);
 486         if (dma_mapping_error(ctx->buffer_bus)) {
 487                 kfree(ctx->buffer);
 488                 return -ENOMEM;
 489         }
 490
 491         ctx->head_descriptor      = ctx->buffer;
 492         ctx->prev_descriptor      = ctx->buffer;
 493         ctx->tail_descriptor      = ctx->buffer;
 494         ctx->tail_descriptor_last = ctx->buffer;
 495
 496         /*
 497          * We put a dummy descriptor in the buffer that has a NULL
 498          * branch address and looks like it's been sent.  That way we
 499          * have a descriptor to append DMA programs to.  Also, the
 500          * ring buffer invariant is that it always has at least one
 501          * element so that head == tail means buffer full.
 502          */
 503
 504         memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
 505         ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 506         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
 507         ctx->head_descriptor++;
 508
 509         return 0;
 510 }
 511
 512 static void
 513 context_release(struct context *ctx)
 514 {
 515         struct fw_card *card = &ctx->ohci->card;
 516
 517         dma_unmap_single(card->device, ctx->buffer_bus,
 518                          ctx->buffer_size, DMA_TO_DEVICE);
 519         kfree(ctx->buffer);
 520 }
 521
 522 static struct descriptor *
 523 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 524 {
 525         struct descriptor *d, *tail, *end;
 526
 527         d = ctx->head_descriptor;
 528         tail = ctx->tail_descriptor;
 529         end = ctx->buffer + ctx->buffer_size / sizeof(*d);
 530
 531         if (d + z <= tail) {
 532                 goto has_space;
 533         } else if (d > tail && d + z <= end) {
 534                 goto has_space;
 535         } else if (d > tail && ctx->buffer + z <= tail) {
 536                 d = ctx->buffer;
 537                 goto has_space;
 538         }
 539
 540         return NULL;
 541
 542  has_space:
 543         memset(d, 0, z * sizeof(*d));
 544         *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 545
 546         return d;
 547 }
 548
 549 static void context_run(struct context *ctx, u32 extra)
 550 {
 551         struct fw_ohci *ohci = ctx->ohci;
 552
 553         reg_write(ohci, COMMAND_PTR(ctx->regs),
 554                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
 555         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 556         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 557         flush_writes(ohci);
 558 }
 559
 560 static void context_append(struct context *ctx,
 561                            struct descriptor *d, int z, int extra)
 562 {
 563         dma_addr_t d_bus;
 564
 565         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 566
 567         ctx->head_descriptor = d + z + extra;
 568         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
 569         ctx->prev_descriptor = z == 2 ? d : d + z - 1;
 570
 571         dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
 572                                    ctx->buffer_size, DMA_TO_DEVICE);
 573
 574         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 575         flush_writes(ctx->ohci);
 576 }
 577
 578 static void context_stop(struct context *ctx)
 579 {
 580         u32 reg;
 581         int i;
 582
 583         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 584         flush_writes(ctx->ohci);
 585
 586         for (i = 0; i < 10; i++) {
 587                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 588                 if ((reg & CONTEXT_ACTIVE) == 0)
 589                         break;
 590
 591                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 592                 mdelay(1);
 593         }
 594 }
 595
 596 struct driver_data {
 597         struct fw_packet *packet;
 598 };
 599
 600 /*
 601  * This function apppends a packet to the DMA queue for transmission.
 602  * Must always be called with the ochi->lock held to ensure proper
 603  * generation handling and locking around packet queue manipulation.
 604  */
 605 static int
 606 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 607 {
 608         struct fw_ohci *ohci = ctx->ohci;
 609         dma_addr_t d_bus, payload_bus;
 610         struct driver_data *driver_data;
 611         struct descriptor *d, *last;
 612         __le32 *header;
 613         int z, tcode;
 614         u32 reg;
 615
 616         d = context_get_descriptors(ctx, 4, &d_bus);
 617         if (d == NULL) {
 618                 packet->ack = RCODE_SEND_ERROR;
 619                 return -1;
 620         }
 621
 622         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 623         d[0].res_count = cpu_to_le16(packet->timestamp);
 624
 625         /*
 626          * The DMA format for asyncronous link packets is different
 627          * from the IEEE1394 layout, so shift the fields around
 628          * accordingly.  If header_length is 8, it's a PHY packet, to
 629          * which we need to prepend an extra quadlet.
 630          */
 631
 632         header = (__le32 *) &d[1];
 633         if (packet->header_length > 8) {
 634                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 635                                         (packet->speed << 16));
 636                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 637                                         (packet->header[0] & 0xffff0000));
 638                 header[2] = cpu_to_le32(packet->header[2]);
 639
 640                 tcode = (packet->header[0] >> 4) & 0x0f;
 641                 if (TCODE_IS_BLOCK_PACKET(tcode))
 642                         header[3] = cpu_to_le32(packet->header[3]);
 643                 else
 644                         header[3] = (__force __le32) packet->header[3];
 645
 646                 d[0].req_count = cpu_to_le16(packet->header_length);
 647         } else {
 648                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 649                                         (packet->speed << 16));
 650                 header[1] = cpu_to_le32(packet->header[0]);
 651                 header[2] = cpu_to_le32(packet->header[1]);
 652                 d[0].req_count = cpu_to_le16(12);
 653         }
 654
 655         driver_data = (struct driver_data *) &d[3];
 656         driver_data->packet = packet;
 657         packet->driver_data = driver_data;
 658
 659         if (packet->payload_length > 0) {
 660                 payload_bus =
 661                         dma_map_single(ohci->card.device, packet->payload,
 662                                        packet->payload_length, DMA_TO_DEVICE);
 663                 if (dma_mapping_error(payload_bus)) {
 664                         packet->ack = RCODE_SEND_ERROR;
 665                         return -1;
 666                 }
 667
 668                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 669                 d[2].data_address = cpu_to_le32(payload_bus);
 670                 last = &d[2];
 671                 z = 3;
 672         } else {
 673                 last = &d[0];
 674                 z = 2;
 675         }
 676
 677         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 678                                      DESCRIPTOR_IRQ_ALWAYS |
 679                                      DESCRIPTOR_BRANCH_ALWAYS);
 680
 681         /* FIXME: Document how the locking works. */
 682         if (ohci->generation != packet->generation) {
 683                 packet->ack = RCODE_GENERATION;
 684                 return -1;
 685         }
 686
 687         context_append(ctx, d, z, 4 - z);
 688
 689         /* If the context isn't already running, start it up. */
 690         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 691         if ((reg & CONTEXT_RUN) == 0)
 692                 context_run(ctx, 0);
 693
 694         return 0;
 695 }
 696
 697 static int handle_at_packet(struct context *context,
 698                             struct descriptor *d,
 699                             struct descriptor *last)
 700 {
 701         struct driver_data *driver_data;
 702         struct fw_packet *packet;
 703         struct fw_ohci *ohci = context->ohci;
 704         dma_addr_t payload_bus;
 705         int evt;
 706
 707         if (last->transfer_status == 0)
 708                 /* This descriptor isn't done yet, stop iteration. */
 709                 return 0;
 710
 711         driver_data = (struct driver_data *) &d[3];
 712         packet = driver_data->packet;
 713         if (packet == NULL)
 714                 /* This packet was cancelled, just continue. */
 715                 return 1;
 716
 717         payload_bus = le32_to_cpu(last->data_address);
 718         if (payload_bus != 0)
 719                 dma_unmap_single(ohci->card.device, payload_bus,
 720                                  packet->payload_length, DMA_TO_DEVICE);
 721
 722         evt = le16_to_cpu(last->transfer_status) & 0x1f;
 723         packet->timestamp = le16_to_cpu(last->res_count);
 724
 725         switch (evt) {
 726         case OHCI1394_evt_timeout:
 727                 /* Async response transmit timed out. */
 728                 packet->ack = RCODE_CANCELLED;
 729                 break;
 730
 731         case OHCI1394_evt_flushed:
 732                 /*
 733                  * The packet was flushed should give same error as
 734                  * when we try to use a stale generation count.
 735                  */
 736                 packet->ack = RCODE_GENERATION;
 737                 break;
 738
 739         case OHCI1394_evt_missing_ack:
 740                 /*
 741                  * Using a valid (current) generation count, but the
 742                  * node is not on the bus or not sending acks.
 743                  */
 744                 packet->ack = RCODE_NO_ACK;
 745                 break;
 746
 747         case ACK_COMPLETE + 0x10:
 748         case ACK_PENDING + 0x10:
 749         case ACK_BUSY_X + 0x10:
 750         case ACK_BUSY_A + 0x10:
 751         case ACK_BUSY_B + 0x10:
 752         case ACK_DATA_ERROR + 0x10:
 753         case ACK_TYPE_ERROR + 0x10:
 754                 packet->ack = evt - 0x10;
 755                 break;
 756
 757         default:
 758                 packet->ack = RCODE_SEND_ERROR;
 759                 break;
 760         }
 761
 762         packet->callback(packet, &ohci->card, packet->ack);
 763
 764         return 1;
 765 }
 766
 767 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
 768 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
 769 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
 770 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
 771 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
 772
 773 static void
 774 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 775 {
 776         struct fw_packet response;
 777         int tcode, length, i;
 778
 779         tcode = HEADER_GET_TCODE(packet->header[0]);
 780         if (TCODE_IS_BLOCK_PACKET(tcode))
 781                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 782         else
 783                 length = 4;
 784
 785         i = csr - CSR_CONFIG_ROM;
 786         if (i + length > CONFIG_ROM_SIZE) {
 787                 fw_fill_response(&response, packet->header,
 788                                  RCODE_ADDRESS_ERROR, NULL, 0);
 789         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
 790                 fw_fill_response(&response, packet->header,
 791                                  RCODE_TYPE_ERROR, NULL, 0);
 792         } else {
 793                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
 794                                  (void *) ohci->config_rom + i, length);
 795         }
 796
 797         fw_core_handle_response(&ohci->card, &response);
 798 }
 799
 800 static void
 801 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 802 {
 803         struct fw_packet response;
 804         int tcode, length, ext_tcode, sel;
 805         __be32 *payload, lock_old;
 806         u32 lock_arg, lock_data;
 807
 808         tcode = HEADER_GET_TCODE(packet->header[0]);
 809         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 810         payload = packet->payload;
 811         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
 812
 813         if (tcode == TCODE_LOCK_REQUEST &&
 814             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
 815                 lock_arg = be32_to_cpu(payload[0]);
 816                 lock_data = be32_to_cpu(payload[1]);
 817         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
 818                 lock_arg = 0;
 819                 lock_data = 0;
 820         } else {
 821                 fw_fill_response(&response, packet->header,
 822                                  RCODE_TYPE_ERROR, NULL, 0);
 823                 goto out;
 824         }
 825
 826         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 827         reg_write(ohci, OHCI1394_CSRData, lock_data);
 828         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 829         reg_write(ohci, OHCI1394_CSRControl, sel);
 830
 831         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
 832                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
 833         else
 834                 fw_notify("swap not done yet\n");
 835
 836         fw_fill_response(&response, packet->header,
 837                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
 838  out:
 839         fw_core_handle_response(&ohci->card, &response);
 840 }
 841
 842 static void
 843 handle_local_request(struct context *ctx, struct fw_packet *packet)
 844 {
 845         u64 offset;
 846         u32 csr;
 847
 848         if (ctx == &ctx->ohci->at_request_ctx) {
 849                 packet->ack = ACK_PENDING;
 850                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 851         }
 852
 853         offset =
 854                 ((unsigned long long)
 855                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
 856                 packet->header[2];
 857         csr = offset - CSR_REGISTER_BASE;
 858
 859         /* Handle config rom reads. */
 860         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
 861                 handle_local_rom(ctx->ohci, packet, csr);
 862         else switch (csr) {
 863         case CSR_BUS_MANAGER_ID:
 864         case CSR_BANDWIDTH_AVAILABLE:
 865         case CSR_CHANNELS_AVAILABLE_HI:
 866         case CSR_CHANNELS_AVAILABLE_LO:
 867                 handle_local_lock(ctx->ohci, packet, csr);
 868                 break;
 869         default:
 870                 if (ctx == &ctx->ohci->at_request_ctx)
 871                         fw_core_handle_request(&ctx->ohci->card, packet);
 872                 else
 873                         fw_core_handle_response(&ctx->ohci->card, packet);
 874                 break;
 875         }
 876
 877         if (ctx == &ctx->ohci->at_response_ctx) {
 878                 packet->ack = ACK_COMPLETE;
 879                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 880         }
 881 }
 882
 883 static void
 884 at_context_transmit(struct context *ctx, struct fw_packet *packet)
 885 {
 886         unsigned long flags;
 887         int retval;
 888
 889         spin_lock_irqsave(&ctx->ohci->lock, flags);
 890
 891         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
 892             ctx->ohci->generation == packet->generation) {
 893                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 894                 handle_local_request(ctx, packet);
 895                 return;
 896         }
 897
 898         retval = at_context_queue_packet(ctx, packet);
 899         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 900
 901         if (retval < 0)
 902                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 903
 904 }
 905
 906 static void bus_reset_tasklet(unsigned long data)
 907 {
 908         struct fw_ohci *ohci = (struct fw_ohci *)data;
 909         int self_id_count, i, j, reg;
 910         int generation, new_generation;
 911         unsigned long flags;
 912         void *free_rom = NULL;
 913         dma_addr_t free_rom_bus = 0;
 914
 915         reg = reg_read(ohci, OHCI1394_NodeID);
 916         if (!(reg & OHCI1394_NodeID_idValid)) {
 917                 fw_error("node ID not valid, new bus reset in progress\n");
 918                 return;
 919         }
 920         ohci->node_id = reg & 0xffff;
 921
 922         /*
 923          * The count in the SelfIDCount register is the number of
 924          * bytes in the self ID receive buffer.  Since we also receive
 925          * the inverted quadlets and a header quadlet, we shift one
 926          * bit extra to get the actual number of self IDs.
 927          */
 928
 929         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
 930         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 931         rmb();
 932
 933         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 934                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
 935                         fw_error("inconsistent self IDs\n");
 936                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
 937         }
 938         rmb();
 939
 940         /*
 941          * Check the consistency of the self IDs we just read.  The
 942          * problem we face is that a new bus reset can start while we
 943          * read out the self IDs from the DMA buffer. If this happens,
 944          * the DMA buffer will be overwritten with new self IDs and we
 945          * will read out inconsistent data.  The OHCI specification
 946          * (section 11.2) recommends a technique similar to
 947          * linux/seqlock.h, where we remember the generation of the
 948          * self IDs in the buffer before reading them out and compare
 949          * it to the current generation after reading them out.  If
 950          * the two generations match we know we have a consistent set
 951          * of self IDs.
 952          */
 953
 954         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 955         if (new_generation != generation) {
 956                 fw_notify("recursive bus reset detected, "
 957                           "discarding self ids\n");
 958                 return;
 959         }
 960
 961         /* FIXME: Document how the locking works. */
 962         spin_lock_irqsave(&ohci->lock, flags);
 963
 964         ohci->generation = generation;
 965         context_stop(&ohci->at_request_ctx);
 966         context_stop(&ohci->at_response_ctx);
 967         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 968
 969         /*
 970          * This next bit is unrelated to the AT context stuff but we
 971          * have to do it under the spinlock also.  If a new config rom
 972          * was set up before this reset, the old one is now no longer
 973          * in use and we can free it. Update the config rom pointers
 974          * to point to the current config rom and clear the
 975          * next_config_rom pointer so a new udpate can take place.
 976          */
 977
 978         if (ohci->next_config_rom != NULL) {
 979                 free_rom     = ohci->config_rom;
 980                 free_rom_bus = ohci->config_rom_bus;
 981                 ohci->config_rom      = ohci->next_config_rom;
 982                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
 983                 ohci->next_config_rom = NULL;
 984
 985                 /*
 986                  * Restore config_rom image and manually update
 987                  * config_rom registers.  Writing the header quadlet
 988                  * will indicate that the config rom is ready, so we
 989                  * do that last.
 990                  */
 991                 reg_write(ohci, OHCI1394_BusOptions,
 992                           be32_to_cpu(ohci->config_rom[2]));
 993                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
 994                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
 995         }
 996
 997         spin_unlock_irqrestore(&ohci->lock, flags);
 998
 999         if (free_rom)
1000                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1001                                   free_rom, free_rom_bus);
1002
1003         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1004                                  self_id_count, ohci->self_id_buffer);
1005 }
1006
1007 static irqreturn_t irq_handler(int irq, void *data)
1008 {
1009         struct fw_ohci *ohci = data;
1010         u32 event, iso_event, cycle_time;
1011         int i;
1012
1013         event = reg_read(ohci, OHCI1394_IntEventClear);
1014
1015         if (!event || !~event)
1016                 return IRQ_NONE;
1017
1018         reg_write(ohci, OHCI1394_IntEventClear, event);
1019
1020         if (event & OHCI1394_selfIDComplete)
1021                 tasklet_schedule(&ohci->bus_reset_tasklet);
1022
1023         if (event & OHCI1394_RQPkt)
1024                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1025
1026         if (event & OHCI1394_RSPkt)
1027                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1028
1029         if (event & OHCI1394_reqTxComplete)
1030                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1031
1032         if (event & OHCI1394_respTxComplete)
1033                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1034
1035         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1036         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1037
1038         while (iso_event) {
1039                 i = ffs(iso_event) - 1;
1040                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1041                 iso_event &= ~(1 << i);
1042         }
1043
1044         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1045         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1046
1047         while (iso_event) {
1048                 i = ffs(iso_event) - 1;
1049                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1050                 iso_event &= ~(1 << i);
1051         }
1052
1053         if (unlikely(event & OHCI1394_postedWriteErr))
1054                 fw_error("PCI posted write error\n");
1055
1056         if (event & OHCI1394_cycle64Seconds) {
1057                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1058                 if ((cycle_time & 0x80000000) == 0)
1059                         ohci->bus_seconds++;
1060         }
1061
1062         return IRQ_HANDLED;
1063 }
1064
1065 static int software_reset(struct fw_ohci *ohci)
1066 {
1067         int i;
1068
1069         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1070
1071         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1072                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1073                      OHCI1394_HCControl_softReset) == 0)
1074                         return 0;
1075                 msleep(1);
1076         }
1077
1078         return -EBUSY;
1079 }
1080
1081 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1082 {
1083         struct fw_ohci *ohci = fw_ohci(card);
1084         struct pci_dev *dev = to_pci_dev(card->device);
1085
1086         if (software_reset(ohci)) {
1087                 fw_error("Failed to reset ohci card.\n");
1088                 return -EBUSY;
1089         }
1090
1091         /*
1092          * Now enable LPS, which we need in order to start accessing
1093          * most of the registers.  In fact, on some cards (ALI M5251),
1094          * accessing registers in the SClk domain without LPS enabled
1095          * will lock up the machine.  Wait 50msec to make sure we have
1096          * full link enabled.
1097          */
1098         reg_write(ohci, OHCI1394_HCControlSet,
1099                   OHCI1394_HCControl_LPS |
1100                   OHCI1394_HCControl_postedWriteEnable);
1101         flush_writes(ohci);
1102         msleep(50);
1103
1104         reg_write(ohci, OHCI1394_HCControlClear,
1105                   OHCI1394_HCControl_noByteSwapData);
1106
1107         reg_write(ohci, OHCI1394_LinkControlSet,
1108                   OHCI1394_LinkControl_rcvSelfID |
1109                   OHCI1394_LinkControl_cycleTimerEnable |
1110                   OHCI1394_LinkControl_cycleMaster);
1111
1112         reg_write(ohci, OHCI1394_ATRetries,
1113                   OHCI1394_MAX_AT_REQ_RETRIES |
1114                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1115                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1116
1117         ar_context_run(&ohci->ar_request_ctx);
1118         ar_context_run(&ohci->ar_response_ctx);
1119
1120         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1121         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1122         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1123         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1124         reg_write(ohci, OHCI1394_IntMaskSet,
1125                   OHCI1394_selfIDComplete |
1126                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1127                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1128                   OHCI1394_isochRx | OHCI1394_isochTx |
1129                   OHCI1394_postedWriteErr | OHCI1394_cycle64Seconds |
1130                   OHCI1394_masterIntEnable);
1131
1132         /* Activate link_on bit and contender bit in our self ID packets.*/
1133         if (ohci_update_phy_reg(card, 4, 0,
1134                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1135                 return -EIO;
1136
1137         /*
1138          * When the link is not yet enabled, the atomic config rom
1139          * update mechanism described below in ohci_set_config_rom()
1140          * is not active.  We have to update ConfigRomHeader and
1141          * BusOptions manually, and the write to ConfigROMmap takes
1142          * effect immediately.  We tie this to the enabling of the
1143          * link, so we have a valid config rom before enabling - the
1144          * OHCI requires that ConfigROMhdr and BusOptions have valid
1145          * values before enabling.
1146          *
1147          * However, when the ConfigROMmap is written, some controllers
1148          * always read back quadlets 0 and 2 from the config rom to
1149          * the ConfigRomHeader and BusOptions registers on bus reset.
1150          * They shouldn't do that in this initial case where the link
1151          * isn't enabled.  This means we have to use the same
1152          * workaround here, setting the bus header to 0 and then write
1153          * the right values in the bus reset tasklet.
1154          */
1155
1156         ohci->next_config_rom =
1157                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1158                                    &ohci->next_config_rom_bus, GFP_KERNEL);
1159         if (ohci->next_config_rom == NULL)
1160                 return -ENOMEM;
1161
1162         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1163         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1164
1165         ohci->next_header = config_rom[0];
1166         ohci->next_config_rom[0] = 0;
1167         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1168         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1169         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1170
1171         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1172
1173         if (request_irq(dev->irq, irq_handler,
1174                         IRQF_SHARED, ohci_driver_name, ohci)) {
1175                 fw_error("Failed to allocate shared interrupt %d.\n",
1176                          dev->irq);
1177                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1178                                   ohci->config_rom, ohci->config_rom_bus);
1179                 return -EIO;
1180         }
1181
1182         reg_write(ohci, OHCI1394_HCControlSet,
1183                   OHCI1394_HCControl_linkEnable |
1184                   OHCI1394_HCControl_BIBimageValid);
1185         flush_writes(ohci);
1186
1187         /*
1188          * We are ready to go, initiate bus reset to finish the
1189          * initialization.
1190          */
1191
1192         fw_core_initiate_bus_reset(&ohci->card, 1);
1193
1194         return 0;
1195 }
1196
1197 static int
1198 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1199 {
1200         struct fw_ohci *ohci;
1201         unsigned long flags;
1202         int retval = -EBUSY;
1203         __be32 *next_config_rom;
1204         dma_addr_t next_config_rom_bus;
1205
1206         ohci = fw_ohci(card);
1207
1208         /*
1209          * When the OHCI controller is enabled, the config rom update
1210          * mechanism is a bit tricky, but easy enough to use.  See
1211          * section 5.5.6 in the OHCI specification.
1212          *
1213          * The OHCI controller caches the new config rom address in a
1214          * shadow register (ConfigROMmapNext) and needs a bus reset
1215          * for the changes to take place.  When the bus reset is
1216          * detected, the controller loads the new values for the
1217          * ConfigRomHeader and BusOptions registers from the specified
1218          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1219          * shadow register. All automatically and atomically.
1220          *
1221          * Now, there's a twist to this story.  The automatic load of
1222          * ConfigRomHeader and BusOptions doesn't honor the
1223          * noByteSwapData bit, so with a be32 config rom, the
1224          * controller will load be32 values in to these registers
1225          * during the atomic update, even on litte endian
1226          * architectures.  The workaround we use is to put a 0 in the
1227          * header quadlet; 0 is endian agnostic and means that the
1228          * config rom isn't ready yet.  In the bus reset tasklet we
1229          * then set up the real values for the two registers.
1230          *
1231          * We use ohci->lock to avoid racing with the code that sets
1232          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1233          */
1234
1235         next_config_rom =
1236                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1237                                    &next_config_rom_bus, GFP_KERNEL);
1238         if (next_config_rom == NULL)
1239                 return -ENOMEM;
1240
1241         spin_lock_irqsave(&ohci->lock, flags);
1242
1243         if (ohci->next_config_rom == NULL) {
1244                 ohci->next_config_rom = next_config_rom;
1245                 ohci->next_config_rom_bus = next_config_rom_bus;
1246
1247                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1248                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1249                                   length * 4);
1250
1251                 ohci->next_header = config_rom[0];
1252                 ohci->next_config_rom[0] = 0;
1253
1254                 reg_write(ohci, OHCI1394_ConfigROMmap,
1255                           ohci->next_config_rom_bus);
1256                 retval = 0;
1257         }
1258
1259         spin_unlock_irqrestore(&ohci->lock, flags);
1260
1261         /*
1262          * Now initiate a bus reset to have the changes take
1263          * effect. We clean up the old config rom memory and DMA
1264          * mappings in the bus reset tasklet, since the OHCI
1265          * controller could need to access it before the bus reset
1266          * takes effect.
1267          */
1268         if (retval == 0)
1269                 fw_core_initiate_bus_reset(&ohci->card, 1);
1270         else
1271                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1272                                   next_config_rom, next_config_rom_bus);
1273
1274         return retval;
1275 }
1276
1277 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1278 {
1279         struct fw_ohci *ohci = fw_ohci(card);
1280
1281         at_context_transmit(&ohci->at_request_ctx, packet);
1282 }
1283
1284 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1285 {
1286         struct fw_ohci *ohci = fw_ohci(card);
1287
1288         at_context_transmit(&ohci->at_response_ctx, packet);
1289 }
1290
1291 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1292 {
1293         struct fw_ohci *ohci = fw_ohci(card);
1294         struct context *ctx = &ohci->at_request_ctx;
1295         struct driver_data *driver_data = packet->driver_data;
1296         int retval = -ENOENT;
1297
1298         tasklet_disable(&ctx->tasklet);
1299
1300         if (packet->ack != 0)
1301                 goto out;
1302
1303         driver_data->packet = NULL;
1304         packet->ack = RCODE_CANCELLED;
1305         packet->callback(packet, &ohci->card, packet->ack);
1306         retval = 0;
1307
1308  out:
1309         tasklet_enable(&ctx->tasklet);
1310
1311         return retval;
1312 }
1313
1314 static int
1315 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1316 {
1317         struct fw_ohci *ohci = fw_ohci(card);
1318         unsigned long flags;
1319         int n, retval = 0;
1320
1321         /*
1322          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1323          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1324          */
1325
1326         spin_lock_irqsave(&ohci->lock, flags);
1327
1328         if (ohci->generation != generation) {
1329                 retval = -ESTALE;
1330                 goto out;
1331         }
1332
1333         /*
1334          * Note, if the node ID contains a non-local bus ID, physical DMA is
1335          * enabled for _all_ nodes on remote buses.
1336          */
1337
1338         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1339         if (n < 32)
1340                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1341         else
1342                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1343
1344         flush_writes(ohci);
1345  out:
1346         spin_unlock_irqrestore(&ohci->lock, flags);
1347         return retval;
1348 }
1349
1350 static u64
1351 ohci_get_bus_time(struct fw_card *card)
1352 {
1353         struct fw_ohci *ohci = fw_ohci(card);
1354         u32 cycle_time;
1355         u64 bus_time;
1356
1357         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1358         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1359
1360         return bus_time;
1361 }
1362
1363 static int handle_ir_dualbuffer_packet(struct context *context,
1364                                        struct descriptor *d,
1365                                        struct descriptor *last)
1366 {
1367         struct iso_context *ctx =
1368                 container_of(context, struct iso_context, context);
1369         struct db_descriptor *db = (struct db_descriptor *) d;
1370         __le32 *ir_header;
1371         size_t header_length;
1372         void *p, *end;
1373         int i;
1374
1375         if (db->first_res_count > 0 && db->second_res_count > 0)
1376                 /* This descriptor isn't done yet, stop iteration. */
1377                 return 0;
1378
1379         header_length = le16_to_cpu(db->first_req_count) -
1380                 le16_to_cpu(db->first_res_count);
1381
1382         i = ctx->header_length;
1383         p = db + 1;
1384         end = p + header_length;
1385         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1386                 /*
1387                  * The iso header is byteswapped to little endian by
1388                  * the controller, but the remaining header quadlets
1389                  * are big endian.  We want to present all the headers
1390                  * as big endian, so we have to swap the first
1391                  * quadlet.
1392                  */
1393                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1394                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1395                 i += ctx->base.header_size;
1396                 p += ctx->base.header_size + 4;
1397         }
1398
1399         ctx->header_length = i;
1400
1401         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1402                 ir_header = (__le32 *) (db + 1);
1403                 ctx->base.callback(&ctx->base,
1404                                    le32_to_cpu(ir_header[0]) & 0xffff,
1405                                    ctx->header_length, ctx->header,
1406                                    ctx->base.callback_data);
1407                 ctx->header_length = 0;
1408         }
1409
1410         return 1;
1411 }
1412
1413 static int handle_it_packet(struct context *context,
1414                             struct descriptor *d,
1415                             struct descriptor *last)
1416 {
1417         struct iso_context *ctx =
1418                 container_of(context, struct iso_context, context);
1419
1420         if (last->transfer_status == 0)
1421                 /* This descriptor isn't done yet, stop iteration. */
1422                 return 0;
1423
1424         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1425                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1426                                    0, NULL, ctx->base.callback_data);
1427
1428         return 1;
1429 }
1430
1431 static struct fw_iso_context *
1432 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1433 {
1434         struct fw_ohci *ohci = fw_ohci(card);
1435         struct iso_context *ctx, *list;
1436         descriptor_callback_t callback;
1437         u32 *mask, regs;
1438         unsigned long flags;
1439         int index, retval = -ENOMEM;
1440
1441         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1442                 mask = &ohci->it_context_mask;
1443                 list = ohci->it_context_list;
1444                 callback = handle_it_packet;
1445         } else {
1446                 mask = &ohci->ir_context_mask;
1447                 list = ohci->ir_context_list;
1448                 callback = handle_ir_dualbuffer_packet;
1449         }
1450
1451         /* FIXME: We need a fallback for pre 1.1 OHCI. */
1452         if (callback == handle_ir_dualbuffer_packet &&
1453             ohci->version < OHCI_VERSION_1_1)
1454                 return ERR_PTR(-EINVAL);
1455
1456         spin_lock_irqsave(&ohci->lock, flags);
1457         index = ffs(*mask) - 1;
1458         if (index >= 0)
1459                 *mask &= ~(1 << index);
1460         spin_unlock_irqrestore(&ohci->lock, flags);
1461
1462         if (index < 0)
1463                 return ERR_PTR(-EBUSY);
1464
1465         if (type == FW_ISO_CONTEXT_TRANSMIT)
1466                 regs = OHCI1394_IsoXmitContextBase(index);
1467         else
1468                 regs = OHCI1394_IsoRcvContextBase(index);
1469
1470         ctx = &list[index];
1471         memset(ctx, 0, sizeof(*ctx));
1472         ctx->header_length = 0;
1473         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1474         if (ctx->header == NULL)
1475                 goto out;
1476
1477         retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
1478                               regs, callback);
1479         if (retval < 0)
1480                 goto out_with_header;
1481
1482         return &ctx->base;
1483
1484  out_with_header:
1485         free_page((unsigned long)ctx->header);
1486  out:
1487         spin_lock_irqsave(&ohci->lock, flags);
1488         *mask |= 1 << index;
1489         spin_unlock_irqrestore(&ohci->lock, flags);
1490
1491         return ERR_PTR(retval);
1492 }
1493
1494 static int ohci_start_iso(struct fw_iso_context *base,
1495                           s32 cycle, u32 sync, u32 tags)
1496 {
1497         struct iso_context *ctx = container_of(base, struct iso_context, base);
1498         struct fw_ohci *ohci = ctx->context.ohci;
1499         u32 control, match;
1500         int index;
1501
1502         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1503                 index = ctx - ohci->it_context_list;
1504                 match = 0;
1505                 if (cycle >= 0)
1506                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1507                                 (cycle & 0x7fff) << 16;
1508
1509                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1510                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1511                 context_run(&ctx->context, match);
1512         } else {
1513                 index = ctx - ohci->ir_context_list;
1514                 control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
1515                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1516                 if (cycle >= 0) {
1517                         match |= (cycle & 0x07fff) << 12;
1518                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1519                 }
1520
1521                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1522                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1523                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1524                 context_run(&ctx->context, control);
1525         }
1526
1527         return 0;
1528 }
1529
1530 static int ohci_stop_iso(struct fw_iso_context *base)
1531 {
1532         struct fw_ohci *ohci = fw_ohci(base->card);
1533         struct iso_context *ctx = container_of(base, struct iso_context, base);
1534         int index;
1535
1536         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1537                 index = ctx - ohci->it_context_list;
1538                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1539         } else {
1540                 index = ctx - ohci->ir_context_list;
1541                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1542         }
1543         flush_writes(ohci);
1544         context_stop(&ctx->context);
1545
1546         return 0;
1547 }
1548
1549 static void ohci_free_iso_context(struct fw_iso_context *base)
1550 {
1551         struct fw_ohci *ohci = fw_ohci(base->card);
1552         struct iso_context *ctx = container_of(base, struct iso_context, base);
1553         unsigned long flags;
1554         int index;
1555
1556         ohci_stop_iso(base);
1557         context_release(&ctx->context);
1558         free_page((unsigned long)ctx->header);
1559
1560         spin_lock_irqsave(&ohci->lock, flags);
1561
1562         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1563                 index = ctx - ohci->it_context_list;
1564                 ohci->it_context_mask |= 1 << index;
1565         } else {
1566                 index = ctx - ohci->ir_context_list;
1567                 ohci->ir_context_mask |= 1 << index;
1568         }
1569
1570         spin_unlock_irqrestore(&ohci->lock, flags);
1571 }
1572
1573 static int
1574 ohci_queue_iso_transmit(struct fw_iso_context *base,
1575                         struct fw_iso_packet *packet,
1576                         struct fw_iso_buffer *buffer,
1577                         unsigned long payload)
1578 {
1579         struct iso_context *ctx = container_of(base, struct iso_context, base);
1580         struct descriptor *d, *last, *pd;
1581         struct fw_iso_packet *p;
1582         __le32 *header;
1583         dma_addr_t d_bus, page_bus;
1584         u32 z, header_z, payload_z, irq;
1585         u32 payload_index, payload_end_index, next_page_index;
1586         int page, end_page, i, length, offset;
1587
1588         /*
1589          * FIXME: Cycle lost behavior should be configurable: lose
1590          * packet, retransmit or terminate..
1591          */
1592
1593         p = packet;
1594         payload_index = payload;
1595
1596         if (p->skip)
1597                 z = 1;
1598         else
1599                 z = 2;
1600         if (p->header_length > 0)
1601                 z++;
1602
1603         /* Determine the first page the payload isn't contained in. */
1604         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1605         if (p->payload_length > 0)
1606                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1607         else
1608                 payload_z = 0;
1609
1610         z += payload_z;
1611
1612         /* Get header size in number of descriptors. */
1613         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1614
1615         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1616         if (d == NULL)
1617                 return -ENOMEM;
1618
1619         if (!p->skip) {
1620                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1621                 d[0].req_count = cpu_to_le16(8);
1622
1623                 header = (__le32 *) &d[1];
1624                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1625                                         IT_HEADER_TAG(p->tag) |
1626                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1627                                         IT_HEADER_CHANNEL(ctx->base.channel) |
1628                                         IT_HEADER_SPEED(ctx->base.speed));
1629                 header[1] =
1630                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
1631                                                           p->payload_length));
1632         }
1633
1634         if (p->header_length > 0) {
1635                 d[2].req_count    = cpu_to_le16(p->header_length);
1636                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
1637                 memcpy(&d[z], p->header, p->header_length);
1638         }
1639
1640         pd = d + z - payload_z;
1641         payload_end_index = payload_index + p->payload_length;
1642         for (i = 0; i < payload_z; i++) {
1643                 page               = payload_index >> PAGE_SHIFT;
1644                 offset             = payload_index & ~PAGE_MASK;
1645                 next_page_index    = (page + 1) << PAGE_SHIFT;
1646                 length             =
1647                         min(next_page_index, payload_end_index) - payload_index;
1648                 pd[i].req_count    = cpu_to_le16(length);
1649
1650                 page_bus = page_private(buffer->pages[page]);
1651                 pd[i].data_address = cpu_to_le32(page_bus + offset);
1652
1653                 payload_index += length;
1654         }
1655
1656         if (p->interrupt)
1657                 irq = DESCRIPTOR_IRQ_ALWAYS;
1658         else
1659                 irq = DESCRIPTOR_NO_IRQ;
1660
1661         last = z == 2 ? d : d + z - 1;
1662         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1663                                      DESCRIPTOR_STATUS |
1664                                      DESCRIPTOR_BRANCH_ALWAYS |
1665                                      irq);
1666
1667         context_append(&ctx->context, d, z, header_z);
1668
1669         return 0;
1670 }
1671
1672 static int
1673 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1674                                   struct fw_iso_packet *packet,
1675                                   struct fw_iso_buffer *buffer,
1676                                   unsigned long payload)
1677 {
1678         struct iso_context *ctx = container_of(base, struct iso_context, base);
1679         struct db_descriptor *db = NULL;
1680         struct descriptor *d;
1681         struct fw_iso_packet *p;
1682         dma_addr_t d_bus, page_bus;
1683         u32 z, header_z, length, rest;
1684         int page, offset, packet_count, header_size;
1685
1686         /*
1687          * FIXME: Cycle lost behavior should be configurable: lose
1688          * packet, retransmit or terminate..
1689          */
1690
1691         if (packet->skip) {
1692                 d = context_get_descriptors(&ctx->context, 2, &d_bus);
1693                 if (d == NULL)
1694                         return -ENOMEM;
1695
1696                 db = (struct db_descriptor *) d;
1697                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1698                                           DESCRIPTOR_BRANCH_ALWAYS |
1699                                           DESCRIPTOR_WAIT);
1700                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1701                 context_append(&ctx->context, d, 2, 0);
1702         }
1703
1704         p = packet;
1705         z = 2;
1706
1707         /*
1708          * The OHCI controller puts the status word in the header
1709          * buffer too, so we need 4 extra bytes per packet.
1710          */
1711         packet_count = p->header_length / ctx->base.header_size;
1712         header_size = packet_count * (ctx->base.header_size + 4);
1713
1714         /* Get header size in number of descriptors. */
1715         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1716         page     = payload >> PAGE_SHIFT;
1717         offset   = payload & ~PAGE_MASK;
1718         rest     = p->payload_length;
1719
1720         /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1721         /* FIXME: make packet-per-buffer/dual-buffer a context option */
1722         while (rest > 0) {
1723                 d = context_get_descriptors(&ctx->context,
1724                                             z + header_z, &d_bus);
1725                 if (d == NULL)
1726                         return -ENOMEM;
1727
1728                 db = (struct db_descriptor *) d;
1729                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1730                                           DESCRIPTOR_BRANCH_ALWAYS);
1731                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1732                 db->first_req_count = cpu_to_le16(header_size);
1733                 db->first_res_count = db->first_req_count;
1734                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
1735
1736                 if (offset + rest < PAGE_SIZE)
1737                         length = rest;
1738                 else
1739                         length = PAGE_SIZE - offset;
1740
1741                 db->second_req_count = cpu_to_le16(length);
1742                 db->second_res_count = db->second_req_count;
1743                 page_bus = page_private(buffer->pages[page]);
1744                 db->second_buffer = cpu_to_le32(page_bus + offset);
1745
1746                 if (p->interrupt && length == rest)
1747                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1748
1749                 context_append(&ctx->context, d, z, header_z);
1750                 offset = (offset + length) & ~PAGE_MASK;
1751                 rest -= length;
1752                 page++;
1753         }
1754
1755         return 0;
1756 }
1757
1758 static int
1759 ohci_queue_iso(struct fw_iso_context *base,
1760                struct fw_iso_packet *packet,
1761                struct fw_iso_buffer *buffer,
1762                unsigned long payload)
1763 {
1764         struct iso_context *ctx = container_of(base, struct iso_context, base);
1765
1766         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1767                 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1768         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
1769                 return ohci_queue_iso_receive_dualbuffer(base, packet,
1770                                                          buffer, payload);
1771         else
1772                 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1773                 return -EINVAL;
1774 }
1775
1776 static const struct fw_card_driver ohci_driver = {
1777         .name                   = ohci_driver_name,
1778         .enable                 = ohci_enable,
1779         .update_phy_reg         = ohci_update_phy_reg,
1780         .set_config_rom         = ohci_set_config_rom,
1781         .send_request           = ohci_send_request,
1782         .send_response          = ohci_send_response,
1783         .cancel_packet          = ohci_cancel_packet,
1784         .enable_phys_dma        = ohci_enable_phys_dma,
1785         .get_bus_time           = ohci_get_bus_time,
1786
1787         .allocate_iso_context   = ohci_allocate_iso_context,
1788         .free_iso_context       = ohci_free_iso_context,
1789         .queue_iso              = ohci_queue_iso,
1790         .start_iso              = ohci_start_iso,
1791         .stop_iso               = ohci_stop_iso,
1792 };
1793
1794 static int __devinit
1795 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1796 {
1797         struct fw_ohci *ohci;
1798         u32 bus_options, max_receive, link_speed;
1799         u64 guid;
1800         int err;
1801         size_t size;
1802
1803         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
1804         if (ohci == NULL) {
1805                 fw_error("Could not malloc fw_ohci data.\n");
1806                 return -ENOMEM;
1807         }
1808
1809         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1810
1811         err = pci_enable_device(dev);
1812         if (err) {
1813                 fw_error("Failed to enable OHCI hardware.\n");
1814                 goto fail_put_card;
1815         }
1816
1817         pci_set_master(dev);
1818         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1819         pci_set_drvdata(dev, ohci);
1820
1821         spin_lock_init(&ohci->lock);
1822
1823         tasklet_init(&ohci->bus_reset_tasklet,
1824                      bus_reset_tasklet, (unsigned long)ohci);
1825
1826         err = pci_request_region(dev, 0, ohci_driver_name);
1827         if (err) {
1828                 fw_error("MMIO resource unavailable\n");
1829                 goto fail_disable;
1830         }
1831
1832         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1833         if (ohci->registers == NULL) {
1834                 fw_error("Failed to remap registers\n");
1835                 err = -ENXIO;
1836                 goto fail_iomem;
1837         }
1838
1839         ar_context_init(&ohci->ar_request_ctx, ohci,
1840                         OHCI1394_AsReqRcvContextControlSet);
1841
1842         ar_context_init(&ohci->ar_response_ctx, ohci,
1843                         OHCI1394_AsRspRcvContextControlSet);
1844
1845         context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
1846                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
1847
1848         context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
1849                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
1850
1851         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1852         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1853         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1854         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1855         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1856
1857         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1858         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1859         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1860         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1861         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1862
1863         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1864                 fw_error("Out of memory for it/ir contexts.\n");
1865                 err = -ENOMEM;
1866                 goto fail_registers;
1867         }
1868
1869         /* self-id dma buffer allocation */
1870         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1871                                                SELF_ID_BUF_SIZE,
1872                                                &ohci->self_id_bus,
1873                                                GFP_KERNEL);
1874         if (ohci->self_id_cpu == NULL) {
1875                 fw_error("Out of memory for self ID buffer.\n");
1876                 err = -ENOMEM;
1877                 goto fail_registers;
1878         }
1879
1880         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1881         max_receive = (bus_options >> 12) & 0xf;
1882         link_speed = bus_options & 0x7;
1883         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1884                 reg_read(ohci, OHCI1394_GUIDLo);
1885
1886         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1887         if (err < 0)
1888                 goto fail_self_id;
1889
1890         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1891         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1892                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
1893
1894         return 0;
1895
1896  fail_self_id:
1897         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1898                           ohci->self_id_cpu, ohci->self_id_bus);
1899  fail_registers:
1900         kfree(ohci->it_context_list);
1901         kfree(ohci->ir_context_list);
1902         pci_iounmap(dev, ohci->registers);
1903  fail_iomem:
1904         pci_release_region(dev, 0);
1905  fail_disable:
1906         pci_disable_device(dev);
1907  fail_put_card:
1908         fw_card_put(&ohci->card);
1909
1910         return err;
1911 }
1912
1913 static void pci_remove(struct pci_dev *dev)
1914 {
1915         struct fw_ohci *ohci;
1916
1917         ohci = pci_get_drvdata(dev);
1918         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1919         flush_writes(ohci);
1920         fw_core_remove_card(&ohci->card);
1921
1922         /*
1923          * FIXME: Fail all pending packets here, now that the upper
1924          * layers can't queue any more.
1925          */
1926
1927         software_reset(ohci);
1928         free_irq(dev->irq, ohci);
1929         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1930                           ohci->self_id_cpu, ohci->self_id_bus);
1931         kfree(ohci->it_context_list);
1932         kfree(ohci->ir_context_list);
1933         pci_iounmap(dev, ohci->registers);
1934         pci_release_region(dev, 0);
1935         pci_disable_device(dev);
1936         fw_card_put(&ohci->card);
1937
1938         fw_notify("Removed fw-ohci device.\n");
1939 }
1940
1941 #ifdef CONFIG_PM
1942 static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
1943 {
1944         struct fw_ohci *ohci = pci_get_drvdata(pdev);
1945         int err;
1946
1947         software_reset(ohci);
1948         free_irq(pdev->irq, ohci);
1949         err = pci_save_state(pdev);
1950         if (err) {
1951                 fw_error("pci_save_state failed\n");
1952                 return err;
1953         }
1954         err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
1955         if (err)
1956                 fw_error("pci_set_power_state failed with %d\n", err);
1957
1958         return 0;
1959 }
1960
1961 static int pci_resume(struct pci_dev *pdev)
1962 {
1963         struct fw_ohci *ohci = pci_get_drvdata(pdev);
1964         int err;
1965
1966         pci_set_power_state(pdev, PCI_D0);
1967         pci_restore_state(pdev);
1968         err = pci_enable_device(pdev);
1969         if (err) {
1970                 fw_error("pci_enable_device failed\n");
1971                 return err;
1972         }
1973
1974         return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE);
1975 }
1976 #endif
1977
1978 static struct pci_device_id pci_table[] = {
1979         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1980         { }
1981 };
1982
1983 MODULE_DEVICE_TABLE(pci, pci_table);
1984
1985 static struct pci_driver fw_ohci_pci_driver = {
1986         .name           = ohci_driver_name,
1987         .id_table       = pci_table,
1988         .probe          = pci_probe,
1989         .remove         = pci_remove,
1990 #ifdef CONFIG_PM
1991         .resume         = pci_resume,
1992         .suspend        = pci_suspend,
1993 #endif
1994 };
1995
1996 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1997 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1998 MODULE_LICENSE("GPL");
1999
2000 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2001 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2002 MODULE_ALIAS("ohci1394");
2003 #endif
2004
2005 static int __init fw_ohci_init(void)
2006 {
2007         return pci_register_driver(&fw_ohci_pci_driver);
2008 }
2009
2010 static void __exit fw_ohci_cleanup(void)
2011 {
2012         pci_unregister_driver(&fw_ohci_pci_driver);
2013 }
2014
2015 module_init(fw_ohci_init);
2016 module_exit(fw_ohci_cleanup);