1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver;
57 static unsigned int i915_load_fail_count;
59 bool __i915_inject_load_failure(const char *func, int line)
61 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
64 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915_modparams.inject_load_failure, func, line);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
81 static bool shown_bug_once;
82 struct device *kdev = dev_priv->drm.dev;
83 bool is_error = level[1] <= KERN_ERR[1];
84 bool is_debug = level[1] == KERN_DEBUG[1];
88 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
96 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
97 __builtin_return_address(0), &vaf);
99 if (is_error && !shown_bug_once) {
100 dev_notice(kdev, "%s", FDO_BUG_MSG);
101 shown_bug_once = true;
107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
109 return i915_modparams.inject_load_failure &&
110 i915_load_fail_count == i915_modparams.inject_load_failure;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
121 enum intel_pch ret = PCH_NOP;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
138 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
139 dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
141 dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
143 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146 } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
154 static void intel_detect_pch(struct drm_i915_private *dev_priv)
156 struct pci_dev *pch = NULL;
158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
161 if (INTEL_INFO(dev_priv)->num_pipes == 0) {
162 dev_priv->pch_type = PCH_NOP;
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
177 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
178 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
179 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
181 dev_priv->pch_id = id;
183 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
184 dev_priv->pch_type = PCH_IBX;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
186 WARN_ON(!IS_GEN5(dev_priv));
187 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
188 dev_priv->pch_type = PCH_CPT;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
190 WARN_ON(!IS_GEN6(dev_priv) &&
191 !IS_IVYBRIDGE(dev_priv));
192 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
193 /* PantherPoint is CPT compatible */
194 dev_priv->pch_type = PCH_CPT;
195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
196 WARN_ON(!IS_GEN6(dev_priv) &&
197 !IS_IVYBRIDGE(dev_priv));
198 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
199 dev_priv->pch_type = PCH_LPT;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201 WARN_ON(!IS_HASWELL(dev_priv) &&
202 !IS_BROADWELL(dev_priv));
203 WARN_ON(IS_HSW_ULT(dev_priv) ||
204 IS_BDW_ULT(dev_priv));
205 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
206 dev_priv->pch_type = PCH_LPT;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
208 WARN_ON(!IS_HASWELL(dev_priv) &&
209 !IS_BROADWELL(dev_priv));
210 WARN_ON(!IS_HSW_ULT(dev_priv) &&
211 !IS_BDW_ULT(dev_priv));
212 } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv->pch_type = PCH_LPT;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv) &&
217 !IS_BROADWELL(dev_priv));
218 WARN_ON(IS_HSW_ULT(dev_priv) ||
219 IS_BDW_ULT(dev_priv));
220 } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv->pch_type = PCH_LPT;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv) &&
225 !IS_BROADWELL(dev_priv));
226 WARN_ON(!IS_HSW_ULT(dev_priv) &&
227 !IS_BDW_ULT(dev_priv));
228 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
229 dev_priv->pch_type = PCH_SPT;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
231 WARN_ON(!IS_SKYLAKE(dev_priv) &&
232 !IS_KABYLAKE(dev_priv));
233 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
234 dev_priv->pch_type = PCH_SPT;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
236 WARN_ON(!IS_SKYLAKE(dev_priv) &&
237 !IS_KABYLAKE(dev_priv));
238 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
239 dev_priv->pch_type = PCH_KBP;
240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
241 WARN_ON(!IS_SKYLAKE(dev_priv) &&
242 !IS_KABYLAKE(dev_priv) &&
243 !IS_COFFEELAKE(dev_priv));
244 } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
245 dev_priv->pch_type = PCH_CNP;
246 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
247 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
248 !IS_COFFEELAKE(dev_priv));
249 } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
250 dev_priv->pch_type = PCH_CNP;
251 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
252 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
253 !IS_COFFEELAKE(dev_priv));
254 } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
255 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
256 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
257 pch->subsystem_vendor ==
258 PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
259 pch->subsystem_device ==
260 PCI_SUBDEVICE_ID_QEMU)) {
262 intel_virt_detect_pch(dev_priv);
270 DRM_DEBUG_KMS("No PCH found.\n");
275 static int i915_getparam(struct drm_device *dev, void *data,
276 struct drm_file *file_priv)
278 struct drm_i915_private *dev_priv = to_i915(dev);
279 struct pci_dev *pdev = dev_priv->drm.pdev;
280 drm_i915_getparam_t *param = data;
283 switch (param->param) {
284 case I915_PARAM_IRQ_ACTIVE:
285 case I915_PARAM_ALLOW_BATCHBUFFER:
286 case I915_PARAM_LAST_DISPATCH:
287 case I915_PARAM_HAS_EXEC_CONSTANTS:
288 /* Reject all old ums/dri params. */
290 case I915_PARAM_CHIPSET_ID:
291 value = pdev->device;
293 case I915_PARAM_REVISION:
294 value = pdev->revision;
296 case I915_PARAM_NUM_FENCES_AVAIL:
297 value = dev_priv->num_fence_regs;
299 case I915_PARAM_HAS_OVERLAY:
300 value = dev_priv->overlay ? 1 : 0;
302 case I915_PARAM_HAS_BSD:
303 value = !!dev_priv->engine[VCS];
305 case I915_PARAM_HAS_BLT:
306 value = !!dev_priv->engine[BCS];
308 case I915_PARAM_HAS_VEBOX:
309 value = !!dev_priv->engine[VECS];
311 case I915_PARAM_HAS_BSD2:
312 value = !!dev_priv->engine[VCS2];
314 case I915_PARAM_HAS_LLC:
315 value = HAS_LLC(dev_priv);
317 case I915_PARAM_HAS_WT:
318 value = HAS_WT(dev_priv);
320 case I915_PARAM_HAS_ALIASING_PPGTT:
321 value = USES_PPGTT(dev_priv);
323 case I915_PARAM_HAS_SEMAPHORES:
324 value = i915_modparams.semaphores;
326 case I915_PARAM_HAS_SECURE_BATCHES:
327 value = capable(CAP_SYS_ADMIN);
329 case I915_PARAM_CMD_PARSER_VERSION:
330 value = i915_cmd_parser_get_version(dev_priv);
332 case I915_PARAM_SUBSLICE_TOTAL:
333 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
337 case I915_PARAM_EU_TOTAL:
338 value = INTEL_INFO(dev_priv)->sseu.eu_total;
342 case I915_PARAM_HAS_GPU_RESET:
343 value = i915_modparams.enable_hangcheck &&
344 intel_has_gpu_reset(dev_priv);
345 if (value && intel_has_reset_engine(dev_priv))
348 case I915_PARAM_HAS_RESOURCE_STREAMER:
349 value = HAS_RESOURCE_STREAMER(dev_priv);
351 case I915_PARAM_HAS_POOLED_EU:
352 value = HAS_POOLED_EU(dev_priv);
354 case I915_PARAM_MIN_EU_IN_POOL:
355 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
357 case I915_PARAM_HUC_STATUS:
358 intel_runtime_pm_get(dev_priv);
359 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
360 intel_runtime_pm_put(dev_priv);
362 case I915_PARAM_MMAP_GTT_VERSION:
363 /* Though we've started our numbering from 1, and so class all
364 * earlier versions as 0, in effect their value is undefined as
365 * the ioctl will report EINVAL for the unknown param!
367 value = i915_gem_mmap_gtt_version();
369 case I915_PARAM_HAS_SCHEDULER:
370 value = dev_priv->engine[RCS] &&
371 dev_priv->engine[RCS]->schedule;
373 case I915_PARAM_MMAP_VERSION:
374 /* Remember to bump this if the version changes! */
375 case I915_PARAM_HAS_GEM:
376 case I915_PARAM_HAS_PAGEFLIPPING:
377 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
378 case I915_PARAM_HAS_RELAXED_FENCING:
379 case I915_PARAM_HAS_COHERENT_RINGS:
380 case I915_PARAM_HAS_RELAXED_DELTA:
381 case I915_PARAM_HAS_GEN7_SOL_RESET:
382 case I915_PARAM_HAS_WAIT_TIMEOUT:
383 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
384 case I915_PARAM_HAS_PINNED_BATCHES:
385 case I915_PARAM_HAS_EXEC_NO_RELOC:
386 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
387 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
388 case I915_PARAM_HAS_EXEC_SOFTPIN:
389 case I915_PARAM_HAS_EXEC_ASYNC:
390 case I915_PARAM_HAS_EXEC_FENCE:
391 case I915_PARAM_HAS_EXEC_CAPTURE:
392 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
393 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
394 /* For the time being all of these are always true;
395 * if some supported hardware does not have one of these
396 * features this value needs to be provided from
397 * INTEL_INFO(), a feature macro, or similar.
401 case I915_PARAM_SLICE_MASK:
402 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
406 case I915_PARAM_SUBSLICE_MASK:
407 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
412 DRM_DEBUG("Unknown parameter %d\n", param->param);
416 if (put_user(value, param->value))
422 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
424 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
425 if (!dev_priv->bridge_dev) {
426 DRM_ERROR("bridge device not found\n");
432 /* Allocate space for the MCH regs if needed, return nonzero on error */
434 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
436 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
437 u32 temp_lo, temp_hi = 0;
441 if (INTEL_GEN(dev_priv) >= 4)
442 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
443 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
444 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
446 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
449 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
453 /* Get some space for it */
454 dev_priv->mch_res.name = "i915 MCHBAR";
455 dev_priv->mch_res.flags = IORESOURCE_MEM;
456 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
458 MCHBAR_SIZE, MCHBAR_SIZE,
460 0, pcibios_align_resource,
461 dev_priv->bridge_dev);
463 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
464 dev_priv->mch_res.start = 0;
468 if (INTEL_GEN(dev_priv) >= 4)
469 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
470 upper_32_bits(dev_priv->mch_res.start));
472 pci_write_config_dword(dev_priv->bridge_dev, reg,
473 lower_32_bits(dev_priv->mch_res.start));
477 /* Setup MCHBAR if possible, return true if we should disable it again */
479 intel_setup_mchbar(struct drm_i915_private *dev_priv)
481 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
485 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
488 dev_priv->mchbar_need_disable = false;
490 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
491 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
492 enabled = !!(temp & DEVEN_MCHBAR_EN);
494 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
498 /* If it's already enabled, don't have to do anything */
502 if (intel_alloc_mchbar_resource(dev_priv))
505 dev_priv->mchbar_need_disable = true;
507 /* Space is allocated or reserved, so enable it. */
508 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
509 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
510 temp | DEVEN_MCHBAR_EN);
512 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
513 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
518 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
520 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
522 if (dev_priv->mchbar_need_disable) {
523 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
526 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
528 deven_val &= ~DEVEN_MCHBAR_EN;
529 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
534 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
537 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
542 if (dev_priv->mch_res.start)
543 release_resource(&dev_priv->mch_res);
546 /* true = enable decode, false = disable decoder */
547 static unsigned int i915_vga_set_decode(void *cookie, bool state)
549 struct drm_i915_private *dev_priv = cookie;
551 intel_modeset_vga_set_state(dev_priv, state);
553 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
554 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
556 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
559 static int i915_resume_switcheroo(struct drm_device *dev);
560 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
562 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
564 struct drm_device *dev = pci_get_drvdata(pdev);
565 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
567 if (state == VGA_SWITCHEROO_ON) {
568 pr_info("switched on\n");
569 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
570 /* i915 resume handler doesn't set to D0 */
571 pci_set_power_state(pdev, PCI_D0);
572 i915_resume_switcheroo(dev);
573 dev->switch_power_state = DRM_SWITCH_POWER_ON;
575 pr_info("switched off\n");
576 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
577 i915_suspend_switcheroo(dev, pmm);
578 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
582 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
584 struct drm_device *dev = pci_get_drvdata(pdev);
587 * FIXME: open_count is protected by drm_global_mutex but that would lead to
588 * locking inversion with the driver load path. And the access here is
589 * completely racy anyway. So don't bother with locking for now.
591 return dev->open_count == 0;
594 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
595 .set_gpu_state = i915_switcheroo_set_state,
597 .can_switch = i915_switcheroo_can_switch,
600 static void i915_gem_fini(struct drm_i915_private *dev_priv)
602 /* Flush any outstanding unpin_work. */
603 i915_gem_drain_workqueue(dev_priv);
605 mutex_lock(&dev_priv->drm.struct_mutex);
606 intel_uc_fini_hw(dev_priv);
607 i915_gem_cleanup_engines(dev_priv);
608 i915_gem_contexts_fini(dev_priv);
609 i915_gem_cleanup_userptr(dev_priv);
610 mutex_unlock(&dev_priv->drm.struct_mutex);
612 i915_gem_drain_freed_objects(dev_priv);
614 WARN_ON(!list_empty(&dev_priv->contexts.list));
617 static int i915_load_modeset_init(struct drm_device *dev)
619 struct drm_i915_private *dev_priv = to_i915(dev);
620 struct pci_dev *pdev = dev_priv->drm.pdev;
623 if (i915_inject_load_failure())
626 intel_bios_init(dev_priv);
628 /* If we have > 1 VGA cards, then we need to arbitrate access
629 * to the common VGA resources.
631 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
632 * then we do not take part in VGA arbitration and the
633 * vga_client_register() fails with -ENODEV.
635 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
636 if (ret && ret != -ENODEV)
639 intel_register_dsm_handler();
641 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
643 goto cleanup_vga_client;
645 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
646 intel_update_rawclk(dev_priv);
648 intel_power_domains_init_hw(dev_priv, false);
650 intel_csr_ucode_init(dev_priv);
652 ret = intel_irq_install(dev_priv);
656 intel_setup_gmbus(dev_priv);
658 /* Important: The output setup functions called by modeset_init need
659 * working irqs for e.g. gmbus and dp aux transfers. */
660 ret = intel_modeset_init(dev);
664 intel_uc_init_fw(dev_priv);
666 ret = i915_gem_init(dev_priv);
670 intel_modeset_gem_init(dev);
672 if (INTEL_INFO(dev_priv)->num_pipes == 0)
675 ret = intel_fbdev_init(dev);
679 /* Only enable hotplug handling once the fbdev is fully set up. */
680 intel_hpd_init(dev_priv);
682 drm_kms_helper_poll_init(dev);
687 if (i915_gem_suspend(dev_priv))
688 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
689 i915_gem_fini(dev_priv);
691 intel_uc_fini_fw(dev_priv);
693 drm_irq_uninstall(dev);
694 intel_teardown_gmbus(dev_priv);
696 intel_csr_ucode_fini(dev_priv);
697 intel_power_domains_fini(dev_priv);
698 vga_switcheroo_unregister_client(pdev);
700 vga_client_register(pdev, NULL, NULL, NULL);
705 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
707 struct apertures_struct *ap;
708 struct pci_dev *pdev = dev_priv->drm.pdev;
709 struct i915_ggtt *ggtt = &dev_priv->ggtt;
713 ap = alloc_apertures(1);
717 ap->ranges[0].base = ggtt->mappable_base;
718 ap->ranges[0].size = ggtt->mappable_end;
721 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
723 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
730 #if !defined(CONFIG_VGA_CONSOLE)
731 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
735 #elif !defined(CONFIG_DUMMY_CONSOLE)
736 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
741 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
745 DRM_INFO("Replacing VGA console driver\n");
748 if (con_is_bound(&vga_con))
749 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
751 ret = do_unregister_con_driver(&vga_con);
753 /* Ignore "already unregistered". */
763 static void intel_init_dpio(struct drm_i915_private *dev_priv)
766 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
767 * CHV x1 PHY (DP/HDMI D)
768 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
770 if (IS_CHERRYVIEW(dev_priv)) {
771 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
772 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
773 } else if (IS_VALLEYVIEW(dev_priv)) {
774 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
778 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
781 * The i915 workqueue is primarily used for batched retirement of
782 * requests (and thus managing bo) once the task has been completed
783 * by the GPU. i915_gem_retire_requests() is called directly when we
784 * need high-priority retirement, such as waiting for an explicit
787 * It is also used for periodic low-priority events, such as
788 * idle-timers and recording error state.
790 * All tasks on the workqueue are expected to acquire the dev mutex
791 * so there is no point in running more than one instance of the
792 * workqueue at any time. Use an ordered one.
794 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
795 if (dev_priv->wq == NULL)
798 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
799 if (dev_priv->hotplug.dp_wq == NULL)
805 destroy_workqueue(dev_priv->wq);
807 DRM_ERROR("Failed to allocate workqueues.\n");
812 static void i915_engines_cleanup(struct drm_i915_private *i915)
814 struct intel_engine_cs *engine;
815 enum intel_engine_id id;
817 for_each_engine(engine, i915, id)
821 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
823 destroy_workqueue(dev_priv->hotplug.dp_wq);
824 destroy_workqueue(dev_priv->wq);
828 * We don't keep the workarounds for pre-production hardware, so we expect our
829 * driver to fail on these machines in one way or another. A little warning on
830 * dmesg may help both the user and the bug triagers.
832 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
836 pre |= IS_HSW_EARLY_SDV(dev_priv);
837 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
838 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
841 DRM_ERROR("This is a pre-production stepping. "
842 "It may not be fully functional.\n");
843 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
848 * i915_driver_init_early - setup state not requiring device access
849 * @dev_priv: device private
851 * Initialize everything that is a "SW-only" state, that is state not
852 * requiring accessing the device or exposing the driver via kernel internal
853 * or userspace interfaces. Example steps belonging here: lock initialization,
854 * system memory allocation, setting up device specific attributes and
855 * function hooks not requiring accessing the device.
857 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
858 const struct pci_device_id *ent)
860 const struct intel_device_info *match_info =
861 (struct intel_device_info *)ent->driver_data;
862 struct intel_device_info *device_info;
865 if (i915_inject_load_failure())
868 /* Setup the write-once "constant" device info */
869 device_info = mkwrite_device_info(dev_priv);
870 memcpy(device_info, match_info, sizeof(*device_info));
871 device_info->device_id = dev_priv->drm.pdev->device;
873 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
874 sizeof(device_info->platform_mask) * BITS_PER_BYTE);
875 device_info->platform_mask = BIT(device_info->platform);
877 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
878 device_info->gen_mask = BIT(device_info->gen - 1);
880 spin_lock_init(&dev_priv->irq_lock);
881 spin_lock_init(&dev_priv->gpu_error.lock);
882 mutex_init(&dev_priv->backlight_lock);
883 spin_lock_init(&dev_priv->uncore.lock);
885 spin_lock_init(&dev_priv->mm.object_stat_lock);
886 mutex_init(&dev_priv->sb_lock);
887 mutex_init(&dev_priv->modeset_restore_lock);
888 mutex_init(&dev_priv->av_mutex);
889 mutex_init(&dev_priv->wm.wm_mutex);
890 mutex_init(&dev_priv->pps_mutex);
892 intel_uc_init_early(dev_priv);
893 i915_memcpy_init_early(dev_priv);
895 ret = i915_workqueues_init(dev_priv);
899 /* This must be called before any calls to HAS_PCH_* */
900 intel_detect_pch(dev_priv);
902 intel_pm_setup(dev_priv);
903 intel_init_dpio(dev_priv);
904 intel_power_domains_init(dev_priv);
905 intel_irq_init(dev_priv);
906 intel_hangcheck_init(dev_priv);
907 intel_init_display_hooks(dev_priv);
908 intel_init_clock_gating_hooks(dev_priv);
909 intel_init_audio_hooks(dev_priv);
910 ret = i915_gem_load_init(dev_priv);
914 intel_display_crc_init(dev_priv);
916 intel_device_info_dump(dev_priv);
918 intel_detect_preproduction_hw(dev_priv);
920 i915_perf_init(dev_priv);
925 intel_irq_fini(dev_priv);
926 i915_workqueues_cleanup(dev_priv);
928 i915_engines_cleanup(dev_priv);
933 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
934 * @dev_priv: device private
936 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
938 i915_perf_fini(dev_priv);
939 i915_gem_load_cleanup(dev_priv);
940 intel_irq_fini(dev_priv);
941 i915_workqueues_cleanup(dev_priv);
942 i915_engines_cleanup(dev_priv);
945 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
947 struct pci_dev *pdev = dev_priv->drm.pdev;
951 mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
953 * Before gen4, the registers and the GTT are behind different BARs.
954 * However, from gen4 onwards, the registers and the GTT are shared
955 * in the same BAR, so we want to restrict this ioremap from
956 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
957 * the register BAR remains the same size for all the earlier
958 * generations up to Ironlake.
960 if (INTEL_GEN(dev_priv) < 5)
961 mmio_size = 512 * 1024;
963 mmio_size = 2 * 1024 * 1024;
964 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
965 if (dev_priv->regs == NULL) {
966 DRM_ERROR("failed to map registers\n");
971 /* Try to make sure MCHBAR is enabled before poking at it */
972 intel_setup_mchbar(dev_priv);
977 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
979 struct pci_dev *pdev = dev_priv->drm.pdev;
981 intel_teardown_mchbar(dev_priv);
982 pci_iounmap(pdev, dev_priv->regs);
986 * i915_driver_init_mmio - setup device MMIO
987 * @dev_priv: device private
989 * Setup minimal device state necessary for MMIO accesses later in the
990 * initialization sequence. The setup here should avoid any other device-wide
991 * side effects or exposing the driver via kernel internal or user space
994 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
998 if (i915_inject_load_failure())
1001 if (i915_get_bridge_dev(dev_priv))
1004 ret = i915_mmio_setup(dev_priv);
1008 intel_uncore_init(dev_priv);
1010 ret = intel_engines_init_mmio(dev_priv);
1014 i915_gem_init_mmio(dev_priv);
1019 intel_uncore_fini(dev_priv);
1021 pci_dev_put(dev_priv->bridge_dev);
1027 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1028 * @dev_priv: device private
1030 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1032 intel_uncore_fini(dev_priv);
1033 i915_mmio_cleanup(dev_priv);
1034 pci_dev_put(dev_priv->bridge_dev);
1037 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1039 i915_modparams.enable_execlists =
1040 intel_sanitize_enable_execlists(dev_priv,
1041 i915_modparams.enable_execlists);
1044 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1045 * user's requested state against the hardware/driver capabilities. We
1046 * do this now so that we can print out any log messages once rather
1047 * than every time we check intel_enable_ppgtt().
1049 i915_modparams.enable_ppgtt =
1050 intel_sanitize_enable_ppgtt(dev_priv,
1051 i915_modparams.enable_ppgtt);
1052 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1054 i915_modparams.semaphores =
1055 intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
1056 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1057 yesno(i915_modparams.semaphores));
1059 intel_uc_sanitize_options(dev_priv);
1061 intel_gvt_sanitize_options(dev_priv);
1065 * i915_driver_init_hw - setup state requiring device access
1066 * @dev_priv: device private
1068 * Setup state that requires accessing the device, but doesn't require
1069 * exposing the driver via kernel internal or userspace interfaces.
1071 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1073 struct pci_dev *pdev = dev_priv->drm.pdev;
1076 if (i915_inject_load_failure())
1079 intel_device_info_runtime_init(dev_priv);
1081 intel_sanitize_options(dev_priv);
1083 ret = i915_ggtt_probe_hw(dev_priv);
1087 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1088 * otherwise the vga fbdev driver falls over. */
1089 ret = i915_kick_out_firmware_fb(dev_priv);
1091 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1095 ret = i915_kick_out_vgacon(dev_priv);
1097 DRM_ERROR("failed to remove conflicting VGA console\n");
1101 ret = i915_ggtt_init_hw(dev_priv);
1105 ret = i915_ggtt_enable_hw(dev_priv);
1107 DRM_ERROR("failed to enable GGTT\n");
1111 pci_set_master(pdev);
1113 /* overlay on gen2 is broken and can't address above 1G */
1114 if (IS_GEN2(dev_priv)) {
1115 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1117 DRM_ERROR("failed to set DMA mask\n");
1123 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1124 * using 32bit addressing, overwriting memory if HWS is located
1127 * The documentation also mentions an issue with undefined
1128 * behaviour if any general state is accessed within a page above 4GB,
1129 * which also needs to be handled carefully.
1131 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1132 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1135 DRM_ERROR("failed to set DMA mask\n");
1141 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1142 PM_QOS_DEFAULT_VALUE);
1144 intel_uncore_sanitize(dev_priv);
1146 intel_opregion_setup(dev_priv);
1148 i915_gem_load_init_fences(dev_priv);
1150 /* On the 945G/GM, the chipset reports the MSI capability on the
1151 * integrated graphics even though the support isn't actually there
1152 * according to the published specs. It doesn't appear to function
1153 * correctly in testing on 945G.
1154 * This may be a side effect of MSI having been made available for PEG
1155 * and the registers being closely associated.
1157 * According to chipset errata, on the 965GM, MSI interrupts may
1158 * be lost or delayed, and was defeatured. MSI interrupts seem to
1159 * get lost on g4x as well, and interrupt delivery seems to stay
1160 * properly dead afterwards. So we'll just disable them for all
1161 * pre-gen5 chipsets.
1163 if (INTEL_GEN(dev_priv) >= 5) {
1164 if (pci_enable_msi(pdev) < 0)
1165 DRM_DEBUG_DRIVER("can't enable MSI");
1168 ret = intel_gvt_init(dev_priv);
1175 i915_ggtt_cleanup_hw(dev_priv);
1181 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1182 * @dev_priv: device private
1184 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1186 struct pci_dev *pdev = dev_priv->drm.pdev;
1188 if (pdev->msi_enabled)
1189 pci_disable_msi(pdev);
1191 pm_qos_remove_request(&dev_priv->pm_qos);
1192 i915_ggtt_cleanup_hw(dev_priv);
1196 * i915_driver_register - register the driver with the rest of the system
1197 * @dev_priv: device private
1199 * Perform any steps necessary to make the driver available via kernel
1200 * internal or userspace interfaces.
1202 static void i915_driver_register(struct drm_i915_private *dev_priv)
1204 struct drm_device *dev = &dev_priv->drm;
1206 i915_gem_shrinker_init(dev_priv);
1209 * Notify a valid surface after modesetting,
1210 * when running inside a VM.
1212 if (intel_vgpu_active(dev_priv))
1213 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1215 /* Reveal our presence to userspace */
1216 if (drm_dev_register(dev, 0) == 0) {
1217 i915_debugfs_register(dev_priv);
1218 i915_guc_log_register(dev_priv);
1219 i915_setup_sysfs(dev_priv);
1221 /* Depends on sysfs having been initialized */
1222 i915_perf_register(dev_priv);
1224 DRM_ERROR("Failed to register driver for userspace access!\n");
1226 if (INTEL_INFO(dev_priv)->num_pipes) {
1227 /* Must be done after probing outputs */
1228 intel_opregion_register(dev_priv);
1229 acpi_video_register();
1232 if (IS_GEN5(dev_priv))
1233 intel_gpu_ips_init(dev_priv);
1235 intel_audio_init(dev_priv);
1238 * Some ports require correctly set-up hpd registers for detection to
1239 * work properly (leading to ghost connected connector status), e.g. VGA
1240 * on gm45. Hence we can only set up the initial fbdev config after hpd
1241 * irqs are fully enabled. We do it last so that the async config
1242 * cannot run before the connectors are registered.
1244 intel_fbdev_initial_config_async(dev);
1248 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1249 * @dev_priv: device private
1251 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1253 intel_fbdev_unregister(dev_priv);
1254 intel_audio_deinit(dev_priv);
1256 intel_gpu_ips_teardown();
1257 acpi_video_unregister();
1258 intel_opregion_unregister(dev_priv);
1260 i915_perf_unregister(dev_priv);
1262 i915_teardown_sysfs(dev_priv);
1263 i915_guc_log_unregister(dev_priv);
1264 drm_dev_unregister(&dev_priv->drm);
1266 i915_gem_shrinker_cleanup(dev_priv);
1270 * i915_driver_load - setup chip and create an initial config
1272 * @ent: matching PCI ID entry
1274 * The driver load routine has to do several things:
1275 * - drive output discovery via intel_modeset_init()
1276 * - initialize the memory manager
1277 * - allocate initial config memory
1278 * - setup the DRM framebuffer with the allocated memory
1280 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1282 const struct intel_device_info *match_info =
1283 (struct intel_device_info *)ent->driver_data;
1284 struct drm_i915_private *dev_priv;
1287 /* Enable nuclear pageflip on ILK+ */
1288 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1289 driver.driver_features &= ~DRIVER_ATOMIC;
1292 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1294 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1296 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1300 dev_priv->drm.pdev = pdev;
1301 dev_priv->drm.dev_private = dev_priv;
1303 ret = pci_enable_device(pdev);
1307 pci_set_drvdata(pdev, &dev_priv->drm);
1309 * Disable the system suspend direct complete optimization, which can
1310 * leave the device suspended skipping the driver's suspend handlers
1311 * if the device was already runtime suspended. This is needed due to
1312 * the difference in our runtime and system suspend sequence and
1313 * becaue the HDA driver may require us to enable the audio power
1314 * domain during system suspend.
1316 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1318 ret = i915_driver_init_early(dev_priv, ent);
1320 goto out_pci_disable;
1322 intel_runtime_pm_get(dev_priv);
1324 ret = i915_driver_init_mmio(dev_priv);
1326 goto out_runtime_pm_put;
1328 ret = i915_driver_init_hw(dev_priv);
1330 goto out_cleanup_mmio;
1333 * TODO: move the vblank init and parts of modeset init steps into one
1334 * of the i915_driver_init_/i915_driver_register functions according
1335 * to the role/effect of the given init step.
1337 if (INTEL_INFO(dev_priv)->num_pipes) {
1338 ret = drm_vblank_init(&dev_priv->drm,
1339 INTEL_INFO(dev_priv)->num_pipes);
1341 goto out_cleanup_hw;
1344 ret = i915_load_modeset_init(&dev_priv->drm);
1346 goto out_cleanup_hw;
1348 i915_driver_register(dev_priv);
1350 intel_runtime_pm_enable(dev_priv);
1352 intel_init_ipc(dev_priv);
1354 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1355 DRM_INFO("DRM_I915_DEBUG enabled\n");
1356 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1357 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1359 intel_runtime_pm_put(dev_priv);
1364 i915_driver_cleanup_hw(dev_priv);
1366 i915_driver_cleanup_mmio(dev_priv);
1368 intel_runtime_pm_put(dev_priv);
1369 i915_driver_cleanup_early(dev_priv);
1371 pci_disable_device(pdev);
1373 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1374 drm_dev_fini(&dev_priv->drm);
1380 void i915_driver_unload(struct drm_device *dev)
1382 struct drm_i915_private *dev_priv = to_i915(dev);
1383 struct pci_dev *pdev = dev_priv->drm.pdev;
1385 i915_driver_unregister(dev_priv);
1387 if (i915_gem_suspend(dev_priv))
1388 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1390 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1392 drm_atomic_helper_shutdown(dev);
1394 intel_gvt_cleanup(dev_priv);
1396 intel_modeset_cleanup(dev);
1399 * free the memory space allocated for the child device
1400 * config parsed from VBT
1402 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1403 kfree(dev_priv->vbt.child_dev);
1404 dev_priv->vbt.child_dev = NULL;
1405 dev_priv->vbt.child_dev_num = 0;
1407 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1408 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1409 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1410 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1412 vga_switcheroo_unregister_client(pdev);
1413 vga_client_register(pdev, NULL, NULL, NULL);
1415 intel_csr_ucode_fini(dev_priv);
1417 /* Free error state after interrupts are fully disabled. */
1418 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1419 i915_reset_error_state(dev_priv);
1421 i915_gem_fini(dev_priv);
1422 intel_uc_fini_fw(dev_priv);
1423 intel_fbc_cleanup_cfb(dev_priv);
1425 intel_power_domains_fini(dev_priv);
1427 i915_driver_cleanup_hw(dev_priv);
1428 i915_driver_cleanup_mmio(dev_priv);
1430 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1433 static void i915_driver_release(struct drm_device *dev)
1435 struct drm_i915_private *dev_priv = to_i915(dev);
1437 i915_driver_cleanup_early(dev_priv);
1438 drm_dev_fini(&dev_priv->drm);
1443 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1445 struct drm_i915_private *i915 = to_i915(dev);
1448 ret = i915_gem_open(i915, file);
1456 * i915_driver_lastclose - clean up after all DRM clients have exited
1459 * Take care of cleaning up after all DRM clients have exited. In the
1460 * mode setting case, we want to restore the kernel's initial mode (just
1461 * in case the last client left us in a bad state).
1463 * Additionally, in the non-mode setting case, we'll tear down the GTT
1464 * and DMA structures, since the kernel won't be using them, and clea
1467 static void i915_driver_lastclose(struct drm_device *dev)
1469 intel_fbdev_restore_mode(dev);
1470 vga_switcheroo_process_delayed_switch();
1473 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1475 struct drm_i915_file_private *file_priv = file->driver_priv;
1477 mutex_lock(&dev->struct_mutex);
1478 i915_gem_context_close(file);
1479 i915_gem_release(dev, file);
1480 mutex_unlock(&dev->struct_mutex);
1485 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1487 struct drm_device *dev = &dev_priv->drm;
1488 struct intel_encoder *encoder;
1490 drm_modeset_lock_all(dev);
1491 for_each_intel_encoder(dev, encoder)
1492 if (encoder->suspend)
1493 encoder->suspend(encoder);
1494 drm_modeset_unlock_all(dev);
1497 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1499 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1501 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1503 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1504 if (acpi_target_system_state() < ACPI_STATE_S3)
1510 static int i915_drm_suspend(struct drm_device *dev)
1512 struct drm_i915_private *dev_priv = to_i915(dev);
1513 struct pci_dev *pdev = dev_priv->drm.pdev;
1514 pci_power_t opregion_target_state;
1517 /* ignore lid events during suspend */
1518 mutex_lock(&dev_priv->modeset_restore_lock);
1519 dev_priv->modeset_restore = MODESET_SUSPENDED;
1520 mutex_unlock(&dev_priv->modeset_restore_lock);
1522 disable_rpm_wakeref_asserts(dev_priv);
1524 /* We do a lot of poking in a lot of registers, make sure they work
1526 intel_display_set_init_power(dev_priv, true);
1528 drm_kms_helper_poll_disable(dev);
1530 pci_save_state(pdev);
1532 error = i915_gem_suspend(dev_priv);
1535 "GEM idle failed, resume might fail\n");
1539 intel_display_suspend(dev);
1541 intel_dp_mst_suspend(dev);
1543 intel_runtime_pm_disable_interrupts(dev_priv);
1544 intel_hpd_cancel_work(dev_priv);
1546 intel_suspend_encoders(dev_priv);
1548 intel_suspend_hw(dev_priv);
1550 i915_gem_suspend_gtt_mappings(dev_priv);
1552 i915_save_state(dev_priv);
1554 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1555 intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1557 intel_uncore_suspend(dev_priv);
1558 intel_opregion_unregister(dev_priv);
1560 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1562 dev_priv->suspend_count++;
1564 intel_csr_ucode_suspend(dev_priv);
1567 enable_rpm_wakeref_asserts(dev_priv);
1572 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1574 struct drm_i915_private *dev_priv = to_i915(dev);
1575 struct pci_dev *pdev = dev_priv->drm.pdev;
1579 disable_rpm_wakeref_asserts(dev_priv);
1581 intel_display_set_init_power(dev_priv, false);
1583 fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1584 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1586 * In case of firmware assisted context save/restore don't manually
1587 * deinit the power domains. This also means the CSR/DMC firmware will
1588 * stay active, it will power down any HW resources as required and
1589 * also enable deeper system power states that would be blocked if the
1590 * firmware was inactive.
1593 intel_power_domains_suspend(dev_priv);
1596 if (IS_GEN9_LP(dev_priv))
1597 bxt_enable_dc9(dev_priv);
1598 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1599 hsw_enable_pc8(dev_priv);
1600 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1601 ret = vlv_suspend_complete(dev_priv);
1604 DRM_ERROR("Suspend complete failed: %d\n", ret);
1606 intel_power_domains_init_hw(dev_priv, true);
1611 pci_disable_device(pdev);
1613 * During hibernation on some platforms the BIOS may try to access
1614 * the device even though it's already in D3 and hang the machine. So
1615 * leave the device in D0 on those platforms and hope the BIOS will
1616 * power down the device properly. The issue was seen on multiple old
1617 * GENs with different BIOS vendors, so having an explicit blacklist
1618 * is inpractical; apply the workaround on everything pre GEN6. The
1619 * platforms where the issue was seen:
1620 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1624 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1625 pci_set_power_state(pdev, PCI_D3hot);
1627 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1630 enable_rpm_wakeref_asserts(dev_priv);
1635 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1640 DRM_ERROR("dev: %p\n", dev);
1641 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1645 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1646 state.event != PM_EVENT_FREEZE))
1649 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1652 error = i915_drm_suspend(dev);
1656 return i915_drm_suspend_late(dev, false);
1659 static int i915_drm_resume(struct drm_device *dev)
1661 struct drm_i915_private *dev_priv = to_i915(dev);
1664 disable_rpm_wakeref_asserts(dev_priv);
1665 intel_sanitize_gt_powersave(dev_priv);
1667 ret = i915_ggtt_enable_hw(dev_priv);
1669 DRM_ERROR("failed to re-enable GGTT\n");
1671 intel_csr_ucode_resume(dev_priv);
1673 i915_gem_resume(dev_priv);
1675 i915_restore_state(dev_priv);
1676 intel_pps_unlock_regs_wa(dev_priv);
1677 intel_opregion_setup(dev_priv);
1679 intel_init_pch_refclk(dev_priv);
1682 * Interrupts have to be enabled before any batches are run. If not the
1683 * GPU will hang. i915_gem_init_hw() will initiate batches to
1684 * update/restore the context.
1686 * drm_mode_config_reset() needs AUX interrupts.
1688 * Modeset enabling in intel_modeset_init_hw() also needs working
1691 intel_runtime_pm_enable_interrupts(dev_priv);
1693 drm_mode_config_reset(dev);
1695 mutex_lock(&dev->struct_mutex);
1696 if (i915_gem_init_hw(dev_priv)) {
1697 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1698 i915_gem_set_wedged(dev_priv);
1700 mutex_unlock(&dev->struct_mutex);
1702 intel_guc_resume(dev_priv);
1704 intel_modeset_init_hw(dev);
1706 spin_lock_irq(&dev_priv->irq_lock);
1707 if (dev_priv->display.hpd_irq_setup)
1708 dev_priv->display.hpd_irq_setup(dev_priv);
1709 spin_unlock_irq(&dev_priv->irq_lock);
1711 intel_dp_mst_resume(dev);
1713 intel_display_resume(dev);
1715 drm_kms_helper_poll_enable(dev);
1718 * ... but also need to make sure that hotplug processing
1719 * doesn't cause havoc. Like in the driver load code we don't
1720 * bother with the tiny race here where we might loose hotplug
1723 intel_hpd_init(dev_priv);
1725 intel_opregion_register(dev_priv);
1727 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1729 mutex_lock(&dev_priv->modeset_restore_lock);
1730 dev_priv->modeset_restore = MODESET_DONE;
1731 mutex_unlock(&dev_priv->modeset_restore_lock);
1733 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1735 intel_autoenable_gt_powersave(dev_priv);
1737 enable_rpm_wakeref_asserts(dev_priv);
1742 static int i915_drm_resume_early(struct drm_device *dev)
1744 struct drm_i915_private *dev_priv = to_i915(dev);
1745 struct pci_dev *pdev = dev_priv->drm.pdev;
1749 * We have a resume ordering issue with the snd-hda driver also
1750 * requiring our device to be power up. Due to the lack of a
1751 * parent/child relationship we currently solve this with an early
1754 * FIXME: This should be solved with a special hdmi sink device or
1755 * similar so that power domains can be employed.
1759 * Note that we need to set the power state explicitly, since we
1760 * powered off the device during freeze and the PCI core won't power
1761 * it back up for us during thaw. Powering off the device during
1762 * freeze is not a hard requirement though, and during the
1763 * suspend/resume phases the PCI core makes sure we get here with the
1764 * device powered on. So in case we change our freeze logic and keep
1765 * the device powered we can also remove the following set power state
1768 ret = pci_set_power_state(pdev, PCI_D0);
1770 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1775 * Note that pci_enable_device() first enables any parent bridge
1776 * device and only then sets the power state for this device. The
1777 * bridge enabling is a nop though, since bridge devices are resumed
1778 * first. The order of enabling power and enabling the device is
1779 * imposed by the PCI core as described above, so here we preserve the
1780 * same order for the freeze/thaw phases.
1782 * TODO: eventually we should remove pci_disable_device() /
1783 * pci_enable_enable_device() from suspend/resume. Due to how they
1784 * depend on the device enable refcount we can't anyway depend on them
1785 * disabling/enabling the device.
1787 if (pci_enable_device(pdev)) {
1792 pci_set_master(pdev);
1794 disable_rpm_wakeref_asserts(dev_priv);
1796 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1797 ret = vlv_resume_prepare(dev_priv, false);
1799 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1802 intel_uncore_resume_early(dev_priv);
1804 if (IS_GEN9_LP(dev_priv)) {
1805 if (!dev_priv->suspended_to_idle)
1806 gen9_sanitize_dc_state(dev_priv);
1807 bxt_disable_dc9(dev_priv);
1808 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1809 hsw_disable_pc8(dev_priv);
1812 intel_uncore_sanitize(dev_priv);
1814 if (IS_GEN9_LP(dev_priv) ||
1815 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1816 intel_power_domains_init_hw(dev_priv, true);
1818 i915_gem_sanitize(dev_priv);
1820 enable_rpm_wakeref_asserts(dev_priv);
1823 dev_priv->suspended_to_idle = false;
1828 static int i915_resume_switcheroo(struct drm_device *dev)
1832 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1835 ret = i915_drm_resume_early(dev);
1839 return i915_drm_resume(dev);
1843 * i915_reset - reset chip after a hang
1844 * @i915: #drm_i915_private to reset
1845 * @flags: Instructions
1847 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1850 * Caller must hold the struct_mutex.
1852 * Procedure is fairly simple:
1853 * - reset the chip using the reset reg
1854 * - re-init context state
1855 * - re-init hardware status page
1856 * - re-init ring buffer
1857 * - re-init interrupt state
1860 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1862 struct i915_gpu_error *error = &i915->gpu_error;
1865 lockdep_assert_held(&i915->drm.struct_mutex);
1866 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1868 if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1871 /* Clear any previous failed attempts at recovery. Time to try again. */
1872 if (!i915_gem_unset_wedged(i915))
1875 if (!(flags & I915_RESET_QUIET))
1876 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1877 error->reset_count++;
1879 disable_irq(i915->drm.irq);
1880 ret = i915_gem_reset_prepare(i915);
1882 DRM_ERROR("GPU recovery failed\n");
1883 intel_gpu_reset(i915, ALL_ENGINES);
1887 ret = intel_gpu_reset(i915, ALL_ENGINES);
1890 DRM_ERROR("Failed to reset chip: %i\n", ret);
1892 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1896 i915_gem_reset(i915);
1897 intel_overlay_reset(i915);
1899 /* Ok, now get things going again... */
1902 * Everything depends on having the GTT running, so we need to start
1905 ret = i915_ggtt_enable_hw(i915);
1907 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1912 * Next we need to restore the context, but we don't use those
1915 * Ring buffer needs to be re-initialized in the KMS case, or if X
1916 * was running at the time of the reset (i.e. we weren't VT
1919 ret = i915_gem_init_hw(i915);
1921 DRM_ERROR("Failed hw init on reset %d\n", ret);
1925 i915_queue_hangcheck(i915);
1928 i915_gem_reset_finish(i915);
1929 enable_irq(i915->drm.irq);
1932 clear_bit(I915_RESET_HANDOFF, &error->flags);
1933 wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1937 i915_gem_set_wedged(i915);
1938 i915_gem_retire_requests(i915);
1943 * i915_reset_engine - reset GPU engine to recover from a hang
1944 * @engine: engine to reset
1947 * Reset a specific GPU engine. Useful if a hang is detected.
1948 * Returns zero on successful reset or otherwise an error code.
1951 * - identifies the request that caused the hang and it is dropped
1952 * - reset engine (which will force the engine to idle)
1953 * - re-init/configure engine
1955 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1957 struct i915_gpu_error *error = &engine->i915->gpu_error;
1958 struct drm_i915_gem_request *active_request;
1961 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1963 if (!(flags & I915_RESET_QUIET)) {
1964 dev_notice(engine->i915->drm.dev,
1965 "Resetting %s after gpu hang\n", engine->name);
1967 error->reset_engine_count[engine->id]++;
1969 active_request = i915_gem_reset_prepare_engine(engine);
1970 if (IS_ERR(active_request)) {
1971 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1972 ret = PTR_ERR(active_request);
1976 ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
1978 /* If we fail here, we expect to fallback to a global reset */
1979 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1985 * The request that caused the hang is stuck on elsp, we know the
1986 * active request and can drop it, adjust head to skip the offending
1987 * request to resume executing remaining requests in the queue.
1989 i915_gem_reset_engine(engine, active_request);
1992 * The engine and its registers (and workarounds in case of render)
1993 * have been reset to their default values. Follow the init_ring
1994 * process to program RING_MODE, HWSP and re-enable submission.
1996 ret = engine->init_hw(engine);
2001 i915_gem_reset_finish_engine(engine);
2005 static int i915_pm_suspend(struct device *kdev)
2007 struct pci_dev *pdev = to_pci_dev(kdev);
2008 struct drm_device *dev = pci_get_drvdata(pdev);
2011 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2015 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2018 return i915_drm_suspend(dev);
2021 static int i915_pm_suspend_late(struct device *kdev)
2023 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2026 * We have a suspend ordering issue with the snd-hda driver also
2027 * requiring our device to be power up. Due to the lack of a
2028 * parent/child relationship we currently solve this with an late
2031 * FIXME: This should be solved with a special hdmi sink device or
2032 * similar so that power domains can be employed.
2034 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2037 return i915_drm_suspend_late(dev, false);
2040 static int i915_pm_poweroff_late(struct device *kdev)
2042 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2044 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2047 return i915_drm_suspend_late(dev, true);
2050 static int i915_pm_resume_early(struct device *kdev)
2052 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2054 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2057 return i915_drm_resume_early(dev);
2060 static int i915_pm_resume(struct device *kdev)
2062 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2064 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2067 return i915_drm_resume(dev);
2070 /* freeze: before creating the hibernation_image */
2071 static int i915_pm_freeze(struct device *kdev)
2073 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2076 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2077 ret = i915_drm_suspend(dev);
2082 ret = i915_gem_freeze(kdev_to_i915(kdev));
2089 static int i915_pm_freeze_late(struct device *kdev)
2091 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2094 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2095 ret = i915_drm_suspend_late(dev, true);
2100 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2107 /* thaw: called after creating the hibernation image, but before turning off. */
2108 static int i915_pm_thaw_early(struct device *kdev)
2110 return i915_pm_resume_early(kdev);
2113 static int i915_pm_thaw(struct device *kdev)
2115 return i915_pm_resume(kdev);
2118 /* restore: called after loading the hibernation image. */
2119 static int i915_pm_restore_early(struct device *kdev)
2121 return i915_pm_resume_early(kdev);
2124 static int i915_pm_restore(struct device *kdev)
2126 return i915_pm_resume(kdev);
2130 * Save all Gunit registers that may be lost after a D3 and a subsequent
2131 * S0i[R123] transition. The list of registers needing a save/restore is
2132 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2133 * registers in the following way:
2134 * - Driver: saved/restored by the driver
2135 * - Punit : saved/restored by the Punit firmware
2136 * - No, w/o marking: no need to save/restore, since the register is R/O or
2137 * used internally by the HW in a way that doesn't depend
2138 * keeping the content across a suspend/resume.
2139 * - Debug : used for debugging
2141 * We save/restore all registers marked with 'Driver', with the following
2143 * - Registers out of use, including also registers marked with 'Debug'.
2144 * These have no effect on the driver's operation, so we don't save/restore
2145 * them to reduce the overhead.
2146 * - Registers that are fully setup by an initialization function called from
2147 * the resume path. For example many clock gating and RPS/RC6 registers.
2148 * - Registers that provide the right functionality with their reset defaults.
2150 * TODO: Except for registers that based on the above 3 criteria can be safely
2151 * ignored, we save/restore all others, practically treating the HW context as
2152 * a black-box for the driver. Further investigation is needed to reduce the
2153 * saved/restored registers even further, by following the same 3 criteria.
2155 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2157 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2160 /* GAM 0x4000-0x4770 */
2161 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2162 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2163 s->arb_mode = I915_READ(ARB_MODE);
2164 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2165 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2167 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2168 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2170 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2171 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2173 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2174 s->ecochk = I915_READ(GAM_ECOCHK);
2175 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2176 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2178 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2180 /* MBC 0x9024-0x91D0, 0x8500 */
2181 s->g3dctl = I915_READ(VLV_G3DCTL);
2182 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2183 s->mbctl = I915_READ(GEN6_MBCTL);
2185 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2186 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2187 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2188 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2189 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2190 s->rstctl = I915_READ(GEN6_RSTCTL);
2191 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2193 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2194 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2195 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2196 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2197 s->ecobus = I915_READ(ECOBUS);
2198 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2199 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2200 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2201 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2202 s->rcedata = I915_READ(VLV_RCEDATA);
2203 s->spare2gh = I915_READ(VLV_SPAREG2H);
2205 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2206 s->gt_imr = I915_READ(GTIMR);
2207 s->gt_ier = I915_READ(GTIER);
2208 s->pm_imr = I915_READ(GEN6_PMIMR);
2209 s->pm_ier = I915_READ(GEN6_PMIER);
2211 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2212 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2214 /* GT SA CZ domain, 0x100000-0x138124 */
2215 s->tilectl = I915_READ(TILECTL);
2216 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2217 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2218 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2219 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2221 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2222 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2223 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2224 s->pcbr = I915_READ(VLV_PCBR);
2225 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2228 * Not saving any of:
2229 * DFT, 0x9800-0x9EC0
2230 * SARB, 0xB000-0xB1FC
2231 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2236 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2238 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2242 /* GAM 0x4000-0x4770 */
2243 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2244 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2245 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2246 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2247 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2249 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2250 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2252 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2253 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2255 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2256 I915_WRITE(GAM_ECOCHK, s->ecochk);
2257 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2258 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2260 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2262 /* MBC 0x9024-0x91D0, 0x8500 */
2263 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2264 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2265 I915_WRITE(GEN6_MBCTL, s->mbctl);
2267 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2268 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2269 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2270 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2271 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2272 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2273 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2275 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2276 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2277 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2278 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2279 I915_WRITE(ECOBUS, s->ecobus);
2280 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2281 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2282 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2283 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2284 I915_WRITE(VLV_RCEDATA, s->rcedata);
2285 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2287 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2288 I915_WRITE(GTIMR, s->gt_imr);
2289 I915_WRITE(GTIER, s->gt_ier);
2290 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2291 I915_WRITE(GEN6_PMIER, s->pm_ier);
2293 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2294 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2296 /* GT SA CZ domain, 0x100000-0x138124 */
2297 I915_WRITE(TILECTL, s->tilectl);
2298 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2300 * Preserve the GT allow wake and GFX force clock bit, they are not
2301 * be restored, as they are used to control the s0ix suspend/resume
2302 * sequence by the caller.
2304 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2305 val &= VLV_GTLC_ALLOWWAKEREQ;
2306 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2307 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2309 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2310 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2311 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2312 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2314 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2316 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2317 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2318 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2319 I915_WRITE(VLV_PCBR, s->pcbr);
2320 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2323 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2326 /* The HW does not like us polling for PW_STATUS frequently, so
2327 * use the sleeping loop rather than risk the busy spin within
2328 * intel_wait_for_register().
2330 * Transitioning between RC6 states should be at most 2ms (see
2331 * valleyview_enable_rps) so use a 3ms timeout.
2333 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2337 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2342 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2343 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2345 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2346 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2351 err = intel_wait_for_register(dev_priv,
2352 VLV_GTLC_SURVIVABILITY_REG,
2353 VLV_GFX_CLK_STATUS_BIT,
2354 VLV_GFX_CLK_STATUS_BIT,
2357 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2358 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2363 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2369 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2370 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2372 val |= VLV_GTLC_ALLOWWAKEREQ;
2373 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2374 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2376 mask = VLV_GTLC_ALLOWWAKEACK;
2377 val = allow ? mask : 0;
2379 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2381 DRM_ERROR("timeout disabling GT waking\n");
2386 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2392 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2393 val = wait_for_on ? mask : 0;
2396 * RC6 transitioning can be delayed up to 2 msec (see
2397 * valleyview_enable_rps), use 3 msec for safety.
2399 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2400 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2401 onoff(wait_for_on));
2404 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2406 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2409 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2410 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2413 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2419 * Bspec defines the following GT well on flags as debug only, so
2420 * don't treat them as hard failures.
2422 vlv_wait_for_gt_wells(dev_priv, false);
2424 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2425 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2427 vlv_check_no_gt_access(dev_priv);
2429 err = vlv_force_gfx_clock(dev_priv, true);
2433 err = vlv_allow_gt_wake(dev_priv, false);
2437 if (!IS_CHERRYVIEW(dev_priv))
2438 vlv_save_gunit_s0ix_state(dev_priv);
2440 err = vlv_force_gfx_clock(dev_priv, false);
2447 /* For safety always re-enable waking and disable gfx clock forcing */
2448 vlv_allow_gt_wake(dev_priv, true);
2450 vlv_force_gfx_clock(dev_priv, false);
2455 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2462 * If any of the steps fail just try to continue, that's the best we
2463 * can do at this point. Return the first error code (which will also
2464 * leave RPM permanently disabled).
2466 ret = vlv_force_gfx_clock(dev_priv, true);
2468 if (!IS_CHERRYVIEW(dev_priv))
2469 vlv_restore_gunit_s0ix_state(dev_priv);
2471 err = vlv_allow_gt_wake(dev_priv, true);
2475 err = vlv_force_gfx_clock(dev_priv, false);
2479 vlv_check_no_gt_access(dev_priv);
2482 intel_init_clock_gating(dev_priv);
2487 static int intel_runtime_suspend(struct device *kdev)
2489 struct pci_dev *pdev = to_pci_dev(kdev);
2490 struct drm_device *dev = pci_get_drvdata(pdev);
2491 struct drm_i915_private *dev_priv = to_i915(dev);
2494 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2497 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2500 DRM_DEBUG_KMS("Suspending device\n");
2502 disable_rpm_wakeref_asserts(dev_priv);
2505 * We are safe here against re-faults, since the fault handler takes
2508 i915_gem_runtime_suspend(dev_priv);
2510 intel_guc_suspend(dev_priv);
2512 intel_runtime_pm_disable_interrupts(dev_priv);
2515 if (IS_GEN9_LP(dev_priv)) {
2516 bxt_display_core_uninit(dev_priv);
2517 bxt_enable_dc9(dev_priv);
2518 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2519 hsw_enable_pc8(dev_priv);
2520 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2521 ret = vlv_suspend_complete(dev_priv);
2525 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2526 intel_runtime_pm_enable_interrupts(dev_priv);
2528 enable_rpm_wakeref_asserts(dev_priv);
2533 intel_uncore_suspend(dev_priv);
2535 enable_rpm_wakeref_asserts(dev_priv);
2536 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2538 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2539 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2541 dev_priv->pm.suspended = true;
2544 * FIXME: We really should find a document that references the arguments
2547 if (IS_BROADWELL(dev_priv)) {
2549 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2550 * being detected, and the call we do at intel_runtime_resume()
2551 * won't be able to restore them. Since PCI_D3hot matches the
2552 * actual specification and appears to be working, use it.
2554 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2557 * current versions of firmware which depend on this opregion
2558 * notification have repurposed the D1 definition to mean
2559 * "runtime suspended" vs. what you would normally expect (D3)
2560 * to distinguish it from notifications that might be sent via
2563 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2566 assert_forcewakes_inactive(dev_priv);
2568 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2569 intel_hpd_poll_init(dev_priv);
2571 DRM_DEBUG_KMS("Device suspended\n");
2575 static int intel_runtime_resume(struct device *kdev)
2577 struct pci_dev *pdev = to_pci_dev(kdev);
2578 struct drm_device *dev = pci_get_drvdata(pdev);
2579 struct drm_i915_private *dev_priv = to_i915(dev);
2582 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2585 DRM_DEBUG_KMS("Resuming device\n");
2587 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2588 disable_rpm_wakeref_asserts(dev_priv);
2590 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2591 dev_priv->pm.suspended = false;
2592 if (intel_uncore_unclaimed_mmio(dev_priv))
2593 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2595 intel_guc_resume(dev_priv);
2597 if (IS_GEN9_LP(dev_priv)) {
2598 bxt_disable_dc9(dev_priv);
2599 bxt_display_core_init(dev_priv, true);
2600 if (dev_priv->csr.dmc_payload &&
2601 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2602 gen9_enable_dc5(dev_priv);
2603 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2604 hsw_disable_pc8(dev_priv);
2605 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2606 ret = vlv_resume_prepare(dev_priv, true);
2610 * No point of rolling back things in case of an error, as the best
2611 * we can do is to hope that things will still work (and disable RPM).
2613 i915_gem_init_swizzling(dev_priv);
2614 i915_gem_restore_fences(dev_priv);
2616 intel_runtime_pm_enable_interrupts(dev_priv);
2619 * On VLV/CHV display interrupts are part of the display
2620 * power well, so hpd is reinitialized from there. For
2621 * everyone else do it here.
2623 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2624 intel_hpd_init(dev_priv);
2626 intel_enable_ipc(dev_priv);
2628 enable_rpm_wakeref_asserts(dev_priv);
2631 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2633 DRM_DEBUG_KMS("Device resumed\n");
2638 const struct dev_pm_ops i915_pm_ops = {
2640 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2643 .suspend = i915_pm_suspend,
2644 .suspend_late = i915_pm_suspend_late,
2645 .resume_early = i915_pm_resume_early,
2646 .resume = i915_pm_resume,
2650 * @freeze, @freeze_late : called (1) before creating the
2651 * hibernation image [PMSG_FREEZE] and
2652 * (2) after rebooting, before restoring
2653 * the image [PMSG_QUIESCE]
2654 * @thaw, @thaw_early : called (1) after creating the hibernation
2655 * image, before writing it [PMSG_THAW]
2656 * and (2) after failing to create or
2657 * restore the image [PMSG_RECOVER]
2658 * @poweroff, @poweroff_late: called after writing the hibernation
2659 * image, before rebooting [PMSG_HIBERNATE]
2660 * @restore, @restore_early : called after rebooting and restoring the
2661 * hibernation image [PMSG_RESTORE]
2663 .freeze = i915_pm_freeze,
2664 .freeze_late = i915_pm_freeze_late,
2665 .thaw_early = i915_pm_thaw_early,
2666 .thaw = i915_pm_thaw,
2667 .poweroff = i915_pm_suspend,
2668 .poweroff_late = i915_pm_poweroff_late,
2669 .restore_early = i915_pm_restore_early,
2670 .restore = i915_pm_restore,
2672 /* S0ix (via runtime suspend) event handlers */
2673 .runtime_suspend = intel_runtime_suspend,
2674 .runtime_resume = intel_runtime_resume,
2677 static const struct vm_operations_struct i915_gem_vm_ops = {
2678 .fault = i915_gem_fault,
2679 .open = drm_gem_vm_open,
2680 .close = drm_gem_vm_close,
2683 static const struct file_operations i915_driver_fops = {
2684 .owner = THIS_MODULE,
2686 .release = drm_release,
2687 .unlocked_ioctl = drm_ioctl,
2688 .mmap = drm_gem_mmap,
2691 .compat_ioctl = i915_compat_ioctl,
2692 .llseek = noop_llseek,
2696 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2697 struct drm_file *file)
2702 static const struct drm_ioctl_desc i915_ioctls[] = {
2703 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2704 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2705 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2706 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2707 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2708 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2709 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2710 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2711 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2712 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2713 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2714 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2715 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2716 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2717 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2718 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2719 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2720 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2721 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2722 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2723 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2724 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2725 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2726 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2727 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2728 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2729 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2730 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2731 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2732 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2733 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2734 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2735 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2736 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2737 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2738 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2739 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2740 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2741 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2742 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2743 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2744 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2745 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2746 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2747 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2748 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2749 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2750 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2751 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2752 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2753 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2754 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2755 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2756 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2757 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2760 static struct drm_driver driver = {
2761 /* Don't use MTRRs here; the Xserver or userspace app should
2762 * deal with them for Intel hardware.
2765 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2766 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2767 .release = i915_driver_release,
2768 .open = i915_driver_open,
2769 .lastclose = i915_driver_lastclose,
2770 .postclose = i915_driver_postclose,
2772 .gem_close_object = i915_gem_close_object,
2773 .gem_free_object_unlocked = i915_gem_free_object,
2774 .gem_vm_ops = &i915_gem_vm_ops,
2776 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2777 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2778 .gem_prime_export = i915_gem_prime_export,
2779 .gem_prime_import = i915_gem_prime_import,
2781 .dumb_create = i915_gem_dumb_create,
2782 .dumb_map_offset = i915_gem_mmap_gtt,
2783 .ioctls = i915_ioctls,
2784 .num_ioctls = ARRAY_SIZE(i915_ioctls),
2785 .fops = &i915_driver_fops,
2786 .name = DRIVER_NAME,
2787 .desc = DRIVER_DESC,
2788 .date = DRIVER_DATE,
2789 .major = DRIVER_MAJOR,
2790 .minor = DRIVER_MINOR,
2791 .patchlevel = DRIVER_PATCHLEVEL,
2794 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2795 #include "selftests/mock_drm.c"