git.rot13.org Git - linux/blob - drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vgaarb.h>
  27 #include <linux/vga_switcheroo.h>
  28
  29 #include "i915_active.h"
  30 #include "i915_drv.h"
  31 #include "i915_selftest.h"
  32
  33 #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
  34 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  35
  36 #define GEN_DEFAULT_PIPEOFFSETS \
  37         .pipe_offsets = { \
  38                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  39                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  40                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  41                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  42         }, \
  43         .trans_offsets = { \
  44                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  45                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  46                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  47                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  48         }
  49
  50 #define GEN_CHV_PIPEOFFSETS \
  51         .pipe_offsets = { \
  52                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  53                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  54                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  55         }, \
  56         .trans_offsets = { \
  57                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  58                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  59                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  60         }
  61
  62 #define CURSOR_OFFSETS \
  63         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  64
  65 #define IVB_CURSOR_OFFSETS \
  66         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  67
  68 #define BDW_COLORS \
  69         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  70 #define CHV_COLORS \
  71         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
  72                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
  73                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
  74         }
  75 #define GLK_COLORS \
  76         .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024, \
  77                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
  78                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
  79         }
  80
  81 /* Keep in gen based order, and chronological order within a gen */
  82
  83 #define GEN_DEFAULT_PAGE_SIZES \
  84         .page_sizes = I915_GTT_PAGE_SIZE_4K
  85
  86 #define GEN2_FEATURES \
  87         GEN(2), \
  88         .num_pipes = 1, \
  89         .display.has_overlay = 1, \
  90         .display.overlay_needs_physical = 1, \
  91         .display.has_gmch = 1, \
  92         .gpu_reset_clobbers_display = true, \
  93         .hws_needs_physical = 1, \
  94         .unfenced_needs_alignment = 1, \
  95         .ring_mask = RENDER_RING, \
  96         .has_snoop = true, \
  97         .has_coherent_ggtt = false, \
  98         GEN_DEFAULT_PIPEOFFSETS, \
  99         GEN_DEFAULT_PAGE_SIZES, \
 100         CURSOR_OFFSETS
 101
 102 static const struct intel_device_info intel_i830_info = {
 103         GEN2_FEATURES,
 104         PLATFORM(INTEL_I830),
 105         .is_mobile = 1,
 106         .display.cursor_needs_physical = 1,
 107         .num_pipes = 2, /* legal, last one wins */
 108 };
 109
 110 static const struct intel_device_info intel_i845g_info = {
 111         GEN2_FEATURES,
 112         PLATFORM(INTEL_I845G),
 113 };
 114
 115 static const struct intel_device_info intel_i85x_info = {
 116         GEN2_FEATURES,
 117         PLATFORM(INTEL_I85X),
 118         .is_mobile = 1,
 119         .num_pipes = 2, /* legal, last one wins */
 120         .display.cursor_needs_physical = 1,
 121         .display.has_fbc = 1,
 122 };
 123
 124 static const struct intel_device_info intel_i865g_info = {
 125         GEN2_FEATURES,
 126         PLATFORM(INTEL_I865G),
 127 };
 128
 129 #define GEN3_FEATURES \
 130         GEN(3), \
 131         .num_pipes = 2, \
 132         .display.has_gmch = 1, \
 133         .gpu_reset_clobbers_display = true, \
 134         .ring_mask = RENDER_RING, \
 135         .has_snoop = true, \
 136         .has_coherent_ggtt = true, \
 137         GEN_DEFAULT_PIPEOFFSETS, \
 138         GEN_DEFAULT_PAGE_SIZES, \
 139         CURSOR_OFFSETS
 140
 141 static const struct intel_device_info intel_i915g_info = {
 142         GEN3_FEATURES,
 143         PLATFORM(INTEL_I915G),
 144         .has_coherent_ggtt = false,
 145         .display.cursor_needs_physical = 1,
 146         .display.has_overlay = 1,
 147         .display.overlay_needs_physical = 1,
 148         .hws_needs_physical = 1,
 149         .unfenced_needs_alignment = 1,
 150 };
 151
 152 static const struct intel_device_info intel_i915gm_info = {
 153         GEN3_FEATURES,
 154         PLATFORM(INTEL_I915GM),
 155         .is_mobile = 1,
 156         .display.cursor_needs_physical = 1,
 157         .display.has_overlay = 1,
 158         .display.overlay_needs_physical = 1,
 159         .display.supports_tv = 1,
 160         .display.has_fbc = 1,
 161         .hws_needs_physical = 1,
 162         .unfenced_needs_alignment = 1,
 163 };
 164
 165 static const struct intel_device_info intel_i945g_info = {
 166         GEN3_FEATURES,
 167         PLATFORM(INTEL_I945G),
 168         .display.has_hotplug = 1,
 169         .display.cursor_needs_physical = 1,
 170         .display.has_overlay = 1,
 171         .display.overlay_needs_physical = 1,
 172         .hws_needs_physical = 1,
 173         .unfenced_needs_alignment = 1,
 174 };
 175
 176 static const struct intel_device_info intel_i945gm_info = {
 177         GEN3_FEATURES,
 178         PLATFORM(INTEL_I945GM),
 179         .is_mobile = 1,
 180         .display.has_hotplug = 1,
 181         .display.cursor_needs_physical = 1,
 182         .display.has_overlay = 1,
 183         .display.overlay_needs_physical = 1,
 184         .display.supports_tv = 1,
 185         .display.has_fbc = 1,
 186         .hws_needs_physical = 1,
 187         .unfenced_needs_alignment = 1,
 188 };
 189
 190 static const struct intel_device_info intel_g33_info = {
 191         GEN3_FEATURES,
 192         PLATFORM(INTEL_G33),
 193         .display.has_hotplug = 1,
 194         .display.has_overlay = 1,
 195 };
 196
 197 static const struct intel_device_info intel_pineview_info = {
 198         GEN3_FEATURES,
 199         PLATFORM(INTEL_PINEVIEW),
 200         .is_mobile = 1,
 201         .display.has_hotplug = 1,
 202         .display.has_overlay = 1,
 203 };
 204
 205 #define GEN4_FEATURES \
 206         GEN(4), \
 207         .num_pipes = 2, \
 208         .display.has_hotplug = 1, \
 209         .display.has_gmch = 1, \
 210         .gpu_reset_clobbers_display = true, \
 211         .ring_mask = RENDER_RING, \
 212         .has_snoop = true, \
 213         .has_coherent_ggtt = true, \
 214         GEN_DEFAULT_PIPEOFFSETS, \
 215         GEN_DEFAULT_PAGE_SIZES, \
 216         CURSOR_OFFSETS
 217
 218 static const struct intel_device_info intel_i965g_info = {
 219         GEN4_FEATURES,
 220         PLATFORM(INTEL_I965G),
 221         .display.has_overlay = 1,
 222         .hws_needs_physical = 1,
 223         .has_snoop = false,
 224 };
 225
 226 static const struct intel_device_info intel_i965gm_info = {
 227         GEN4_FEATURES,
 228         PLATFORM(INTEL_I965GM),
 229         .is_mobile = 1,
 230         .display.has_fbc = 1,
 231         .display.has_overlay = 1,
 232         .display.supports_tv = 1,
 233         .hws_needs_physical = 1,
 234         .has_snoop = false,
 235 };
 236
 237 static const struct intel_device_info intel_g45_info = {
 238         GEN4_FEATURES,
 239         PLATFORM(INTEL_G45),
 240         .ring_mask = RENDER_RING | BSD_RING,
 241         .gpu_reset_clobbers_display = false,
 242 };
 243
 244 static const struct intel_device_info intel_gm45_info = {
 245         GEN4_FEATURES,
 246         PLATFORM(INTEL_GM45),
 247         .is_mobile = 1,
 248         .display.has_fbc = 1,
 249         .display.supports_tv = 1,
 250         .ring_mask = RENDER_RING | BSD_RING,
 251         .gpu_reset_clobbers_display = false,
 252 };
 253
 254 #define GEN5_FEATURES \
 255         GEN(5), \
 256         .num_pipes = 2, \
 257         .display.has_hotplug = 1, \
 258         .ring_mask = RENDER_RING | BSD_RING, \
 259         .has_snoop = true, \
 260         .has_coherent_ggtt = true, \
 261         /* ilk does support rc6, but we do not implement [power] contexts */ \
 262         .has_rc6 = 0, \
 263         GEN_DEFAULT_PIPEOFFSETS, \
 264         GEN_DEFAULT_PAGE_SIZES, \
 265         CURSOR_OFFSETS
 266
 267 static const struct intel_device_info intel_ironlake_d_info = {
 268         GEN5_FEATURES,
 269         PLATFORM(INTEL_IRONLAKE),
 270 };
 271
 272 static const struct intel_device_info intel_ironlake_m_info = {
 273         GEN5_FEATURES,
 274         PLATFORM(INTEL_IRONLAKE),
 275         .is_mobile = 1,
 276         .display.has_fbc = 1,
 277 };
 278
 279 #define GEN6_FEATURES \
 280         GEN(6), \
 281         .num_pipes = 2, \
 282         .display.has_hotplug = 1, \
 283         .display.has_fbc = 1, \
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 285         .has_coherent_ggtt = true, \
 286         .has_llc = 1, \
 287         .has_rc6 = 1, \
 288         .has_rc6p = 1, \
 289         .ppgtt = INTEL_PPGTT_ALIASING, \
 290         GEN_DEFAULT_PIPEOFFSETS, \
 291         GEN_DEFAULT_PAGE_SIZES, \
 292         CURSOR_OFFSETS
 293
 294 #define SNB_D_PLATFORM \
 295         GEN6_FEATURES, \
 296         PLATFORM(INTEL_SANDYBRIDGE)
 297
 298 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 299         SNB_D_PLATFORM,
 300         .gt = 1,
 301 };
 302
 303 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 304         SNB_D_PLATFORM,
 305         .gt = 2,
 306 };
 307
 308 #define SNB_M_PLATFORM \
 309         GEN6_FEATURES, \
 310         PLATFORM(INTEL_SANDYBRIDGE), \
 311         .is_mobile = 1
 312
 313
 314 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 315         SNB_M_PLATFORM,
 316         .gt = 1,
 317 };
 318
 319 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 320         SNB_M_PLATFORM,
 321         .gt = 2,
 322 };
 323
 324 #define GEN7_FEATURES  \
 325         GEN(7), \
 326         .num_pipes = 3, \
 327         .display.has_hotplug = 1, \
 328         .display.has_fbc = 1, \
 329         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 330         .has_coherent_ggtt = true, \
 331         .has_llc = 1, \
 332         .has_rc6 = 1, \
 333         .has_rc6p = 1, \
 334         .ppgtt = INTEL_PPGTT_FULL, \
 335         GEN_DEFAULT_PIPEOFFSETS, \
 336         GEN_DEFAULT_PAGE_SIZES, \
 337         IVB_CURSOR_OFFSETS
 338
 339 #define IVB_D_PLATFORM \
 340         GEN7_FEATURES, \
 341         PLATFORM(INTEL_IVYBRIDGE), \
 342         .has_l3_dpf = 1
 343
 344 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 345         IVB_D_PLATFORM,
 346         .gt = 1,
 347 };
 348
 349 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 350         IVB_D_PLATFORM,
 351         .gt = 2,
 352 };
 353
 354 #define IVB_M_PLATFORM \
 355         GEN7_FEATURES, \
 356         PLATFORM(INTEL_IVYBRIDGE), \
 357         .is_mobile = 1, \
 358         .has_l3_dpf = 1
 359
 360 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 361         IVB_M_PLATFORM,
 362         .gt = 1,
 363 };
 364
 365 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
 366         IVB_M_PLATFORM,
 367         .gt = 2,
 368 };
 369
 370 static const struct intel_device_info intel_ivybridge_q_info = {
 371         GEN7_FEATURES,
 372         PLATFORM(INTEL_IVYBRIDGE),
 373         .gt = 2,
 374         .num_pipes = 0, /* legal, last one wins */
 375         .has_l3_dpf = 1,
 376 };
 377
 378 static const struct intel_device_info intel_valleyview_info = {
 379         PLATFORM(INTEL_VALLEYVIEW),
 380         GEN(7),
 381         .is_lp = 1,
 382         .num_pipes = 2,
 383         .has_runtime_pm = 1,
 384         .has_rc6 = 1,
 385         .display.has_gmch = 1,
 386         .display.has_hotplug = 1,
 387         .ppgtt = INTEL_PPGTT_FULL,
 388         .has_snoop = true,
 389         .has_coherent_ggtt = false,
 390         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 391         .display_mmio_offset = VLV_DISPLAY_BASE,
 392         GEN_DEFAULT_PAGE_SIZES,
 393         GEN_DEFAULT_PIPEOFFSETS,
 394         CURSOR_OFFSETS
 395 };
 396
 397 #define G75_FEATURES  \
 398         GEN7_FEATURES, \
 399         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 400         .display.has_ddi = 1, \
 401         .has_fpga_dbg = 1, \
 402         .display.has_psr = 1, \
 403         .display.has_dp_mst = 1, \
 404         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 405         .has_runtime_pm = 1
 406
 407 #define HSW_PLATFORM \
 408         G75_FEATURES, \
 409         PLATFORM(INTEL_HASWELL), \
 410         .has_l3_dpf = 1
 411
 412 static const struct intel_device_info intel_haswell_gt1_info = {
 413         HSW_PLATFORM,
 414         .gt = 1,
 415 };
 416
 417 static const struct intel_device_info intel_haswell_gt2_info = {
 418         HSW_PLATFORM,
 419         .gt = 2,
 420 };
 421
 422 static const struct intel_device_info intel_haswell_gt3_info = {
 423         HSW_PLATFORM,
 424         .gt = 3,
 425 };
 426
 427 #define GEN8_FEATURES \
 428         G75_FEATURES, \
 429         GEN(8), \
 430         BDW_COLORS, \
 431         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 432                       I915_GTT_PAGE_SIZE_2M, \
 433         .has_logical_ring_contexts = 1, \
 434         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 435         .has_64bit_reloc = 1, \
 436         .has_reset_engine = 1
 437
 438 #define BDW_PLATFORM \
 439         GEN8_FEATURES, \
 440         PLATFORM(INTEL_BROADWELL)
 441
 442 static const struct intel_device_info intel_broadwell_gt1_info = {
 443         BDW_PLATFORM,
 444         .gt = 1,
 445 };
 446
 447 static const struct intel_device_info intel_broadwell_gt2_info = {
 448         BDW_PLATFORM,
 449         .gt = 2,
 450 };
 451
 452 static const struct intel_device_info intel_broadwell_rsvd_info = {
 453         BDW_PLATFORM,
 454         .gt = 3,
 455         /* According to the device ID those devices are GT3, they were
 456          * previously treated as not GT3, keep it like that.
 457          */
 458 };
 459
 460 static const struct intel_device_info intel_broadwell_gt3_info = {
 461         BDW_PLATFORM,
 462         .gt = 3,
 463         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 464 };
 465
 466 static const struct intel_device_info intel_cherryview_info = {
 467         PLATFORM(INTEL_CHERRYVIEW),
 468         GEN(8),
 469         .num_pipes = 3,
 470         .display.has_hotplug = 1,
 471         .is_lp = 1,
 472         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 473         .has_64bit_reloc = 1,
 474         .has_runtime_pm = 1,
 475         .has_rc6 = 1,
 476         .has_logical_ring_contexts = 1,
 477         .display.has_gmch = 1,
 478         .ppgtt = INTEL_PPGTT_FULL,
 479         .has_reset_engine = 1,
 480         .has_snoop = true,
 481         .has_coherent_ggtt = false,
 482         .display_mmio_offset = VLV_DISPLAY_BASE,
 483         GEN_DEFAULT_PAGE_SIZES,
 484         GEN_CHV_PIPEOFFSETS,
 485         CURSOR_OFFSETS,
 486         CHV_COLORS,
 487 };
 488
 489 #define GEN9_DEFAULT_PAGE_SIZES \
 490         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 491                       I915_GTT_PAGE_SIZE_64K | \
 492                       I915_GTT_PAGE_SIZE_2M
 493
 494 #define GEN9_FEATURES \
 495         GEN8_FEATURES, \
 496         GEN(9), \
 497         GEN9_DEFAULT_PAGE_SIZES, \
 498         .has_logical_ring_preemption = 1, \
 499         .display.has_csr = 1, \
 500         .has_guc = 1, \
 501         .display.has_ipc = 1, \
 502         .ddb_size = 896
 503
 504 #define SKL_PLATFORM \
 505         GEN9_FEATURES, \
 506         /* Display WA #0477 WaDisableIPC: skl */ \
 507         .display.has_ipc = 0, \
 508         PLATFORM(INTEL_SKYLAKE)
 509
 510 static const struct intel_device_info intel_skylake_gt1_info = {
 511         SKL_PLATFORM,
 512         .gt = 1,
 513 };
 514
 515 static const struct intel_device_info intel_skylake_gt2_info = {
 516         SKL_PLATFORM,
 517         .gt = 2,
 518 };
 519
 520 #define SKL_GT3_PLUS_PLATFORM \
 521         SKL_PLATFORM, \
 522         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
 523
 524
 525 static const struct intel_device_info intel_skylake_gt3_info = {
 526         SKL_GT3_PLUS_PLATFORM,
 527         .gt = 3,
 528 };
 529
 530 static const struct intel_device_info intel_skylake_gt4_info = {
 531         SKL_GT3_PLUS_PLATFORM,
 532         .gt = 4,
 533 };
 534
 535 #define GEN9_LP_FEATURES \
 536         GEN(9), \
 537         .is_lp = 1, \
 538         .display.has_hotplug = 1, \
 539         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 540         .num_pipes = 3, \
 541         .has_64bit_reloc = 1, \
 542         .display.has_ddi = 1, \
 543         .has_fpga_dbg = 1, \
 544         .display.has_fbc = 1, \
 545         .display.has_psr = 1, \
 546         .has_runtime_pm = 1, \
 547         .display.has_csr = 1, \
 548         .has_rc6 = 1, \
 549         .display.has_dp_mst = 1, \
 550         .has_logical_ring_contexts = 1, \
 551         .has_logical_ring_preemption = 1, \
 552         .has_guc = 1, \
 553         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
 554         .has_reset_engine = 1, \
 555         .has_snoop = true, \
 556         .has_coherent_ggtt = false, \
 557         .display.has_ipc = 1, \
 558         GEN9_DEFAULT_PAGE_SIZES, \
 559         GEN_DEFAULT_PIPEOFFSETS, \
 560         IVB_CURSOR_OFFSETS, \
 561         BDW_COLORS
 562
 563 static const struct intel_device_info intel_broxton_info = {
 564         GEN9_LP_FEATURES,
 565         PLATFORM(INTEL_BROXTON),
 566         .ddb_size = 512,
 567 };
 568
 569 static const struct intel_device_info intel_geminilake_info = {
 570         GEN9_LP_FEATURES,
 571         PLATFORM(INTEL_GEMINILAKE),
 572         .ddb_size = 1024,
 573         GLK_COLORS,
 574 };
 575
 576 #define KBL_PLATFORM \
 577         GEN9_FEATURES, \
 578         PLATFORM(INTEL_KABYLAKE)
 579
 580 static const struct intel_device_info intel_kabylake_gt1_info = {
 581         KBL_PLATFORM,
 582         .gt = 1,
 583 };
 584
 585 static const struct intel_device_info intel_kabylake_gt2_info = {
 586         KBL_PLATFORM,
 587         .gt = 2,
 588 };
 589
 590 static const struct intel_device_info intel_kabylake_gt3_info = {
 591         KBL_PLATFORM,
 592         .gt = 3,
 593         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 594 };
 595
 596 #define CFL_PLATFORM \
 597         GEN9_FEATURES, \
 598         PLATFORM(INTEL_COFFEELAKE)
 599
 600 static const struct intel_device_info intel_coffeelake_gt1_info = {
 601         CFL_PLATFORM,
 602         .gt = 1,
 603 };
 604
 605 static const struct intel_device_info intel_coffeelake_gt2_info = {
 606         CFL_PLATFORM,
 607         .gt = 2,
 608 };
 609
 610 static const struct intel_device_info intel_coffeelake_gt3_info = {
 611         CFL_PLATFORM,
 612         .gt = 3,
 613         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 614 };
 615
 616 #define GEN10_FEATURES \
 617         GEN9_FEATURES, \
 618         GEN(10), \
 619         .ddb_size = 1024, \
 620         .has_coherent_ggtt = false, \
 621         GLK_COLORS
 622
 623 static const struct intel_device_info intel_cannonlake_info = {
 624         GEN10_FEATURES,
 625         PLATFORM(INTEL_CANNONLAKE),
 626         .gt = 2,
 627 };
 628
 629 #define GEN11_FEATURES \
 630         GEN10_FEATURES, \
 631         .pipe_offsets = { \
 632                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 633                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 634                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 635                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 636                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 637                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 638         }, \
 639         .trans_offsets = { \
 640                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 641                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 642                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 643                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 644                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 645                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 646         }, \
 647         GEN(11), \
 648         .ddb_size = 2048, \
 649         .has_logical_ring_elsq = 1
 650
 651 static const struct intel_device_info intel_icelake_11_info = {
 652         GEN11_FEATURES,
 653         PLATFORM(INTEL_ICELAKE),
 654         .is_alpha_support = 1,
 655         .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 656 };
 657
 658 #undef GEN
 659 #undef PLATFORM
 660
 661 /*
 662  * Make sure any device matches here are from most specific to most
 663  * general.  For example, since the Quanta match is based on the subsystem
 664  * and subvendor IDs, we need it to come before the more general IVB
 665  * PCI ID matches, otherwise we'll use the wrong info struct above.
 666  */
 667 static const struct pci_device_id pciidlist[] = {
 668         INTEL_I830_IDS(&intel_i830_info),
 669         INTEL_I845G_IDS(&intel_i845g_info),
 670         INTEL_I85X_IDS(&intel_i85x_info),
 671         INTEL_I865G_IDS(&intel_i865g_info),
 672         INTEL_I915G_IDS(&intel_i915g_info),
 673         INTEL_I915GM_IDS(&intel_i915gm_info),
 674         INTEL_I945G_IDS(&intel_i945g_info),
 675         INTEL_I945GM_IDS(&intel_i945gm_info),
 676         INTEL_I965G_IDS(&intel_i965g_info),
 677         INTEL_G33_IDS(&intel_g33_info),
 678         INTEL_I965GM_IDS(&intel_i965gm_info),
 679         INTEL_GM45_IDS(&intel_gm45_info),
 680         INTEL_G45_IDS(&intel_g45_info),
 681         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 682         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 683         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 684         INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 685         INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 686         INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 687         INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 688         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 689         INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 690         INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 691         INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 692         INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
 693         INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 694         INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 695         INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
 696         INTEL_VLV_IDS(&intel_valleyview_info),
 697         INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 698         INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 699         INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 700         INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
 701         INTEL_CHV_IDS(&intel_cherryview_info),
 702         INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 703         INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 704         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 705         INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
 706         INTEL_BXT_IDS(&intel_broxton_info),
 707         INTEL_GLK_IDS(&intel_geminilake_info),
 708         INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 709         INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 710         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 711         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 712         INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 713         INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 714         INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 715         INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
 716         INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
 717         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 718         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 719         INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 720         INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 721         INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
 722         INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 723         INTEL_CNL_IDS(&intel_cannonlake_info),
 724         INTEL_ICL_11_IDS(&intel_icelake_11_info),
 725         {0, 0, 0}
 726 };
 727 MODULE_DEVICE_TABLE(pci, pciidlist);
 728
 729 static void i915_pci_remove(struct pci_dev *pdev)
 730 {
 731         struct drm_device *dev;
 732
 733         dev = pci_get_drvdata(pdev);
 734         if (!dev) /* driver load aborted, nothing to cleanup */
 735                 return;
 736
 737         i915_driver_unload(dev);
 738         drm_dev_put(dev);
 739
 740         pci_set_drvdata(pdev, NULL);
 741 }
 742
 743 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 744 {
 745         struct intel_device_info *intel_info =
 746                 (struct intel_device_info *) ent->driver_data;
 747         int err;
 748
 749         if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
 750                 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 751                          "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 752                          "to enable support in this kernel version, or check for kernel updates.\n");
 753                 return -ENODEV;
 754         }
 755
 756         /* Only bind to function 0 of the device. Early generations
 757          * used function 1 as a placeholder for multi-head. This causes
 758          * us confusion instead, especially on the systems where both
 759          * functions have the same PCI-ID!
 760          */
 761         if (PCI_FUNC(pdev->devfn))
 762                 return -ENODEV;
 763
 764         /*
 765          * apple-gmux is needed on dual GPU MacBook Pro
 766          * to probe the panel if we're the inactive GPU.
 767          */
 768         if (vga_switcheroo_client_probe_defer(pdev))
 769                 return -EPROBE_DEFER;
 770
 771         err = i915_driver_load(pdev, ent);
 772         if (err)
 773                 return err;
 774
 775         if (i915_inject_load_failure()) {
 776                 i915_pci_remove(pdev);
 777                 return -ENODEV;
 778         }
 779
 780         err = i915_live_selftests(pdev);
 781         if (err) {
 782                 i915_pci_remove(pdev);
 783                 return err > 0 ? -ENOTTY : err;
 784         }
 785
 786         return 0;
 787 }
 788
 789 static struct pci_driver i915_pci_driver = {
 790         .name = DRIVER_NAME,
 791         .id_table = pciidlist,
 792         .probe = i915_pci_probe,
 793         .remove = i915_pci_remove,
 794         .driver.pm = &i915_pm_ops,
 795 };
 796
 797 static int __init i915_init(void)
 798 {
 799         bool use_kms = true;
 800         int err;
 801
 802         i915_global_active_init();
 803
 804         err = i915_mock_selftests();
 805         if (err)
 806                 return err > 0 ? 0 : err;
 807
 808         /*
 809          * Enable KMS by default, unless explicitly overriden by
 810          * either the i915.modeset prarameter or by the
 811          * vga_text_mode_force boot option.
 812          */
 813
 814         if (i915_modparams.modeset == 0)
 815                 use_kms = false;
 816
 817         if (vgacon_text_force() && i915_modparams.modeset == -1)
 818                 use_kms = false;
 819
 820         if (!use_kms) {
 821                 /* Silently fail loading to not upset userspace. */
 822                 DRM_DEBUG_DRIVER("KMS disabled.\n");
 823                 return 0;
 824         }
 825
 826         return pci_register_driver(&i915_pci_driver);
 827 }
 828
 829 static void __exit i915_exit(void)
 830 {
 831         if (!i915_pci_driver.driver.owner)
 832                 return;
 833
 834         pci_unregister_driver(&i915_pci_driver);
 835         i915_global_active_exit();
 836 }
 837
 838 module_init(i915_init);
 839 module_exit(i915_exit);
 840
 841 MODULE_AUTHOR("Tungsten Graphics, Inc.");
 842 MODULE_AUTHOR("Intel Corporation");
 843
 844 MODULE_DESCRIPTION(DRIVER_DESC);
 845 MODULE_LICENSE("GPL and additional rights");